Component description for ADC. More...

Data Structures
union	ADC_CTRLA_Type

union	ADC_EVCTRL_Type

union	ADC_DBGCTRL_Type

union	ADC_INPUTCTRL_Type

union	ADC_CTRLB_Type

union	ADC_REFCTRL_Type

union	ADC_AVGCTRL_Type

union	ADC_SAMPCTRL_Type

union	ADC_WINLT_Type

union	ADC_WINUT_Type

union	ADC_GAINCORR_Type

union	ADC_OFFSETCORR_Type

union	ADC_SWTRIG_Type

union	ADC_INTENCLR_Type

union	ADC_INTENSET_Type

union	ADC_INTFLAG_Type

union	ADC_STATUS_Type

union	ADC_SYNCBUSY_Type

union	ADC_DSEQDATA_Type

union	ADC_DSEQCTRL_Type

union	ADC_DSEQSTAT_Type

union	ADC_RESULT_Type

union	ADC_RESS_Type

union	ADC_CALIB_Type

struct	Adc
	ADC hardware registers. More...

Macros
#define	ADC_U2500

#define	REV_ADC 0x100

#define	ADC_CTRLA_OFFSET 0x00
	(ADC_CTRLA offset) Control A

#define	ADC_CTRLA_RESETVALUE _U_(0x0000)
	(ADC_CTRLA reset_value) Control A

#define	ADC_CTRLA_SWRST_Pos 0
	(ADC_CTRLA) Software Reset

#define	ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos)

#define	ADC_CTRLA_ENABLE_Pos 1
	(ADC_CTRLA) Enable

#define	ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos)

#define	ADC_CTRLA_DUALSEL_Pos 3
	(ADC_CTRLA) Dual Mode Trigger Selection

#define	ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos)

#define	ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos))

#define	ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0)
	(ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs

#define	ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1)
	(ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1

#define	ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos)

#define	ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos)

#define	ADC_CTRLA_SLAVEEN_Pos 5
	(ADC_CTRLA) Slave Enable

#define	ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos)

#define	ADC_CTRLA_RUNSTDBY_Pos 6
	(ADC_CTRLA) Run in Standby

#define	ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)

#define	ADC_CTRLA_ONDEMAND_Pos 7
	(ADC_CTRLA) On Demand Control

#define	ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos)

#define	ADC_CTRLA_PRESCALER_Pos 8
	(ADC_CTRLA) Prescaler Configuration

#define	ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos)

#define	ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos))

#define	ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0)
	(ADC_CTRLA) Peripheral clock divided by 2

#define	ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1)
	(ADC_CTRLA) Peripheral clock divided by 4

#define	ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2)
	(ADC_CTRLA) Peripheral clock divided by 8

#define	ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3)
	(ADC_CTRLA) Peripheral clock divided by 16

#define	ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4)
	(ADC_CTRLA) Peripheral clock divided by 32

#define	ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5)
	(ADC_CTRLA) Peripheral clock divided by 64

#define	ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6)
	(ADC_CTRLA) Peripheral clock divided by 128

#define	ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7)
	(ADC_CTRLA) Peripheral clock divided by 256

#define	ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos)

#define	ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos)

#define	ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos)

#define	ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos)

#define	ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos)

#define	ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos)

#define	ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos)

#define	ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos)

#define	ADC_CTRLA_R2R_Pos 15
	(ADC_CTRLA) Rail to Rail Operation Enable

#define	ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos)

#define	ADC_CTRLA_MASK _U_(0x87FB)
	(ADC_CTRLA) MASK Register

#define	ADC_EVCTRL_OFFSET 0x02
	(ADC_EVCTRL offset) Event Control

#define	ADC_EVCTRL_RESETVALUE _U_(0x00)
	(ADC_EVCTRL reset_value) Event Control

#define	ADC_EVCTRL_FLUSHEI_Pos 0
	(ADC_EVCTRL) Flush Event Input Enable

#define	ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos)

#define	ADC_EVCTRL_STARTEI_Pos 1
	(ADC_EVCTRL) Start Conversion Event Input Enable

#define	ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos)

#define	ADC_EVCTRL_FLUSHINV_Pos 2
	(ADC_EVCTRL) Flush Event Invert Enable

#define	ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos)

#define	ADC_EVCTRL_STARTINV_Pos 3
	(ADC_EVCTRL) Start Conversion Event Invert Enable

#define	ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos)

#define	ADC_EVCTRL_RESRDYEO_Pos 4
	(ADC_EVCTRL) Result Ready Event Out

#define	ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)

#define	ADC_EVCTRL_WINMONEO_Pos 5
	(ADC_EVCTRL) Window Monitor Event Out

#define	ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos)

#define	ADC_EVCTRL_MASK _U_(0x3F)
	(ADC_EVCTRL) MASK Register

#define	ADC_DBGCTRL_OFFSET 0x03
	(ADC_DBGCTRL offset) Debug Control

#define	ADC_DBGCTRL_RESETVALUE _U_(0x00)
	(ADC_DBGCTRL reset_value) Debug Control

#define	ADC_DBGCTRL_DBGRUN_Pos 0
	(ADC_DBGCTRL) Debug Run

#define	ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)

#define	ADC_DBGCTRL_MASK _U_(0x01)
	(ADC_DBGCTRL) MASK Register

#define	ADC_INPUTCTRL_OFFSET 0x04
	(ADC_INPUTCTRL offset) Input Control

#define	ADC_INPUTCTRL_RESETVALUE _U_(0x0000)
	(ADC_INPUTCTRL reset_value) Input Control

#define	ADC_INPUTCTRL_MUXPOS_Pos 0
	(ADC_INPUTCTRL) Positive Mux Input Selection

#define	ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))

#define	ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0)
	(ADC_INPUTCTRL) ADC AIN0 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1)
	(ADC_INPUTCTRL) ADC AIN1 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2)
	(ADC_INPUTCTRL) ADC AIN2 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3)
	(ADC_INPUTCTRL) ADC AIN3 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4)
	(ADC_INPUTCTRL) ADC AIN4 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5)
	(ADC_INPUTCTRL) ADC AIN5 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6)
	(ADC_INPUTCTRL) ADC AIN6 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7)
	(ADC_INPUTCTRL) ADC AIN7 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8)
	(ADC_INPUTCTRL) ADC AIN8 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9)
	(ADC_INPUTCTRL) ADC AIN9 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA)
	(ADC_INPUTCTRL) ADC AIN10 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB)
	(ADC_INPUTCTRL) ADC AIN11 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC)
	(ADC_INPUTCTRL) ADC AIN12 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD)
	(ADC_INPUTCTRL) ADC AIN13 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE)
	(ADC_INPUTCTRL) ADC AIN14 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF)
	(ADC_INPUTCTRL) ADC AIN15 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10)
	(ADC_INPUTCTRL) ADC AIN16 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11)
	(ADC_INPUTCTRL) ADC AIN17 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12)
	(ADC_INPUTCTRL) ADC AIN18 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13)
	(ADC_INPUTCTRL) ADC AIN19 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14)
	(ADC_INPUTCTRL) ADC AIN20 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15)
	(ADC_INPUTCTRL) ADC AIN21 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16)
	(ADC_INPUTCTRL) ADC AIN22 Pin

#define	ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17)
	(ADC_INPUTCTRL) ADC AIN23 Pin

#define	ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18)
	(ADC_INPUTCTRL) 1/4 Scaled Core Supply

#define	ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19)
	(ADC_INPUTCTRL) 1/4 Scaled VBAT Supply

#define	ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A)
	(ADC_INPUTCTRL) 1/4 Scaled I/O Supply

#define	ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B)
	(ADC_INPUTCTRL) Bandgap Voltage

#define	ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C)
	(ADC_INPUTCTRL) Temperature Sensor

#define	ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D)
	(ADC_INPUTCTRL) Temperature Sensor

#define	ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E)
	(ADC_INPUTCTRL) DAC Output

#define	ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F)
	(ADC_INPUTCTRL) PTC output (only on ADC0)

#define	ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos)

#define	ADC_INPUTCTRL_DIFFMODE_Pos 7
	(ADC_INPUTCTRL) Differential Mode

#define	ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos)

#define	ADC_INPUTCTRL_MUXNEG_Pos 8
	(ADC_INPUTCTRL) Negative Mux Input Selection

#define	ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)

#define	ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))

#define	ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0)
	(ADC_INPUTCTRL) ADC AIN0 Pin

#define	ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1)
	(ADC_INPUTCTRL) ADC AIN1 Pin

#define	ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2)
	(ADC_INPUTCTRL) ADC AIN2 Pin

#define	ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3)
	(ADC_INPUTCTRL) ADC AIN3 Pin

#define	ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4)
	(ADC_INPUTCTRL) ADC AIN4 Pin

#define	ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5)
	(ADC_INPUTCTRL) ADC AIN5 Pin

#define	ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6)
	(ADC_INPUTCTRL) ADC AIN6 Pin

#define	ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7)
	(ADC_INPUTCTRL) ADC AIN7 Pin

#define	ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18)
	(ADC_INPUTCTRL) Internal Ground

#define	ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)

#define	ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)

#define	ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)

#define	ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)

#define	ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)

#define	ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)

#define	ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)

#define	ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)

#define	ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)

#define	ADC_INPUTCTRL_DSEQSTOP_Pos 15
	(ADC_INPUTCTRL) Stop DMA Sequencing

#define	ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos)

#define	ADC_INPUTCTRL_MASK _U_(0x9F9F)
	(ADC_INPUTCTRL) MASK Register

#define	ADC_CTRLB_OFFSET 0x06
	(ADC_CTRLB offset) Control B

#define	ADC_CTRLB_RESETVALUE _U_(0x0000)
	(ADC_CTRLB reset_value) Control B

#define	ADC_CTRLB_LEFTADJ_Pos 0
	(ADC_CTRLB) Left-Adjusted Result

#define	ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos)

#define	ADC_CTRLB_FREERUN_Pos 1
	(ADC_CTRLB) Free Running Mode

#define	ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos)

#define	ADC_CTRLB_CORREN_Pos 2
	(ADC_CTRLB) Digital Correction Logic Enable

#define	ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos)

#define	ADC_CTRLB_RESSEL_Pos 3
	(ADC_CTRLB) Conversion Result Resolution

#define	ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos)

#define	ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))

#define	ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0)
	(ADC_CTRLB) 12-bit result

#define	ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1)
	(ADC_CTRLB) For averaging mode output

#define	ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2)
	(ADC_CTRLB) 10-bit result

#define	ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3)
	(ADC_CTRLB) 8-bit result

#define	ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)

#define	ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)

#define	ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)

#define	ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)

#define	ADC_CTRLB_WINMODE_Pos 8
	(ADC_CTRLB) Window Monitor Mode

#define	ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos)

#define	ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos))

#define	ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0)
	(ADC_CTRLB) No window mode (default)

#define	ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1)
	(ADC_CTRLB) RESULT > WINLT

#define	ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2)
	(ADC_CTRLB) RESULT < WINUT

#define	ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3)
	(ADC_CTRLB) WINLT < RESULT < WINUT

#define	ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4)
	(ADC_CTRLB) !(WINLT < RESULT < WINUT)

#define	ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos)

#define	ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos)

#define	ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos)

#define	ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos)

#define	ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos)

#define	ADC_CTRLB_WINSS_Pos 11
	(ADC_CTRLB) Window Single Sample

#define	ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos)

#define	ADC_CTRLB_MASK _U_(0x0F1F)
	(ADC_CTRLB) MASK Register

#define	ADC_REFCTRL_OFFSET 0x08
	(ADC_REFCTRL offset) Reference Control

#define	ADC_REFCTRL_RESETVALUE _U_(0x00)
	(ADC_REFCTRL reset_value) Reference Control

#define	ADC_REFCTRL_REFSEL_Pos 0
	(ADC_REFCTRL) Reference Selection

#define	ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos)

#define	ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))

#define	ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0)
	(ADC_REFCTRL) Internal Bandgap Reference

#define	ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2)
	(ADC_REFCTRL) 1/2 VDDANA

#define	ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3)
	(ADC_REFCTRL) VDDANA

#define	ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4)
	(ADC_REFCTRL) External Reference

#define	ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5)
	(ADC_REFCTRL) External Reference

#define	ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6)
	(ADC_REFCTRL) External Reference (only on ADC1)

#define	ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos)

#define	ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)

#define	ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)

#define	ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)

#define	ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)

#define	ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos)

#define	ADC_REFCTRL_REFCOMP_Pos 7
	(ADC_REFCTRL) Reference Buffer Offset Compensation Enable

#define	ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos)

#define	ADC_REFCTRL_MASK _U_(0x8F)
	(ADC_REFCTRL) MASK Register

#define	ADC_AVGCTRL_OFFSET 0x0A
	(ADC_AVGCTRL offset) Average Control

#define	ADC_AVGCTRL_RESETVALUE _U_(0x00)
	(ADC_AVGCTRL reset_value) Average Control

#define	ADC_AVGCTRL_SAMPLENUM_Pos 0
	(ADC_AVGCTRL) Number of Samples to be Collected

#define	ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)

#define	ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))

#define	ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0)
	(ADC_AVGCTRL) 1 sample

#define	ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1)
	(ADC_AVGCTRL) 2 samples

#define	ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2)
	(ADC_AVGCTRL) 4 samples

#define	ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3)
	(ADC_AVGCTRL) 8 samples

#define	ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4)
	(ADC_AVGCTRL) 16 samples

#define	ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5)
	(ADC_AVGCTRL) 32 samples

#define	ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6)
	(ADC_AVGCTRL) 64 samples

#define	ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7)
	(ADC_AVGCTRL) 128 samples

#define	ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8)
	(ADC_AVGCTRL) 256 samples

#define	ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9)
	(ADC_AVGCTRL) 512 samples

#define	ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA)
	(ADC_AVGCTRL) 1024 samples

#define	ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)

#define	ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)

#define	ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)

#define	ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)

#define	ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)

#define	ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)

#define	ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)

#define	ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)

#define	ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)

#define	ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)

#define	ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)

#define	ADC_AVGCTRL_ADJRES_Pos 4
	(ADC_AVGCTRL) Adjusting Result / Division Coefficient

#define	ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos)

#define	ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))

#define	ADC_AVGCTRL_MASK _U_(0x7F)
	(ADC_AVGCTRL) MASK Register

#define	ADC_SAMPCTRL_OFFSET 0x0B
	(ADC_SAMPCTRL offset) Sample Time Control

#define	ADC_SAMPCTRL_RESETVALUE _U_(0x00)
	(ADC_SAMPCTRL reset_value) Sample Time Control

#define	ADC_SAMPCTRL_SAMPLEN_Pos 0
	(ADC_SAMPCTRL) Sampling Time Length

#define	ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)

#define	ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))

#define	ADC_SAMPCTRL_OFFCOMP_Pos 7
	(ADC_SAMPCTRL) Comparator Offset Compensation Enable

#define	ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos)

#define	ADC_SAMPCTRL_MASK _U_(0xBF)
	(ADC_SAMPCTRL) MASK Register

#define	ADC_WINLT_OFFSET 0x0C
	(ADC_WINLT offset) Window Monitor Lower Threshold

#define	ADC_WINLT_RESETVALUE _U_(0x0000)
	(ADC_WINLT reset_value) Window Monitor Lower Threshold

#define	ADC_WINLT_WINLT_Pos 0
	(ADC_WINLT) Window Lower Threshold

#define	ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos)

#define	ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))

#define	ADC_WINLT_MASK _U_(0xFFFF)
	(ADC_WINLT) MASK Register

#define	ADC_WINUT_OFFSET 0x0E
	(ADC_WINUT offset) Window Monitor Upper Threshold

#define	ADC_WINUT_RESETVALUE _U_(0x0000)
	(ADC_WINUT reset_value) Window Monitor Upper Threshold

#define	ADC_WINUT_WINUT_Pos 0
	(ADC_WINUT) Window Upper Threshold

#define	ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos)

#define	ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))

#define	ADC_WINUT_MASK _U_(0xFFFF)
	(ADC_WINUT) MASK Register

#define	ADC_GAINCORR_OFFSET 0x10
	(ADC_GAINCORR offset) Gain Correction

#define	ADC_GAINCORR_RESETVALUE _U_(0x0000)
	(ADC_GAINCORR reset_value) Gain Correction

#define	ADC_GAINCORR_GAINCORR_Pos 0
	(ADC_GAINCORR) Gain Correction Value

#define	ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)

#define	ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))

#define	ADC_GAINCORR_MASK _U_(0x0FFF)
	(ADC_GAINCORR) MASK Register

#define	ADC_OFFSETCORR_OFFSET 0x12
	(ADC_OFFSETCORR offset) Offset Correction

#define	ADC_OFFSETCORR_RESETVALUE _U_(0x0000)
	(ADC_OFFSETCORR reset_value) Offset Correction

#define	ADC_OFFSETCORR_OFFSETCORR_Pos 0
	(ADC_OFFSETCORR) Offset Correction Value

#define	ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)

#define	ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))

#define	ADC_OFFSETCORR_MASK _U_(0x0FFF)
	(ADC_OFFSETCORR) MASK Register

#define	ADC_SWTRIG_OFFSET 0x14
	(ADC_SWTRIG offset) Software Trigger

#define	ADC_SWTRIG_RESETVALUE _U_(0x00)
	(ADC_SWTRIG reset_value) Software Trigger

#define	ADC_SWTRIG_FLUSH_Pos 0
	(ADC_SWTRIG) ADC Conversion Flush

#define	ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos)

#define	ADC_SWTRIG_START_Pos 1
	(ADC_SWTRIG) Start ADC Conversion

#define	ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos)

#define	ADC_SWTRIG_MASK _U_(0x03)
	(ADC_SWTRIG) MASK Register

#define	ADC_INTENCLR_OFFSET 0x2C
	(ADC_INTENCLR offset) Interrupt Enable Clear

#define	ADC_INTENCLR_RESETVALUE _U_(0x00)
	(ADC_INTENCLR reset_value) Interrupt Enable Clear

#define	ADC_INTENCLR_RESRDY_Pos 0
	(ADC_INTENCLR) Result Ready Interrupt Disable

#define	ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos)

#define	ADC_INTENCLR_OVERRUN_Pos 1
	(ADC_INTENCLR) Overrun Interrupt Disable

#define	ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos)

#define	ADC_INTENCLR_WINMON_Pos 2
	(ADC_INTENCLR) Window Monitor Interrupt Disable

#define	ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos)

#define	ADC_INTENCLR_MASK _U_(0x07)
	(ADC_INTENCLR) MASK Register

#define	ADC_INTENSET_OFFSET 0x2D
	(ADC_INTENSET offset) Interrupt Enable Set

#define	ADC_INTENSET_RESETVALUE _U_(0x00)
	(ADC_INTENSET reset_value) Interrupt Enable Set

#define	ADC_INTENSET_RESRDY_Pos 0
	(ADC_INTENSET) Result Ready Interrupt Enable

#define	ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos)

#define	ADC_INTENSET_OVERRUN_Pos 1
	(ADC_INTENSET) Overrun Interrupt Enable

#define	ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos)

#define	ADC_INTENSET_WINMON_Pos 2
	(ADC_INTENSET) Window Monitor Interrupt Enable

#define	ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos)

#define	ADC_INTENSET_MASK _U_(0x07)
	(ADC_INTENSET) MASK Register

#define	ADC_INTFLAG_OFFSET 0x2E
	(ADC_INTFLAG offset) Interrupt Flag Status and Clear

#define	ADC_INTFLAG_RESETVALUE _U_(0x00)
	(ADC_INTFLAG reset_value) Interrupt Flag Status and Clear

#define	ADC_INTFLAG_RESRDY_Pos 0
	(ADC_INTFLAG) Result Ready Interrupt Flag

#define	ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos)

#define	ADC_INTFLAG_OVERRUN_Pos 1
	(ADC_INTFLAG) Overrun Interrupt Flag

#define	ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos)

#define	ADC_INTFLAG_WINMON_Pos 2
	(ADC_INTFLAG) Window Monitor Interrupt Flag

#define	ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos)

#define	ADC_INTFLAG_MASK _U_(0x07)
	(ADC_INTFLAG) MASK Register

#define	ADC_STATUS_OFFSET 0x2F
	(ADC_STATUS offset) Status

#define	ADC_STATUS_RESETVALUE _U_(0x00)
	(ADC_STATUS reset_value) Status

#define	ADC_STATUS_ADCBUSY_Pos 0
	(ADC_STATUS) ADC Busy Status

#define	ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos)

#define	ADC_STATUS_WCC_Pos 2
	(ADC_STATUS) Window Comparator Counter

#define	ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos)

#define	ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos))

#define	ADC_STATUS_MASK _U_(0xFD)
	(ADC_STATUS) MASK Register

#define	ADC_SYNCBUSY_OFFSET 0x30
	(ADC_SYNCBUSY offset) Synchronization Busy

#define	ADC_SYNCBUSY_RESETVALUE _U_(0x00000000)
	(ADC_SYNCBUSY reset_value) Synchronization Busy

#define	ADC_SYNCBUSY_SWRST_Pos 0
	(ADC_SYNCBUSY) SWRST Synchronization Busy

#define	ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos)

#define	ADC_SYNCBUSY_ENABLE_Pos 1
	(ADC_SYNCBUSY) ENABLE Synchronization Busy

#define	ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos)

#define	ADC_SYNCBUSY_INPUTCTRL_Pos 2
	(ADC_SYNCBUSY) Input Control Synchronization Busy

#define	ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos)

#define	ADC_SYNCBUSY_CTRLB_Pos 3
	(ADC_SYNCBUSY) Control B Synchronization Busy

#define	ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos)

#define	ADC_SYNCBUSY_REFCTRL_Pos 4
	(ADC_SYNCBUSY) Reference Control Synchronization Busy

#define	ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos)

#define	ADC_SYNCBUSY_AVGCTRL_Pos 5
	(ADC_SYNCBUSY) Average Control Synchronization Busy

#define	ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos)

#define	ADC_SYNCBUSY_SAMPCTRL_Pos 6
	(ADC_SYNCBUSY) Sampling Time Control Synchronization Busy

#define	ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos)

#define	ADC_SYNCBUSY_WINLT_Pos 7
	(ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy

#define	ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos)

#define	ADC_SYNCBUSY_WINUT_Pos 8
	(ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy

#define	ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos)

#define	ADC_SYNCBUSY_GAINCORR_Pos 9
	(ADC_SYNCBUSY) Gain Correction Synchronization Busy

#define	ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos)

#define	ADC_SYNCBUSY_OFFSETCORR_Pos 10
	(ADC_SYNCBUSY) Offset Correction Synchronization Busy

#define	ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos)

#define	ADC_SYNCBUSY_SWTRIG_Pos 11
	(ADC_SYNCBUSY) Software Trigger Synchronization Busy

#define	ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos)

#define	ADC_SYNCBUSY_MASK _U_(0x00000FFF)
	(ADC_SYNCBUSY) MASK Register

#define	ADC_DSEQDATA_OFFSET 0x34
	(ADC_DSEQDATA offset) DMA Sequencial Data

#define	ADC_DSEQDATA_RESETVALUE _U_(0x00000000)
	(ADC_DSEQDATA reset_value) DMA Sequencial Data

#define	ADC_DSEQDATA_DATA_Pos 0
	(ADC_DSEQDATA) DMA Sequential Data

#define	ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos)

#define	ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos))

#define	ADC_DSEQDATA_MASK _U_(0xFFFFFFFF)
	(ADC_DSEQDATA) MASK Register

#define	ADC_DSEQCTRL_OFFSET 0x38
	(ADC_DSEQCTRL offset) DMA Sequential Control

#define	ADC_DSEQCTRL_RESETVALUE _U_(0x00000000)
	(ADC_DSEQCTRL reset_value) DMA Sequential Control

#define	ADC_DSEQCTRL_INPUTCTRL_Pos 0
	(ADC_DSEQCTRL) Input Control

#define	ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos)

#define	ADC_DSEQCTRL_CTRLB_Pos 1
	(ADC_DSEQCTRL) Control B

#define	ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos)

#define	ADC_DSEQCTRL_REFCTRL_Pos 2
	(ADC_DSEQCTRL) Reference Control

#define	ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos)

#define	ADC_DSEQCTRL_AVGCTRL_Pos 3
	(ADC_DSEQCTRL) Average Control

#define	ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos)

#define	ADC_DSEQCTRL_SAMPCTRL_Pos 4
	(ADC_DSEQCTRL) Sampling Time Control

#define	ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos)

#define	ADC_DSEQCTRL_WINLT_Pos 5
	(ADC_DSEQCTRL) Window Monitor Lower Threshold

#define	ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos)

#define	ADC_DSEQCTRL_WINUT_Pos 6
	(ADC_DSEQCTRL) Window Monitor Upper Threshold

#define	ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos)

#define	ADC_DSEQCTRL_GAINCORR_Pos 7
	(ADC_DSEQCTRL) Gain Correction

#define	ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos)

#define	ADC_DSEQCTRL_OFFSETCORR_Pos 8
	(ADC_DSEQCTRL) Offset Correction

#define	ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos)

#define	ADC_DSEQCTRL_AUTOSTART_Pos 31
	(ADC_DSEQCTRL) ADC Auto-Start Conversion

#define	ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos)

#define	ADC_DSEQCTRL_MASK _U_(0x800001FF)
	(ADC_DSEQCTRL) MASK Register

#define	ADC_DSEQSTAT_OFFSET 0x3C
	(ADC_DSEQSTAT offset) DMA Sequencial Status

#define	ADC_DSEQSTAT_RESETVALUE _U_(0x00000000)
	(ADC_DSEQSTAT reset_value) DMA Sequencial Status

#define	ADC_DSEQSTAT_INPUTCTRL_Pos 0
	(ADC_DSEQSTAT) Input Control

#define	ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos)

#define	ADC_DSEQSTAT_CTRLB_Pos 1
	(ADC_DSEQSTAT) Control B

#define	ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos)

#define	ADC_DSEQSTAT_REFCTRL_Pos 2
	(ADC_DSEQSTAT) Reference Control

#define	ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos)

#define	ADC_DSEQSTAT_AVGCTRL_Pos 3
	(ADC_DSEQSTAT) Average Control

#define	ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos)

#define	ADC_DSEQSTAT_SAMPCTRL_Pos 4
	(ADC_DSEQSTAT) Sampling Time Control

#define	ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos)

#define	ADC_DSEQSTAT_WINLT_Pos 5
	(ADC_DSEQSTAT) Window Monitor Lower Threshold

#define	ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos)

#define	ADC_DSEQSTAT_WINUT_Pos 6
	(ADC_DSEQSTAT) Window Monitor Upper Threshold

#define	ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos)

#define	ADC_DSEQSTAT_GAINCORR_Pos 7
	(ADC_DSEQSTAT) Gain Correction

#define	ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos)

#define	ADC_DSEQSTAT_OFFSETCORR_Pos 8
	(ADC_DSEQSTAT) Offset Correction

#define	ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos)

#define	ADC_DSEQSTAT_BUSY_Pos 31
	(ADC_DSEQSTAT) DMA Sequencing Busy

#define	ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos)

#define	ADC_DSEQSTAT_MASK _U_(0x800001FF)
	(ADC_DSEQSTAT) MASK Register

#define	ADC_RESULT_OFFSET 0x40
	(ADC_RESULT offset) Result Conversion Value

#define	ADC_RESULT_RESETVALUE _U_(0x0000)
	(ADC_RESULT reset_value) Result Conversion Value

#define	ADC_RESULT_RESULT_Pos 0
	(ADC_RESULT) Result Conversion Value

#define	ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos)

#define	ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))

#define	ADC_RESULT_MASK _U_(0xFFFF)
	(ADC_RESULT) MASK Register

#define	ADC_RESS_OFFSET 0x44
	(ADC_RESS offset) Last Sample Result

#define	ADC_RESS_RESETVALUE _U_(0x0000)
	(ADC_RESS reset_value) Last Sample Result

#define	ADC_RESS_RESS_Pos 0
	(ADC_RESS) Last ADC conversion result

#define	ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos)

#define	ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos))

#define	ADC_RESS_MASK _U_(0xFFFF)
	(ADC_RESS) MASK Register

#define	ADC_CALIB_OFFSET 0x48
	(ADC_CALIB offset) Calibration

#define	ADC_CALIB_RESETVALUE _U_(0x0000)
	(ADC_CALIB reset_value) Calibration

#define	ADC_CALIB_BIASCOMP_Pos 0
	(ADC_CALIB) Bias Comparator Scaling

#define	ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos)

#define	ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))

#define	ADC_CALIB_BIASR2R_Pos 4
	(ADC_CALIB) Bias R2R Ampli scaling

#define	ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos)

#define	ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos))

#define	ADC_CALIB_BIASREFBUF_Pos 8
	(ADC_CALIB) Bias Reference Buffer Scaling

#define	ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos)

#define	ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))

#define	ADC_CALIB_MASK _U_(0x0777)
	(ADC_CALIB) MASK Register

Detailed Description

Component description for ADC.

\asf_license_start

Definition in file adc.h.

Data Structures

Macros

Detailed Description