SAME54P20A Test Project
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Instance description for TCC2. More...
Go to the source code of this file.
Macros | |
#define | REG_TCC2_CTRLA (*(RwReg *)0x42000C00UL) |
(TCC2) Control A | |
#define | REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42000C04UL) |
(TCC2) Control B Clear | |
#define | REG_TCC2_CTRLBSET (*(RwReg8 *)0x42000C05UL) |
(TCC2) Control B Set | |
#define | REG_TCC2_SYNCBUSY (*(RoReg *)0x42000C08UL) |
(TCC2) Synchronization Busy | |
#define | REG_TCC2_FCTRLA (*(RwReg *)0x42000C0CUL) |
(TCC2) Recoverable Fault A Configuration | |
#define | REG_TCC2_FCTRLB (*(RwReg *)0x42000C10UL) |
(TCC2) Recoverable Fault B Configuration | |
#define | REG_TCC2_WEXCTRL (*(RwReg *)0x42000C14UL) |
(TCC2) Waveform Extension Configuration | |
#define | REG_TCC2_DRVCTRL (*(RwReg *)0x42000C18UL) |
(TCC2) Driver Control | |
#define | REG_TCC2_DBGCTRL (*(RwReg8 *)0x42000C1EUL) |
(TCC2) Debug Control | |
#define | REG_TCC2_EVCTRL (*(RwReg *)0x42000C20UL) |
(TCC2) Event Control | |
#define | REG_TCC2_INTENCLR (*(RwReg *)0x42000C24UL) |
(TCC2) Interrupt Enable Clear | |
#define | REG_TCC2_INTENSET (*(RwReg *)0x42000C28UL) |
(TCC2) Interrupt Enable Set | |
#define | REG_TCC2_INTFLAG (*(RwReg *)0x42000C2CUL) |
(TCC2) Interrupt Flag Status and Clear | |
#define | REG_TCC2_STATUS (*(RwReg *)0x42000C30UL) |
(TCC2) Status | |
#define | REG_TCC2_COUNT (*(RwReg *)0x42000C34UL) |
(TCC2) Count | |
#define | REG_TCC2_WAVE (*(RwReg *)0x42000C3CUL) |
(TCC2) Waveform Control | |
#define | REG_TCC2_PER (*(RwReg *)0x42000C40UL) |
(TCC2) Period | |
#define | REG_TCC2_CC0 (*(RwReg *)0x42000C44UL) |
(TCC2) Compare and Capture 0 | |
#define | REG_TCC2_CC1 (*(RwReg *)0x42000C48UL) |
(TCC2) Compare and Capture 1 | |
#define | REG_TCC2_CC2 (*(RwReg *)0x42000C4CUL) |
(TCC2) Compare and Capture 2 | |
#define | REG_TCC2_PERBUF (*(RwReg *)0x42000C6CUL) |
(TCC2) Period Buffer | |
#define | REG_TCC2_CCBUF0 (*(RwReg *)0x42000C70UL) |
(TCC2) Compare and Capture Buffer 0 | |
#define | REG_TCC2_CCBUF1 (*(RwReg *)0x42000C74UL) |
(TCC2) Compare and Capture Buffer 1 | |
#define | REG_TCC2_CCBUF2 (*(RwReg *)0x42000C78UL) |
(TCC2) Compare and Capture Buffer 2 | |
#define | TCC2_CC_NUM 3 |
#define | TCC2_DITHERING 0 |
#define | TCC2_DMAC_ID_MC_0 35 |
#define | TCC2_DMAC_ID_MC_1 36 |
#define | TCC2_DMAC_ID_MC_2 37 |
#define | TCC2_DMAC_ID_MC_LSB 35 |
#define | TCC2_DMAC_ID_MC_MSB 37 |
#define | TCC2_DMAC_ID_MC_SIZE 3 |
#define | TCC2_DMAC_ID_OVF 34 |
#define | TCC2_DTI 0 |
#define | TCC2_EXT 1 |
#define | TCC2_GCLK_ID 29 |
#define | TCC2_MASTER_SLAVE_MODE 0 |
#define | TCC2_OTMX 1 |
#define | TCC2_OW_NUM 3 |
#define | TCC2_PG 0 |
#define | TCC2_SIZE 16 |
#define | TCC2_SWAP 0 |
Instance description for TCC2.
Copyright (c) 2019 Microchip Technology Inc.
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Definition in file tcc2.h.