SAME54P20A Test Project
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Instance description for PDEC. More...
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Macros | |
#define | REG_PDEC_CTRLA (*(RwReg *)0x42001C00UL) |
(PDEC) Control A | |
#define | REG_PDEC_CTRLBCLR (*(RwReg8 *)0x42001C04UL) |
(PDEC) Control B Clear | |
#define | REG_PDEC_CTRLBSET (*(RwReg8 *)0x42001C05UL) |
(PDEC) Control B Set | |
#define | REG_PDEC_EVCTRL (*(RwReg16*)0x42001C06UL) |
(PDEC) Event Control | |
#define | REG_PDEC_INTENCLR (*(RwReg8 *)0x42001C08UL) |
(PDEC) Interrupt Enable Clear | |
#define | REG_PDEC_INTENSET (*(RwReg8 *)0x42001C09UL) |
(PDEC) Interrupt Enable Set | |
#define | REG_PDEC_INTFLAG (*(RwReg8 *)0x42001C0AUL) |
(PDEC) Interrupt Flag Status and Clear | |
#define | REG_PDEC_STATUS (*(RwReg16*)0x42001C0CUL) |
(PDEC) Status | |
#define | REG_PDEC_DBGCTRL (*(RwReg8 *)0x42001C0FUL) |
(PDEC) Debug Control | |
#define | REG_PDEC_SYNCBUSY (*(RoReg *)0x42001C10UL) |
(PDEC) Synchronization Status | |
#define | REG_PDEC_PRESC (*(RwReg8 *)0x42001C14UL) |
(PDEC) Prescaler Value | |
#define | REG_PDEC_FILTER (*(RwReg8 *)0x42001C15UL) |
(PDEC) Filter Value | |
#define | REG_PDEC_PRESCBUF (*(RwReg8 *)0x42001C18UL) |
(PDEC) Prescaler Buffer Value | |
#define | REG_PDEC_FILTERBUF (*(RwReg8 *)0x42001C19UL) |
(PDEC) Filter Buffer Value | |
#define | REG_PDEC_COUNT (*(RwReg *)0x42001C1CUL) |
(PDEC) Counter Value | |
#define | REG_PDEC_CC0 (*(RwReg *)0x42001C20UL) |
(PDEC) Channel 0 Compare Value | |
#define | REG_PDEC_CC1 (*(RwReg *)0x42001C24UL) |
(PDEC) Channel 1 Compare Value | |
#define | REG_PDEC_CCBUF0 (*(RwReg *)0x42001C30UL) |
(PDEC) Channel Compare Buffer Value 0 | |
#define | REG_PDEC_CCBUF1 (*(RwReg *)0x42001C34UL) |
(PDEC) Channel Compare Buffer Value 1 | |
#define | PDEC_CC_NUM 2 |
#define | PDEC_GCLK_ID 31 |
Instance description for PDEC.
Copyright (c) 2019 Microchip Technology Inc.
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Definition in file pdec.h.