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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Cmcc Struct Reference</div> </div>
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<p>CMCC APB hardware registers.
<a href="structCmcc.html#details">More...</a></p>
<p><code>#include <<a class="el" href="component_2cmcc_8h_source.html">cmcc.h</a>></code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a2d0b2688a6a949aeb2280ba6afda2c65"><td class="memItemLeft" align="right" valign="top"><a id="a2d0b2688a6a949aeb2280ba6afda2c65"></a>
__I <a class="el" href="unionCMCC__TYPE__Type.html">CMCC_TYPE_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCmcc.html#a2d0b2688a6a949aeb2280ba6afda2c65">TYPE</a></td></tr>
<tr class="memdesc:a2d0b2688a6a949aeb2280ba6afda2c65"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/ 32) Cache Type Register. <br /></td></tr>
<tr class="separator:a2d0b2688a6a949aeb2280ba6afda2c65"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a87b8d25fecb96434c28107857a8fea2d"><td class="memItemLeft" align="right" valign="top"><a id="a87b8d25fecb96434c28107857a8fea2d"></a>
__IO <a class="el" href="unionCMCC__CFG__Type.html">CMCC_CFG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCmcc.html#a87b8d25fecb96434c28107857a8fea2d">CFG</a></td></tr>
<tr class="memdesc:a87b8d25fecb96434c28107857a8fea2d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 32) Cache Configuration Register. <br /></td></tr>
<tr class="separator:a87b8d25fecb96434c28107857a8fea2d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a539558149b21db7c991f0742d30e0481"><td class="memItemLeft" align="right" valign="top"><a id="a539558149b21db7c991f0742d30e0481"></a>
__O <a class="el" href="unionCMCC__CTRL__Type.html">CMCC_CTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCmcc.html#a539558149b21db7c991f0742d30e0481">CTRL</a></td></tr>
<tr class="memdesc:a539558149b21db7c991f0742d30e0481"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 ( /W 32) Cache Control Register. <br /></td></tr>
<tr class="separator:a539558149b21db7c991f0742d30e0481"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2e1006a5b7c2ec83104d7fcdc6766fff"><td class="memItemLeft" align="right" valign="top"><a id="a2e1006a5b7c2ec83104d7fcdc6766fff"></a>
__I <a class="el" href="unionCMCC__SR__Type.html">CMCC_SR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCmcc.html#a2e1006a5b7c2ec83104d7fcdc6766fff">SR</a></td></tr>
<tr class="memdesc:a2e1006a5b7c2ec83104d7fcdc6766fff"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/ 32) Cache Status Register. <br /></td></tr>
<tr class="separator:a2e1006a5b7c2ec83104d7fcdc6766fff"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8f4925ba24d719ab190d4bf241922f0a"><td class="memItemLeft" align="right" valign="top"><a id="a8f4925ba24d719ab190d4bf241922f0a"></a>
__IO <a class="el" href="unionCMCC__LCKWAY__Type.html">CMCC_LCKWAY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCmcc.html#a8f4925ba24d719ab190d4bf241922f0a">LCKWAY</a></td></tr>
<tr class="memdesc:a8f4925ba24d719ab190d4bf241922f0a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/W 32) Cache Lock per Way Register. <br /></td></tr>
<tr class="separator:a8f4925ba24d719ab190d4bf241922f0a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7288c784731d01d3ac32efbf2fa9a0a6"><td class="memItemLeft" align="right" valign="top"><a id="a7288c784731d01d3ac32efbf2fa9a0a6"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0xC]</td></tr>
<tr class="separator:a7288c784731d01d3ac32efbf2fa9a0a6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa33ce67fcc1e3cb34a8bff05455be247"><td class="memItemLeft" align="right" valign="top"><a id="aa33ce67fcc1e3cb34a8bff05455be247"></a>
__O <a class="el" href="unionCMCC__MAINT0__Type.html">CMCC_MAINT0_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCmcc.html#aa33ce67fcc1e3cb34a8bff05455be247">MAINT0</a></td></tr>
<tr class="memdesc:aa33ce67fcc1e3cb34a8bff05455be247"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x20 ( /W 32) Cache Maintenance Register 0. <br /></td></tr>
<tr class="separator:aa33ce67fcc1e3cb34a8bff05455be247"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a76bb07832821d65765bbddecd48b047f"><td class="memItemLeft" align="right" valign="top"><a id="a76bb07832821d65765bbddecd48b047f"></a>
__O <a class="el" href="unionCMCC__MAINT1__Type.html">CMCC_MAINT1_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCmcc.html#a76bb07832821d65765bbddecd48b047f">MAINT1</a></td></tr>
<tr class="memdesc:a76bb07832821d65765bbddecd48b047f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x24 ( /W 32) Cache Maintenance Register 1. <br /></td></tr>
<tr class="separator:a76bb07832821d65765bbddecd48b047f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1304e940b4556471b4a722b67b165a8b"><td class="memItemLeft" align="right" valign="top"><a id="a1304e940b4556471b4a722b67b165a8b"></a>
__IO <a class="el" href="unionCMCC__MCFG__Type.html">CMCC_MCFG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCmcc.html#a1304e940b4556471b4a722b67b165a8b">MCFG</a></td></tr>
<tr class="memdesc:a1304e940b4556471b4a722b67b165a8b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x28 (R/W 32) Cache Monitor Configuration Register. <br /></td></tr>
<tr class="separator:a1304e940b4556471b4a722b67b165a8b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4aadc35cd008a8b59ccbef0afd787cca"><td class="memItemLeft" align="right" valign="top"><a id="a4aadc35cd008a8b59ccbef0afd787cca"></a>
__IO <a class="el" href="unionCMCC__MEN__Type.html">CMCC_MEN_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCmcc.html#a4aadc35cd008a8b59ccbef0afd787cca">MEN</a></td></tr>
<tr class="memdesc:a4aadc35cd008a8b59ccbef0afd787cca"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x2C (R/W 32) Cache Monitor Enable Register. <br /></td></tr>
<tr class="separator:a4aadc35cd008a8b59ccbef0afd787cca"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0c4e011510e5e06185b19848f81dd0c9"><td class="memItemLeft" align="right" valign="top"><a id="a0c4e011510e5e06185b19848f81dd0c9"></a>
__O <a class="el" href="unionCMCC__MCTRL__Type.html">CMCC_MCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCmcc.html#a0c4e011510e5e06185b19848f81dd0c9">MCTRL</a></td></tr>
<tr class="memdesc:a0c4e011510e5e06185b19848f81dd0c9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 ( /W 32) Cache Monitor Control Register. <br /></td></tr>
<tr class="separator:a0c4e011510e5e06185b19848f81dd0c9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a38272d8b430ad87ce4552ac7236255b6"><td class="memItemLeft" align="right" valign="top"><a id="a38272d8b430ad87ce4552ac7236255b6"></a>
__I <a class="el" href="unionCMCC__MSR__Type.html">CMCC_MSR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structCmcc.html#a38272d8b430ad87ce4552ac7236255b6">MSR</a></td></tr>
<tr class="memdesc:a38272d8b430ad87ce4552ac7236255b6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x34 (R/ 32) Cache Monitor Status Register. <br /></td></tr>
<tr class="separator:a38272d8b430ad87ce4552ac7236255b6"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>CMCC APB hardware registers. </p>
<p class="definition">Definition at line <a class="el" href="component_2cmcc_8h_source.html#l00339">339</a> of file <a class="el" href="component_2cmcc_8h_source.html">cmcc.h</a>.</p>
</div><hr/>The documentation for this struct was generated from the following file:<ul>
<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2cmcc_8h_source.html">cmcc.h</a></li>
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