Component description for RTC. More...

Data Structures
union	RTC_MODE0_CTRLA_Type

union	RTC_MODE1_CTRLA_Type

union	RTC_MODE2_CTRLA_Type

union	RTC_MODE0_CTRLB_Type

union	RTC_MODE1_CTRLB_Type

union	RTC_MODE2_CTRLB_Type

union	RTC_MODE0_EVCTRL_Type

union	RTC_MODE1_EVCTRL_Type

union	RTC_MODE2_EVCTRL_Type

union	RTC_MODE0_INTENCLR_Type

union	RTC_MODE1_INTENCLR_Type

union	RTC_MODE2_INTENCLR_Type

union	RTC_MODE0_INTENSET_Type

union	RTC_MODE1_INTENSET_Type

union	RTC_MODE2_INTENSET_Type

union	RTC_MODE0_INTFLAG_Type

union	RTC_MODE1_INTFLAG_Type

union	RTC_MODE2_INTFLAG_Type

union	RTC_DBGCTRL_Type

union	RTC_MODE0_SYNCBUSY_Type

union	RTC_MODE1_SYNCBUSY_Type

union	RTC_MODE2_SYNCBUSY_Type

union	RTC_FREQCORR_Type

union	RTC_MODE0_COUNT_Type

union	RTC_MODE1_COUNT_Type

union	RTC_MODE2_CLOCK_Type

union	RTC_MODE1_PER_Type

union	RTC_MODE0_COMP_Type

union	RTC_MODE1_COMP_Type

union	RTC_MODE2_ALARM_Type

union	RTC_MODE2_MASK_Type

union	RTC_GP_Type

union	RTC_TAMPCTRL_Type

union	RTC_MODE0_TIMESTAMP_Type

union	RTC_MODE1_TIMESTAMP_Type

union	RTC_MODE2_TIMESTAMP_Type

union	RTC_TAMPID_Type

union	RTC_BKUP_Type

struct	RtcMode2Alarm
	RtcMode2Alarm hardware registers. More...

struct	RtcMode0
	RTC_MODE0 hardware registers. More...

struct	RtcMode1
	RTC_MODE1 hardware registers. More...

struct	RtcMode2
	RTC_MODE2 hardware registers. More...

union	Rtc

Macros
#define	RTC_U2250

#define	REV_RTC 0x210

#define	RTC_MODE0_CTRLA_OFFSET 0x00
	(RTC_MODE0_CTRLA offset) MODE0 Control A

#define	RTC_MODE0_CTRLA_RESETVALUE _U_(0x0000)
	(RTC_MODE0_CTRLA reset_value) MODE0 Control A

#define	RTC_MODE0_CTRLA_SWRST_Pos 0
	(RTC_MODE0_CTRLA) Software Reset

#define	RTC_MODE0_CTRLA_SWRST (_U_(0x1) << RTC_MODE0_CTRLA_SWRST_Pos)

#define	RTC_MODE0_CTRLA_ENABLE_Pos 1
	(RTC_MODE0_CTRLA) Enable

#define	RTC_MODE0_CTRLA_ENABLE (_U_(0x1) << RTC_MODE0_CTRLA_ENABLE_Pos)

#define	RTC_MODE0_CTRLA_MODE_Pos 2
	(RTC_MODE0_CTRLA) Operating Mode

#define	RTC_MODE0_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE0_CTRLA_MODE_Pos)

#define	RTC_MODE0_CTRLA_MODE(value) (RTC_MODE0_CTRLA_MODE_Msk & ((value) << RTC_MODE0_CTRLA_MODE_Pos))

#define	RTC_MODE0_CTRLA_MODE_COUNT32_Val _U_(0x0)
	(RTC_MODE0_CTRLA) Mode 0: 32-bit Counter

#define	RTC_MODE0_CTRLA_MODE_COUNT16_Val _U_(0x1)
	(RTC_MODE0_CTRLA) Mode 1: 16-bit Counter

#define	RTC_MODE0_CTRLA_MODE_CLOCK_Val _U_(0x2)
	(RTC_MODE0_CTRLA) Mode 2: Clock/Calendar

#define	RTC_MODE0_CTRLA_MODE_COUNT32 (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos)

#define	RTC_MODE0_CTRLA_MODE_COUNT16 (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos)

#define	RTC_MODE0_CTRLA_MODE_CLOCK (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos)

#define	RTC_MODE0_CTRLA_MATCHCLR_Pos 7
	(RTC_MODE0_CTRLA) Clear on Match

#define	RTC_MODE0_CTRLA_MATCHCLR (_U_(0x1) << RTC_MODE0_CTRLA_MATCHCLR_Pos)

#define	RTC_MODE0_CTRLA_PRESCALER_Pos 8
	(RTC_MODE0_CTRLA) Prescaler

#define	RTC_MODE0_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define	RTC_MODE0_CTRLA_PRESCALER(value) (RTC_MODE0_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE0_CTRLA_PRESCALER_Pos))

#define	RTC_MODE0_CTRLA_PRESCALER_OFF_Val _U_(0x0)
	(RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1

#define	RTC_MODE0_CTRLA_PRESCALER_DIV1_Val _U_(0x1)
	(RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1

#define	RTC_MODE0_CTRLA_PRESCALER_DIV2_Val _U_(0x2)
	(RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2

#define	RTC_MODE0_CTRLA_PRESCALER_DIV4_Val _U_(0x3)
	(RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4

#define	RTC_MODE0_CTRLA_PRESCALER_DIV8_Val _U_(0x4)
	(RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8

#define	RTC_MODE0_CTRLA_PRESCALER_DIV16_Val _U_(0x5)
	(RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16

#define	RTC_MODE0_CTRLA_PRESCALER_DIV32_Val _U_(0x6)
	(RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32

#define	RTC_MODE0_CTRLA_PRESCALER_DIV64_Val _U_(0x7)
	(RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64

#define	RTC_MODE0_CTRLA_PRESCALER_DIV128_Val _U_(0x8)
	(RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128

#define	RTC_MODE0_CTRLA_PRESCALER_DIV256_Val _U_(0x9)
	(RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256

#define	RTC_MODE0_CTRLA_PRESCALER_DIV512_Val _U_(0xA)
	(RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512

#define	RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)
	(RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024

#define	RTC_MODE0_CTRLA_PRESCALER_OFF (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define	RTC_MODE0_CTRLA_PRESCALER_DIV1 (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define	RTC_MODE0_CTRLA_PRESCALER_DIV2 (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define	RTC_MODE0_CTRLA_PRESCALER_DIV4 (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define	RTC_MODE0_CTRLA_PRESCALER_DIV8 (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define	RTC_MODE0_CTRLA_PRESCALER_DIV16 (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define	RTC_MODE0_CTRLA_PRESCALER_DIV32 (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define	RTC_MODE0_CTRLA_PRESCALER_DIV64 (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define	RTC_MODE0_CTRLA_PRESCALER_DIV128 (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define	RTC_MODE0_CTRLA_PRESCALER_DIV256 (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define	RTC_MODE0_CTRLA_PRESCALER_DIV512 (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define	RTC_MODE0_CTRLA_PRESCALER_DIV1024 (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)

#define	RTC_MODE0_CTRLA_BKTRST_Pos 13
	(RTC_MODE0_CTRLA) BKUP Registers Reset On Tamper Enable

#define	RTC_MODE0_CTRLA_BKTRST (_U_(0x1) << RTC_MODE0_CTRLA_BKTRST_Pos)

#define	RTC_MODE0_CTRLA_GPTRST_Pos 14
	(RTC_MODE0_CTRLA) GP Registers Reset On Tamper Enable

#define	RTC_MODE0_CTRLA_GPTRST (_U_(0x1) << RTC_MODE0_CTRLA_GPTRST_Pos)

#define	RTC_MODE0_CTRLA_COUNTSYNC_Pos 15
	(RTC_MODE0_CTRLA) Count Read Synchronization Enable

#define	RTC_MODE0_CTRLA_COUNTSYNC (_U_(0x1) << RTC_MODE0_CTRLA_COUNTSYNC_Pos)

#define	RTC_MODE0_CTRLA_MASK _U_(0xEF8F)
	(RTC_MODE0_CTRLA) MASK Register

#define	RTC_MODE1_CTRLA_OFFSET 0x00
	(RTC_MODE1_CTRLA offset) MODE1 Control A

#define	RTC_MODE1_CTRLA_RESETVALUE _U_(0x0000)
	(RTC_MODE1_CTRLA reset_value) MODE1 Control A

#define	RTC_MODE1_CTRLA_SWRST_Pos 0
	(RTC_MODE1_CTRLA) Software Reset

#define	RTC_MODE1_CTRLA_SWRST (_U_(0x1) << RTC_MODE1_CTRLA_SWRST_Pos)

#define	RTC_MODE1_CTRLA_ENABLE_Pos 1
	(RTC_MODE1_CTRLA) Enable

#define	RTC_MODE1_CTRLA_ENABLE (_U_(0x1) << RTC_MODE1_CTRLA_ENABLE_Pos)

#define	RTC_MODE1_CTRLA_MODE_Pos 2
	(RTC_MODE1_CTRLA) Operating Mode

#define	RTC_MODE1_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE1_CTRLA_MODE_Pos)

#define	RTC_MODE1_CTRLA_MODE(value) (RTC_MODE1_CTRLA_MODE_Msk & ((value) << RTC_MODE1_CTRLA_MODE_Pos))

#define	RTC_MODE1_CTRLA_MODE_COUNT32_Val _U_(0x0)
	(RTC_MODE1_CTRLA) Mode 0: 32-bit Counter

#define	RTC_MODE1_CTRLA_MODE_COUNT16_Val _U_(0x1)
	(RTC_MODE1_CTRLA) Mode 1: 16-bit Counter

#define	RTC_MODE1_CTRLA_MODE_CLOCK_Val _U_(0x2)
	(RTC_MODE1_CTRLA) Mode 2: Clock/Calendar

#define	RTC_MODE1_CTRLA_MODE_COUNT32 (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos)

#define	RTC_MODE1_CTRLA_MODE_COUNT16 (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos)

#define	RTC_MODE1_CTRLA_MODE_CLOCK (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos)

#define	RTC_MODE1_CTRLA_PRESCALER_Pos 8
	(RTC_MODE1_CTRLA) Prescaler

#define	RTC_MODE1_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define	RTC_MODE1_CTRLA_PRESCALER(value) (RTC_MODE1_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE1_CTRLA_PRESCALER_Pos))

#define	RTC_MODE1_CTRLA_PRESCALER_OFF_Val _U_(0x0)
	(RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1

#define	RTC_MODE1_CTRLA_PRESCALER_DIV1_Val _U_(0x1)
	(RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1

#define	RTC_MODE1_CTRLA_PRESCALER_DIV2_Val _U_(0x2)
	(RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2

#define	RTC_MODE1_CTRLA_PRESCALER_DIV4_Val _U_(0x3)
	(RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4

#define	RTC_MODE1_CTRLA_PRESCALER_DIV8_Val _U_(0x4)
	(RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8

#define	RTC_MODE1_CTRLA_PRESCALER_DIV16_Val _U_(0x5)
	(RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16

#define	RTC_MODE1_CTRLA_PRESCALER_DIV32_Val _U_(0x6)
	(RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32

#define	RTC_MODE1_CTRLA_PRESCALER_DIV64_Val _U_(0x7)
	(RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64

#define	RTC_MODE1_CTRLA_PRESCALER_DIV128_Val _U_(0x8)
	(RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128

#define	RTC_MODE1_CTRLA_PRESCALER_DIV256_Val _U_(0x9)
	(RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256

#define	RTC_MODE1_CTRLA_PRESCALER_DIV512_Val _U_(0xA)
	(RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512

#define	RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)
	(RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024

#define	RTC_MODE1_CTRLA_PRESCALER_OFF (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define	RTC_MODE1_CTRLA_PRESCALER_DIV1 (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define	RTC_MODE1_CTRLA_PRESCALER_DIV2 (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define	RTC_MODE1_CTRLA_PRESCALER_DIV4 (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define	RTC_MODE1_CTRLA_PRESCALER_DIV8 (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define	RTC_MODE1_CTRLA_PRESCALER_DIV16 (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define	RTC_MODE1_CTRLA_PRESCALER_DIV32 (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define	RTC_MODE1_CTRLA_PRESCALER_DIV64 (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define	RTC_MODE1_CTRLA_PRESCALER_DIV128 (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define	RTC_MODE1_CTRLA_PRESCALER_DIV256 (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define	RTC_MODE1_CTRLA_PRESCALER_DIV512 (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define	RTC_MODE1_CTRLA_PRESCALER_DIV1024 (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)

#define	RTC_MODE1_CTRLA_BKTRST_Pos 13
	(RTC_MODE1_CTRLA) BKUP Registers Reset On Tamper Enable

#define	RTC_MODE1_CTRLA_BKTRST (_U_(0x1) << RTC_MODE1_CTRLA_BKTRST_Pos)

#define	RTC_MODE1_CTRLA_GPTRST_Pos 14
	(RTC_MODE1_CTRLA) GP Registers Reset On Tamper Enable

#define	RTC_MODE1_CTRLA_GPTRST (_U_(0x1) << RTC_MODE1_CTRLA_GPTRST_Pos)

#define	RTC_MODE1_CTRLA_COUNTSYNC_Pos 15
	(RTC_MODE1_CTRLA) Count Read Synchronization Enable

#define	RTC_MODE1_CTRLA_COUNTSYNC (_U_(0x1) << RTC_MODE1_CTRLA_COUNTSYNC_Pos)

#define	RTC_MODE1_CTRLA_MASK _U_(0xEF0F)
	(RTC_MODE1_CTRLA) MASK Register

#define	RTC_MODE2_CTRLA_OFFSET 0x00
	(RTC_MODE2_CTRLA offset) MODE2 Control A

#define	RTC_MODE2_CTRLA_RESETVALUE _U_(0x0000)
	(RTC_MODE2_CTRLA reset_value) MODE2 Control A

#define	RTC_MODE2_CTRLA_SWRST_Pos 0
	(RTC_MODE2_CTRLA) Software Reset

#define	RTC_MODE2_CTRLA_SWRST (_U_(0x1) << RTC_MODE2_CTRLA_SWRST_Pos)

#define	RTC_MODE2_CTRLA_ENABLE_Pos 1
	(RTC_MODE2_CTRLA) Enable

#define	RTC_MODE2_CTRLA_ENABLE (_U_(0x1) << RTC_MODE2_CTRLA_ENABLE_Pos)

#define	RTC_MODE2_CTRLA_MODE_Pos 2
	(RTC_MODE2_CTRLA) Operating Mode

#define	RTC_MODE2_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE2_CTRLA_MODE_Pos)

#define	RTC_MODE2_CTRLA_MODE(value) (RTC_MODE2_CTRLA_MODE_Msk & ((value) << RTC_MODE2_CTRLA_MODE_Pos))

#define	RTC_MODE2_CTRLA_MODE_COUNT32_Val _U_(0x0)
	(RTC_MODE2_CTRLA) Mode 0: 32-bit Counter

#define	RTC_MODE2_CTRLA_MODE_COUNT16_Val _U_(0x1)
	(RTC_MODE2_CTRLA) Mode 1: 16-bit Counter

#define	RTC_MODE2_CTRLA_MODE_CLOCK_Val _U_(0x2)
	(RTC_MODE2_CTRLA) Mode 2: Clock/Calendar

#define	RTC_MODE2_CTRLA_MODE_COUNT32 (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos)

#define	RTC_MODE2_CTRLA_MODE_COUNT16 (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos)

#define	RTC_MODE2_CTRLA_MODE_CLOCK (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos)

#define	RTC_MODE2_CTRLA_CLKREP_Pos 6
	(RTC_MODE2_CTRLA) Clock Representation

#define	RTC_MODE2_CTRLA_CLKREP (_U_(0x1) << RTC_MODE2_CTRLA_CLKREP_Pos)

#define	RTC_MODE2_CTRLA_MATCHCLR_Pos 7
	(RTC_MODE2_CTRLA) Clear on Match

#define	RTC_MODE2_CTRLA_MATCHCLR (_U_(0x1) << RTC_MODE2_CTRLA_MATCHCLR_Pos)

#define	RTC_MODE2_CTRLA_PRESCALER_Pos 8
	(RTC_MODE2_CTRLA) Prescaler

#define	RTC_MODE2_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define	RTC_MODE2_CTRLA_PRESCALER(value) (RTC_MODE2_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE2_CTRLA_PRESCALER_Pos))

#define	RTC_MODE2_CTRLA_PRESCALER_OFF_Val _U_(0x0)
	(RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1

#define	RTC_MODE2_CTRLA_PRESCALER_DIV1_Val _U_(0x1)
	(RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1

#define	RTC_MODE2_CTRLA_PRESCALER_DIV2_Val _U_(0x2)
	(RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2

#define	RTC_MODE2_CTRLA_PRESCALER_DIV4_Val _U_(0x3)
	(RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4

#define	RTC_MODE2_CTRLA_PRESCALER_DIV8_Val _U_(0x4)
	(RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8

#define	RTC_MODE2_CTRLA_PRESCALER_DIV16_Val _U_(0x5)
	(RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16

#define	RTC_MODE2_CTRLA_PRESCALER_DIV32_Val _U_(0x6)
	(RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32

#define	RTC_MODE2_CTRLA_PRESCALER_DIV64_Val _U_(0x7)
	(RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64

#define	RTC_MODE2_CTRLA_PRESCALER_DIV128_Val _U_(0x8)
	(RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128

#define	RTC_MODE2_CTRLA_PRESCALER_DIV256_Val _U_(0x9)
	(RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256

#define	RTC_MODE2_CTRLA_PRESCALER_DIV512_Val _U_(0xA)
	(RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512

#define	RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)
	(RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024

#define	RTC_MODE2_CTRLA_PRESCALER_OFF (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define	RTC_MODE2_CTRLA_PRESCALER_DIV1 (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define	RTC_MODE2_CTRLA_PRESCALER_DIV2 (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define	RTC_MODE2_CTRLA_PRESCALER_DIV4 (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define	RTC_MODE2_CTRLA_PRESCALER_DIV8 (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define	RTC_MODE2_CTRLA_PRESCALER_DIV16 (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define	RTC_MODE2_CTRLA_PRESCALER_DIV32 (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define	RTC_MODE2_CTRLA_PRESCALER_DIV64 (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define	RTC_MODE2_CTRLA_PRESCALER_DIV128 (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define	RTC_MODE2_CTRLA_PRESCALER_DIV256 (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define	RTC_MODE2_CTRLA_PRESCALER_DIV512 (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define	RTC_MODE2_CTRLA_PRESCALER_DIV1024 (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)

#define	RTC_MODE2_CTRLA_BKTRST_Pos 13
	(RTC_MODE2_CTRLA) BKUP Registers Reset On Tamper Enable

#define	RTC_MODE2_CTRLA_BKTRST (_U_(0x1) << RTC_MODE2_CTRLA_BKTRST_Pos)

#define	RTC_MODE2_CTRLA_GPTRST_Pos 14
	(RTC_MODE2_CTRLA) GP Registers Reset On Tamper Enable

#define	RTC_MODE2_CTRLA_GPTRST (_U_(0x1) << RTC_MODE2_CTRLA_GPTRST_Pos)

#define	RTC_MODE2_CTRLA_CLOCKSYNC_Pos 15
	(RTC_MODE2_CTRLA) Clock Read Synchronization Enable

#define	RTC_MODE2_CTRLA_CLOCKSYNC (_U_(0x1) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos)

#define	RTC_MODE2_CTRLA_MASK _U_(0xEFCF)
	(RTC_MODE2_CTRLA) MASK Register

#define	RTC_MODE0_CTRLB_OFFSET 0x02
	(RTC_MODE0_CTRLB offset) MODE0 Control B

#define	RTC_MODE0_CTRLB_RESETVALUE _U_(0x0000)
	(RTC_MODE0_CTRLB reset_value) MODE0 Control B

#define	RTC_MODE0_CTRLB_GP0EN_Pos 0
	(RTC_MODE0_CTRLB) General Purpose 0 Enable

#define	RTC_MODE0_CTRLB_GP0EN (_U_(0x1) << RTC_MODE0_CTRLB_GP0EN_Pos)

#define	RTC_MODE0_CTRLB_GP2EN_Pos 1
	(RTC_MODE0_CTRLB) General Purpose 2 Enable

#define	RTC_MODE0_CTRLB_GP2EN (_U_(0x1) << RTC_MODE0_CTRLB_GP2EN_Pos)

#define	RTC_MODE0_CTRLB_DEBMAJ_Pos 4
	(RTC_MODE0_CTRLB) Debouncer Majority Enable

#define	RTC_MODE0_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE0_CTRLB_DEBMAJ_Pos)

#define	RTC_MODE0_CTRLB_DEBASYNC_Pos 5
	(RTC_MODE0_CTRLB) Debouncer Asynchronous Enable

#define	RTC_MODE0_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE0_CTRLB_DEBASYNC_Pos)

#define	RTC_MODE0_CTRLB_RTCOUT_Pos 6
	(RTC_MODE0_CTRLB) RTC Output Enable

#define	RTC_MODE0_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE0_CTRLB_RTCOUT_Pos)

#define	RTC_MODE0_CTRLB_DMAEN_Pos 7
	(RTC_MODE0_CTRLB) DMA Enable

#define	RTC_MODE0_CTRLB_DMAEN (_U_(0x1) << RTC_MODE0_CTRLB_DMAEN_Pos)

#define	RTC_MODE0_CTRLB_DEBF_Pos 8
	(RTC_MODE0_CTRLB) Debounce Freqnuency

#define	RTC_MODE0_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE0_CTRLB_DEBF_Pos)

#define	RTC_MODE0_CTRLB_DEBF(value) (RTC_MODE0_CTRLB_DEBF_Msk & ((value) << RTC_MODE0_CTRLB_DEBF_Pos))

#define	RTC_MODE0_CTRLB_DEBF_DIV2_Val _U_(0x0)
	(RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/2

#define	RTC_MODE0_CTRLB_DEBF_DIV4_Val _U_(0x1)
	(RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/4

#define	RTC_MODE0_CTRLB_DEBF_DIV8_Val _U_(0x2)
	(RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/8

#define	RTC_MODE0_CTRLB_DEBF_DIV16_Val _U_(0x3)
	(RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/16

#define	RTC_MODE0_CTRLB_DEBF_DIV32_Val _U_(0x4)
	(RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/32

#define	RTC_MODE0_CTRLB_DEBF_DIV64_Val _U_(0x5)
	(RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/64

#define	RTC_MODE0_CTRLB_DEBF_DIV128_Val _U_(0x6)
	(RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/128

#define	RTC_MODE0_CTRLB_DEBF_DIV256_Val _U_(0x7)
	(RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/256

#define	RTC_MODE0_CTRLB_DEBF_DIV2 (RTC_MODE0_CTRLB_DEBF_DIV2_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define	RTC_MODE0_CTRLB_DEBF_DIV4 (RTC_MODE0_CTRLB_DEBF_DIV4_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define	RTC_MODE0_CTRLB_DEBF_DIV8 (RTC_MODE0_CTRLB_DEBF_DIV8_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define	RTC_MODE0_CTRLB_DEBF_DIV16 (RTC_MODE0_CTRLB_DEBF_DIV16_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define	RTC_MODE0_CTRLB_DEBF_DIV32 (RTC_MODE0_CTRLB_DEBF_DIV32_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define	RTC_MODE0_CTRLB_DEBF_DIV64 (RTC_MODE0_CTRLB_DEBF_DIV64_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define	RTC_MODE0_CTRLB_DEBF_DIV128 (RTC_MODE0_CTRLB_DEBF_DIV128_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define	RTC_MODE0_CTRLB_DEBF_DIV256 (RTC_MODE0_CTRLB_DEBF_DIV256_Val << RTC_MODE0_CTRLB_DEBF_Pos)

#define	RTC_MODE0_CTRLB_ACTF_Pos 12
	(RTC_MODE0_CTRLB) Active Layer Freqnuency

#define	RTC_MODE0_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE0_CTRLB_ACTF_Pos)

#define	RTC_MODE0_CTRLB_ACTF(value) (RTC_MODE0_CTRLB_ACTF_Msk & ((value) << RTC_MODE0_CTRLB_ACTF_Pos))

#define	RTC_MODE0_CTRLB_ACTF_DIV2_Val _U_(0x0)
	(RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/2

#define	RTC_MODE0_CTRLB_ACTF_DIV4_Val _U_(0x1)
	(RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/4

#define	RTC_MODE0_CTRLB_ACTF_DIV8_Val _U_(0x2)
	(RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/8

#define	RTC_MODE0_CTRLB_ACTF_DIV16_Val _U_(0x3)
	(RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/16

#define	RTC_MODE0_CTRLB_ACTF_DIV32_Val _U_(0x4)
	(RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/32

#define	RTC_MODE0_CTRLB_ACTF_DIV64_Val _U_(0x5)
	(RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/64

#define	RTC_MODE0_CTRLB_ACTF_DIV128_Val _U_(0x6)
	(RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/128

#define	RTC_MODE0_CTRLB_ACTF_DIV256_Val _U_(0x7)
	(RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/256

#define	RTC_MODE0_CTRLB_ACTF_DIV2 (RTC_MODE0_CTRLB_ACTF_DIV2_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define	RTC_MODE0_CTRLB_ACTF_DIV4 (RTC_MODE0_CTRLB_ACTF_DIV4_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define	RTC_MODE0_CTRLB_ACTF_DIV8 (RTC_MODE0_CTRLB_ACTF_DIV8_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define	RTC_MODE0_CTRLB_ACTF_DIV16 (RTC_MODE0_CTRLB_ACTF_DIV16_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define	RTC_MODE0_CTRLB_ACTF_DIV32 (RTC_MODE0_CTRLB_ACTF_DIV32_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define	RTC_MODE0_CTRLB_ACTF_DIV64 (RTC_MODE0_CTRLB_ACTF_DIV64_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define	RTC_MODE0_CTRLB_ACTF_DIV128 (RTC_MODE0_CTRLB_ACTF_DIV128_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define	RTC_MODE0_CTRLB_ACTF_DIV256 (RTC_MODE0_CTRLB_ACTF_DIV256_Val << RTC_MODE0_CTRLB_ACTF_Pos)

#define	RTC_MODE0_CTRLB_MASK _U_(0x77F3)
	(RTC_MODE0_CTRLB) MASK Register

#define	RTC_MODE1_CTRLB_OFFSET 0x02
	(RTC_MODE1_CTRLB offset) MODE1 Control B

#define	RTC_MODE1_CTRLB_RESETVALUE _U_(0x0000)
	(RTC_MODE1_CTRLB reset_value) MODE1 Control B

#define	RTC_MODE1_CTRLB_GP0EN_Pos 0
	(RTC_MODE1_CTRLB) General Purpose 0 Enable

#define	RTC_MODE1_CTRLB_GP0EN (_U_(0x1) << RTC_MODE1_CTRLB_GP0EN_Pos)

#define	RTC_MODE1_CTRLB_GP2EN_Pos 1
	(RTC_MODE1_CTRLB) General Purpose 2 Enable

#define	RTC_MODE1_CTRLB_GP2EN (_U_(0x1) << RTC_MODE1_CTRLB_GP2EN_Pos)

#define	RTC_MODE1_CTRLB_DEBMAJ_Pos 4
	(RTC_MODE1_CTRLB) Debouncer Majority Enable

#define	RTC_MODE1_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE1_CTRLB_DEBMAJ_Pos)

#define	RTC_MODE1_CTRLB_DEBASYNC_Pos 5
	(RTC_MODE1_CTRLB) Debouncer Asynchronous Enable

#define	RTC_MODE1_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE1_CTRLB_DEBASYNC_Pos)

#define	RTC_MODE1_CTRLB_RTCOUT_Pos 6
	(RTC_MODE1_CTRLB) RTC Output Enable

#define	RTC_MODE1_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE1_CTRLB_RTCOUT_Pos)

#define	RTC_MODE1_CTRLB_DMAEN_Pos 7
	(RTC_MODE1_CTRLB) DMA Enable

#define	RTC_MODE1_CTRLB_DMAEN (_U_(0x1) << RTC_MODE1_CTRLB_DMAEN_Pos)

#define	RTC_MODE1_CTRLB_DEBF_Pos 8
	(RTC_MODE1_CTRLB) Debounce Freqnuency

#define	RTC_MODE1_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE1_CTRLB_DEBF_Pos)

#define	RTC_MODE1_CTRLB_DEBF(value) (RTC_MODE1_CTRLB_DEBF_Msk & ((value) << RTC_MODE1_CTRLB_DEBF_Pos))

#define	RTC_MODE1_CTRLB_DEBF_DIV2_Val _U_(0x0)
	(RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/2

#define	RTC_MODE1_CTRLB_DEBF_DIV4_Val _U_(0x1)
	(RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/4

#define	RTC_MODE1_CTRLB_DEBF_DIV8_Val _U_(0x2)
	(RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/8

#define	RTC_MODE1_CTRLB_DEBF_DIV16_Val _U_(0x3)
	(RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/16

#define	RTC_MODE1_CTRLB_DEBF_DIV32_Val _U_(0x4)
	(RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/32

#define	RTC_MODE1_CTRLB_DEBF_DIV64_Val _U_(0x5)
	(RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/64

#define	RTC_MODE1_CTRLB_DEBF_DIV128_Val _U_(0x6)
	(RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/128

#define	RTC_MODE1_CTRLB_DEBF_DIV256_Val _U_(0x7)
	(RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/256

#define	RTC_MODE1_CTRLB_DEBF_DIV2 (RTC_MODE1_CTRLB_DEBF_DIV2_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define	RTC_MODE1_CTRLB_DEBF_DIV4 (RTC_MODE1_CTRLB_DEBF_DIV4_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define	RTC_MODE1_CTRLB_DEBF_DIV8 (RTC_MODE1_CTRLB_DEBF_DIV8_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define	RTC_MODE1_CTRLB_DEBF_DIV16 (RTC_MODE1_CTRLB_DEBF_DIV16_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define	RTC_MODE1_CTRLB_DEBF_DIV32 (RTC_MODE1_CTRLB_DEBF_DIV32_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define	RTC_MODE1_CTRLB_DEBF_DIV64 (RTC_MODE1_CTRLB_DEBF_DIV64_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define	RTC_MODE1_CTRLB_DEBF_DIV128 (RTC_MODE1_CTRLB_DEBF_DIV128_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define	RTC_MODE1_CTRLB_DEBF_DIV256 (RTC_MODE1_CTRLB_DEBF_DIV256_Val << RTC_MODE1_CTRLB_DEBF_Pos)

#define	RTC_MODE1_CTRLB_ACTF_Pos 12
	(RTC_MODE1_CTRLB) Active Layer Freqnuency

#define	RTC_MODE1_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE1_CTRLB_ACTF_Pos)

#define	RTC_MODE1_CTRLB_ACTF(value) (RTC_MODE1_CTRLB_ACTF_Msk & ((value) << RTC_MODE1_CTRLB_ACTF_Pos))

#define	RTC_MODE1_CTRLB_ACTF_DIV2_Val _U_(0x0)
	(RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/2

#define	RTC_MODE1_CTRLB_ACTF_DIV4_Val _U_(0x1)
	(RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/4

#define	RTC_MODE1_CTRLB_ACTF_DIV8_Val _U_(0x2)
	(RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/8

#define	RTC_MODE1_CTRLB_ACTF_DIV16_Val _U_(0x3)
	(RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/16

#define	RTC_MODE1_CTRLB_ACTF_DIV32_Val _U_(0x4)
	(RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/32

#define	RTC_MODE1_CTRLB_ACTF_DIV64_Val _U_(0x5)
	(RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/64

#define	RTC_MODE1_CTRLB_ACTF_DIV128_Val _U_(0x6)
	(RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/128

#define	RTC_MODE1_CTRLB_ACTF_DIV256_Val _U_(0x7)
	(RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/256

#define	RTC_MODE1_CTRLB_ACTF_DIV2 (RTC_MODE1_CTRLB_ACTF_DIV2_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define	RTC_MODE1_CTRLB_ACTF_DIV4 (RTC_MODE1_CTRLB_ACTF_DIV4_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define	RTC_MODE1_CTRLB_ACTF_DIV8 (RTC_MODE1_CTRLB_ACTF_DIV8_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define	RTC_MODE1_CTRLB_ACTF_DIV16 (RTC_MODE1_CTRLB_ACTF_DIV16_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define	RTC_MODE1_CTRLB_ACTF_DIV32 (RTC_MODE1_CTRLB_ACTF_DIV32_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define	RTC_MODE1_CTRLB_ACTF_DIV64 (RTC_MODE1_CTRLB_ACTF_DIV64_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define	RTC_MODE1_CTRLB_ACTF_DIV128 (RTC_MODE1_CTRLB_ACTF_DIV128_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define	RTC_MODE1_CTRLB_ACTF_DIV256 (RTC_MODE1_CTRLB_ACTF_DIV256_Val << RTC_MODE1_CTRLB_ACTF_Pos)

#define	RTC_MODE1_CTRLB_MASK _U_(0x77F3)
	(RTC_MODE1_CTRLB) MASK Register

#define	RTC_MODE2_CTRLB_OFFSET 0x02
	(RTC_MODE2_CTRLB offset) MODE2 Control B

#define	RTC_MODE2_CTRLB_RESETVALUE _U_(0x0000)
	(RTC_MODE2_CTRLB reset_value) MODE2 Control B

#define	RTC_MODE2_CTRLB_GP0EN_Pos 0
	(RTC_MODE2_CTRLB) General Purpose 0 Enable

#define	RTC_MODE2_CTRLB_GP0EN (_U_(0x1) << RTC_MODE2_CTRLB_GP0EN_Pos)

#define	RTC_MODE2_CTRLB_GP2EN_Pos 1
	(RTC_MODE2_CTRLB) General Purpose 2 Enable

#define	RTC_MODE2_CTRLB_GP2EN (_U_(0x1) << RTC_MODE2_CTRLB_GP2EN_Pos)

#define	RTC_MODE2_CTRLB_DEBMAJ_Pos 4
	(RTC_MODE2_CTRLB) Debouncer Majority Enable

#define	RTC_MODE2_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE2_CTRLB_DEBMAJ_Pos)

#define	RTC_MODE2_CTRLB_DEBASYNC_Pos 5
	(RTC_MODE2_CTRLB) Debouncer Asynchronous Enable

#define	RTC_MODE2_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE2_CTRLB_DEBASYNC_Pos)

#define	RTC_MODE2_CTRLB_RTCOUT_Pos 6
	(RTC_MODE2_CTRLB) RTC Output Enable

#define	RTC_MODE2_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE2_CTRLB_RTCOUT_Pos)

#define	RTC_MODE2_CTRLB_DMAEN_Pos 7
	(RTC_MODE2_CTRLB) DMA Enable

#define	RTC_MODE2_CTRLB_DMAEN (_U_(0x1) << RTC_MODE2_CTRLB_DMAEN_Pos)

#define	RTC_MODE2_CTRLB_DEBF_Pos 8
	(RTC_MODE2_CTRLB) Debounce Freqnuency

#define	RTC_MODE2_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE2_CTRLB_DEBF_Pos)

#define	RTC_MODE2_CTRLB_DEBF(value) (RTC_MODE2_CTRLB_DEBF_Msk & ((value) << RTC_MODE2_CTRLB_DEBF_Pos))

#define	RTC_MODE2_CTRLB_DEBF_DIV2_Val _U_(0x0)
	(RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/2

#define	RTC_MODE2_CTRLB_DEBF_DIV4_Val _U_(0x1)
	(RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/4

#define	RTC_MODE2_CTRLB_DEBF_DIV8_Val _U_(0x2)
	(RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/8

#define	RTC_MODE2_CTRLB_DEBF_DIV16_Val _U_(0x3)
	(RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/16

#define	RTC_MODE2_CTRLB_DEBF_DIV32_Val _U_(0x4)
	(RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/32

#define	RTC_MODE2_CTRLB_DEBF_DIV64_Val _U_(0x5)
	(RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/64

#define	RTC_MODE2_CTRLB_DEBF_DIV128_Val _U_(0x6)
	(RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/128

#define	RTC_MODE2_CTRLB_DEBF_DIV256_Val _U_(0x7)
	(RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/256

#define	RTC_MODE2_CTRLB_DEBF_DIV2 (RTC_MODE2_CTRLB_DEBF_DIV2_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define	RTC_MODE2_CTRLB_DEBF_DIV4 (RTC_MODE2_CTRLB_DEBF_DIV4_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define	RTC_MODE2_CTRLB_DEBF_DIV8 (RTC_MODE2_CTRLB_DEBF_DIV8_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define	RTC_MODE2_CTRLB_DEBF_DIV16 (RTC_MODE2_CTRLB_DEBF_DIV16_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define	RTC_MODE2_CTRLB_DEBF_DIV32 (RTC_MODE2_CTRLB_DEBF_DIV32_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define	RTC_MODE2_CTRLB_DEBF_DIV64 (RTC_MODE2_CTRLB_DEBF_DIV64_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define	RTC_MODE2_CTRLB_DEBF_DIV128 (RTC_MODE2_CTRLB_DEBF_DIV128_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define	RTC_MODE2_CTRLB_DEBF_DIV256 (RTC_MODE2_CTRLB_DEBF_DIV256_Val << RTC_MODE2_CTRLB_DEBF_Pos)

#define	RTC_MODE2_CTRLB_ACTF_Pos 12
	(RTC_MODE2_CTRLB) Active Layer Freqnuency

#define	RTC_MODE2_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE2_CTRLB_ACTF_Pos)

#define	RTC_MODE2_CTRLB_ACTF(value) (RTC_MODE2_CTRLB_ACTF_Msk & ((value) << RTC_MODE2_CTRLB_ACTF_Pos))

#define	RTC_MODE2_CTRLB_ACTF_DIV2_Val _U_(0x0)
	(RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/2

#define	RTC_MODE2_CTRLB_ACTF_DIV4_Val _U_(0x1)
	(RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/4

#define	RTC_MODE2_CTRLB_ACTF_DIV8_Val _U_(0x2)
	(RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/8

#define	RTC_MODE2_CTRLB_ACTF_DIV16_Val _U_(0x3)
	(RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/16

#define	RTC_MODE2_CTRLB_ACTF_DIV32_Val _U_(0x4)
	(RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/32

#define	RTC_MODE2_CTRLB_ACTF_DIV64_Val _U_(0x5)
	(RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/64

#define	RTC_MODE2_CTRLB_ACTF_DIV128_Val _U_(0x6)
	(RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/128

#define	RTC_MODE2_CTRLB_ACTF_DIV256_Val _U_(0x7)
	(RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/256

#define	RTC_MODE2_CTRLB_ACTF_DIV2 (RTC_MODE2_CTRLB_ACTF_DIV2_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define	RTC_MODE2_CTRLB_ACTF_DIV4 (RTC_MODE2_CTRLB_ACTF_DIV4_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define	RTC_MODE2_CTRLB_ACTF_DIV8 (RTC_MODE2_CTRLB_ACTF_DIV8_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define	RTC_MODE2_CTRLB_ACTF_DIV16 (RTC_MODE2_CTRLB_ACTF_DIV16_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define	RTC_MODE2_CTRLB_ACTF_DIV32 (RTC_MODE2_CTRLB_ACTF_DIV32_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define	RTC_MODE2_CTRLB_ACTF_DIV64 (RTC_MODE2_CTRLB_ACTF_DIV64_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define	RTC_MODE2_CTRLB_ACTF_DIV128 (RTC_MODE2_CTRLB_ACTF_DIV128_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define	RTC_MODE2_CTRLB_ACTF_DIV256 (RTC_MODE2_CTRLB_ACTF_DIV256_Val << RTC_MODE2_CTRLB_ACTF_Pos)

#define	RTC_MODE2_CTRLB_MASK _U_(0x77F3)
	(RTC_MODE2_CTRLB) MASK Register

#define	RTC_MODE0_EVCTRL_OFFSET 0x04
	(RTC_MODE0_EVCTRL offset) MODE0 Event Control

#define	RTC_MODE0_EVCTRL_RESETVALUE _U_(0x00000000)
	(RTC_MODE0_EVCTRL reset_value) MODE0 Event Control

#define	RTC_MODE0_EVCTRL_PEREO0_Pos 0
	(RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable

#define	RTC_MODE0_EVCTRL_PEREO0 (_U_(1) << RTC_MODE0_EVCTRL_PEREO0_Pos)

#define	RTC_MODE0_EVCTRL_PEREO1_Pos 1
	(RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable

#define	RTC_MODE0_EVCTRL_PEREO1 (_U_(1) << RTC_MODE0_EVCTRL_PEREO1_Pos)

#define	RTC_MODE0_EVCTRL_PEREO2_Pos 2
	(RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable

#define	RTC_MODE0_EVCTRL_PEREO2 (_U_(1) << RTC_MODE0_EVCTRL_PEREO2_Pos)

#define	RTC_MODE0_EVCTRL_PEREO3_Pos 3
	(RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable

#define	RTC_MODE0_EVCTRL_PEREO3 (_U_(1) << RTC_MODE0_EVCTRL_PEREO3_Pos)

#define	RTC_MODE0_EVCTRL_PEREO4_Pos 4
	(RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable

#define	RTC_MODE0_EVCTRL_PEREO4 (_U_(1) << RTC_MODE0_EVCTRL_PEREO4_Pos)

#define	RTC_MODE0_EVCTRL_PEREO5_Pos 5
	(RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable

#define	RTC_MODE0_EVCTRL_PEREO5 (_U_(1) << RTC_MODE0_EVCTRL_PEREO5_Pos)

#define	RTC_MODE0_EVCTRL_PEREO6_Pos 6
	(RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable

#define	RTC_MODE0_EVCTRL_PEREO6 (_U_(1) << RTC_MODE0_EVCTRL_PEREO6_Pos)

#define	RTC_MODE0_EVCTRL_PEREO7_Pos 7
	(RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable

#define	RTC_MODE0_EVCTRL_PEREO7 (_U_(1) << RTC_MODE0_EVCTRL_PEREO7_Pos)

#define	RTC_MODE0_EVCTRL_PEREO_Pos 0
	(RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable

#define	RTC_MODE0_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos)

#define	RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))

#define	RTC_MODE0_EVCTRL_CMPEO0_Pos 8
	(RTC_MODE0_EVCTRL) Compare 0 Event Output Enable

#define	RTC_MODE0_EVCTRL_CMPEO0 (_U_(1) << RTC_MODE0_EVCTRL_CMPEO0_Pos)

#define	RTC_MODE0_EVCTRL_CMPEO1_Pos 9
	(RTC_MODE0_EVCTRL) Compare 1 Event Output Enable

#define	RTC_MODE0_EVCTRL_CMPEO1 (_U_(1) << RTC_MODE0_EVCTRL_CMPEO1_Pos)

#define	RTC_MODE0_EVCTRL_CMPEO_Pos 8
	(RTC_MODE0_EVCTRL) Compare x Event Output Enable

#define	RTC_MODE0_EVCTRL_CMPEO_Msk (_U_(0x3) << RTC_MODE0_EVCTRL_CMPEO_Pos)

#define	RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))

#define	RTC_MODE0_EVCTRL_TAMPEREO_Pos 14
	(RTC_MODE0_EVCTRL) Tamper Event Output Enable

#define	RTC_MODE0_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEREO_Pos)

#define	RTC_MODE0_EVCTRL_OVFEO_Pos 15
	(RTC_MODE0_EVCTRL) Overflow Event Output Enable

#define	RTC_MODE0_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos)

#define	RTC_MODE0_EVCTRL_TAMPEVEI_Pos 16
	(RTC_MODE0_EVCTRL) Tamper Event Input Enable

#define	RTC_MODE0_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEVEI_Pos)

#define	RTC_MODE0_EVCTRL_MASK _U_(0x0001C3FF)
	(RTC_MODE0_EVCTRL) MASK Register

#define	RTC_MODE1_EVCTRL_OFFSET 0x04
	(RTC_MODE1_EVCTRL offset) MODE1 Event Control

#define	RTC_MODE1_EVCTRL_RESETVALUE _U_(0x00000000)
	(RTC_MODE1_EVCTRL reset_value) MODE1 Event Control

#define	RTC_MODE1_EVCTRL_PEREO0_Pos 0
	(RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable

#define	RTC_MODE1_EVCTRL_PEREO0 (_U_(1) << RTC_MODE1_EVCTRL_PEREO0_Pos)

#define	RTC_MODE1_EVCTRL_PEREO1_Pos 1
	(RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable

#define	RTC_MODE1_EVCTRL_PEREO1 (_U_(1) << RTC_MODE1_EVCTRL_PEREO1_Pos)

#define	RTC_MODE1_EVCTRL_PEREO2_Pos 2
	(RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable

#define	RTC_MODE1_EVCTRL_PEREO2 (_U_(1) << RTC_MODE1_EVCTRL_PEREO2_Pos)

#define	RTC_MODE1_EVCTRL_PEREO3_Pos 3
	(RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable

#define	RTC_MODE1_EVCTRL_PEREO3 (_U_(1) << RTC_MODE1_EVCTRL_PEREO3_Pos)

#define	RTC_MODE1_EVCTRL_PEREO4_Pos 4
	(RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable

#define	RTC_MODE1_EVCTRL_PEREO4 (_U_(1) << RTC_MODE1_EVCTRL_PEREO4_Pos)

#define	RTC_MODE1_EVCTRL_PEREO5_Pos 5
	(RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable

#define	RTC_MODE1_EVCTRL_PEREO5 (_U_(1) << RTC_MODE1_EVCTRL_PEREO5_Pos)

#define	RTC_MODE1_EVCTRL_PEREO6_Pos 6
	(RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable

#define	RTC_MODE1_EVCTRL_PEREO6 (_U_(1) << RTC_MODE1_EVCTRL_PEREO6_Pos)

#define	RTC_MODE1_EVCTRL_PEREO7_Pos 7
	(RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable

#define	RTC_MODE1_EVCTRL_PEREO7 (_U_(1) << RTC_MODE1_EVCTRL_PEREO7_Pos)

#define	RTC_MODE1_EVCTRL_PEREO_Pos 0
	(RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable

#define	RTC_MODE1_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos)

#define	RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))

#define	RTC_MODE1_EVCTRL_CMPEO0_Pos 8
	(RTC_MODE1_EVCTRL) Compare 0 Event Output Enable

#define	RTC_MODE1_EVCTRL_CMPEO0 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO0_Pos)

#define	RTC_MODE1_EVCTRL_CMPEO1_Pos 9
	(RTC_MODE1_EVCTRL) Compare 1 Event Output Enable

#define	RTC_MODE1_EVCTRL_CMPEO1 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO1_Pos)

#define	RTC_MODE1_EVCTRL_CMPEO2_Pos 10
	(RTC_MODE1_EVCTRL) Compare 2 Event Output Enable

#define	RTC_MODE1_EVCTRL_CMPEO2 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO2_Pos)

#define	RTC_MODE1_EVCTRL_CMPEO3_Pos 11
	(RTC_MODE1_EVCTRL) Compare 3 Event Output Enable

#define	RTC_MODE1_EVCTRL_CMPEO3 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO3_Pos)

#define	RTC_MODE1_EVCTRL_CMPEO_Pos 8
	(RTC_MODE1_EVCTRL) Compare x Event Output Enable

#define	RTC_MODE1_EVCTRL_CMPEO_Msk (_U_(0xF) << RTC_MODE1_EVCTRL_CMPEO_Pos)

#define	RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))

#define	RTC_MODE1_EVCTRL_TAMPEREO_Pos 14
	(RTC_MODE1_EVCTRL) Tamper Event Output Enable

#define	RTC_MODE1_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEREO_Pos)

#define	RTC_MODE1_EVCTRL_OVFEO_Pos 15
	(RTC_MODE1_EVCTRL) Overflow Event Output Enable

#define	RTC_MODE1_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos)

#define	RTC_MODE1_EVCTRL_TAMPEVEI_Pos 16
	(RTC_MODE1_EVCTRL) Tamper Event Input Enable

#define	RTC_MODE1_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEVEI_Pos)

#define	RTC_MODE1_EVCTRL_MASK _U_(0x0001CFFF)
	(RTC_MODE1_EVCTRL) MASK Register

#define	RTC_MODE2_EVCTRL_OFFSET 0x04
	(RTC_MODE2_EVCTRL offset) MODE2 Event Control

#define	RTC_MODE2_EVCTRL_RESETVALUE _U_(0x00000000)
	(RTC_MODE2_EVCTRL reset_value) MODE2 Event Control

#define	RTC_MODE2_EVCTRL_PEREO0_Pos 0
	(RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable

#define	RTC_MODE2_EVCTRL_PEREO0 (_U_(1) << RTC_MODE2_EVCTRL_PEREO0_Pos)

#define	RTC_MODE2_EVCTRL_PEREO1_Pos 1
	(RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable

#define	RTC_MODE2_EVCTRL_PEREO1 (_U_(1) << RTC_MODE2_EVCTRL_PEREO1_Pos)

#define	RTC_MODE2_EVCTRL_PEREO2_Pos 2
	(RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable

#define	RTC_MODE2_EVCTRL_PEREO2 (_U_(1) << RTC_MODE2_EVCTRL_PEREO2_Pos)

#define	RTC_MODE2_EVCTRL_PEREO3_Pos 3
	(RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable

#define	RTC_MODE2_EVCTRL_PEREO3 (_U_(1) << RTC_MODE2_EVCTRL_PEREO3_Pos)

#define	RTC_MODE2_EVCTRL_PEREO4_Pos 4
	(RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable

#define	RTC_MODE2_EVCTRL_PEREO4 (_U_(1) << RTC_MODE2_EVCTRL_PEREO4_Pos)

#define	RTC_MODE2_EVCTRL_PEREO5_Pos 5
	(RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable

#define	RTC_MODE2_EVCTRL_PEREO5 (_U_(1) << RTC_MODE2_EVCTRL_PEREO5_Pos)

#define	RTC_MODE2_EVCTRL_PEREO6_Pos 6
	(RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable

#define	RTC_MODE2_EVCTRL_PEREO6 (_U_(1) << RTC_MODE2_EVCTRL_PEREO6_Pos)

#define	RTC_MODE2_EVCTRL_PEREO7_Pos 7
	(RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable

#define	RTC_MODE2_EVCTRL_PEREO7 (_U_(1) << RTC_MODE2_EVCTRL_PEREO7_Pos)

#define	RTC_MODE2_EVCTRL_PEREO_Pos 0
	(RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable

#define	RTC_MODE2_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos)

#define	RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))

#define	RTC_MODE2_EVCTRL_ALARMEO0_Pos 8
	(RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable

#define	RTC_MODE2_EVCTRL_ALARMEO0 (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO0_Pos)

#define	RTC_MODE2_EVCTRL_ALARMEO1_Pos 9
	(RTC_MODE2_EVCTRL) Alarm 1 Event Output Enable

#define	RTC_MODE2_EVCTRL_ALARMEO1 (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO1_Pos)

#define	RTC_MODE2_EVCTRL_ALARMEO_Pos 8
	(RTC_MODE2_EVCTRL) Alarm x Event Output Enable

#define	RTC_MODE2_EVCTRL_ALARMEO_Msk (_U_(0x3) << RTC_MODE2_EVCTRL_ALARMEO_Pos)

#define	RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))

#define	RTC_MODE2_EVCTRL_TAMPEREO_Pos 14
	(RTC_MODE2_EVCTRL) Tamper Event Output Enable

#define	RTC_MODE2_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEREO_Pos)

#define	RTC_MODE2_EVCTRL_OVFEO_Pos 15
	(RTC_MODE2_EVCTRL) Overflow Event Output Enable

#define	RTC_MODE2_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos)

#define	RTC_MODE2_EVCTRL_TAMPEVEI_Pos 16
	(RTC_MODE2_EVCTRL) Tamper Event Input Enable

#define	RTC_MODE2_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEVEI_Pos)

#define	RTC_MODE2_EVCTRL_MASK _U_(0x0001C3FF)
	(RTC_MODE2_EVCTRL) MASK Register

#define	RTC_MODE0_INTENCLR_OFFSET 0x08
	(RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear

#define	RTC_MODE0_INTENCLR_RESETVALUE _U_(0x0000)
	(RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear

#define	RTC_MODE0_INTENCLR_PER0_Pos 0
	(RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable

#define	RTC_MODE0_INTENCLR_PER0 (_U_(1) << RTC_MODE0_INTENCLR_PER0_Pos)

#define	RTC_MODE0_INTENCLR_PER1_Pos 1
	(RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable

#define	RTC_MODE0_INTENCLR_PER1 (_U_(1) << RTC_MODE0_INTENCLR_PER1_Pos)

#define	RTC_MODE0_INTENCLR_PER2_Pos 2
	(RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable

#define	RTC_MODE0_INTENCLR_PER2 (_U_(1) << RTC_MODE0_INTENCLR_PER2_Pos)

#define	RTC_MODE0_INTENCLR_PER3_Pos 3
	(RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable

#define	RTC_MODE0_INTENCLR_PER3 (_U_(1) << RTC_MODE0_INTENCLR_PER3_Pos)

#define	RTC_MODE0_INTENCLR_PER4_Pos 4
	(RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable

#define	RTC_MODE0_INTENCLR_PER4 (_U_(1) << RTC_MODE0_INTENCLR_PER4_Pos)

#define	RTC_MODE0_INTENCLR_PER5_Pos 5
	(RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable

#define	RTC_MODE0_INTENCLR_PER5 (_U_(1) << RTC_MODE0_INTENCLR_PER5_Pos)

#define	RTC_MODE0_INTENCLR_PER6_Pos 6
	(RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable

#define	RTC_MODE0_INTENCLR_PER6 (_U_(1) << RTC_MODE0_INTENCLR_PER6_Pos)

#define	RTC_MODE0_INTENCLR_PER7_Pos 7
	(RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable

#define	RTC_MODE0_INTENCLR_PER7 (_U_(1) << RTC_MODE0_INTENCLR_PER7_Pos)

#define	RTC_MODE0_INTENCLR_PER_Pos 0
	(RTC_MODE0_INTENCLR) Periodic Interval x Interrupt Enable

#define	RTC_MODE0_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE0_INTENCLR_PER_Pos)

#define	RTC_MODE0_INTENCLR_PER(value) (RTC_MODE0_INTENCLR_PER_Msk & ((value) << RTC_MODE0_INTENCLR_PER_Pos))

#define	RTC_MODE0_INTENCLR_CMP0_Pos 8
	(RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable

#define	RTC_MODE0_INTENCLR_CMP0 (_U_(1) << RTC_MODE0_INTENCLR_CMP0_Pos)

#define	RTC_MODE0_INTENCLR_CMP1_Pos 9
	(RTC_MODE0_INTENCLR) Compare 1 Interrupt Enable

#define	RTC_MODE0_INTENCLR_CMP1 (_U_(1) << RTC_MODE0_INTENCLR_CMP1_Pos)

#define	RTC_MODE0_INTENCLR_CMP_Pos 8
	(RTC_MODE0_INTENCLR) Compare x Interrupt Enable

#define	RTC_MODE0_INTENCLR_CMP_Msk (_U_(0x3) << RTC_MODE0_INTENCLR_CMP_Pos)

#define	RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))

#define	RTC_MODE0_INTENCLR_TAMPER_Pos 14
	(RTC_MODE0_INTENCLR) Tamper Enable

#define	RTC_MODE0_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE0_INTENCLR_TAMPER_Pos)

#define	RTC_MODE0_INTENCLR_OVF_Pos 15
	(RTC_MODE0_INTENCLR) Overflow Interrupt Enable

#define	RTC_MODE0_INTENCLR_OVF (_U_(0x1) << RTC_MODE0_INTENCLR_OVF_Pos)

#define	RTC_MODE0_INTENCLR_MASK _U_(0xC3FF)
	(RTC_MODE0_INTENCLR) MASK Register

#define	RTC_MODE1_INTENCLR_OFFSET 0x08
	(RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear

#define	RTC_MODE1_INTENCLR_RESETVALUE _U_(0x0000)
	(RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear

#define	RTC_MODE1_INTENCLR_PER0_Pos 0
	(RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable

#define	RTC_MODE1_INTENCLR_PER0 (_U_(1) << RTC_MODE1_INTENCLR_PER0_Pos)

#define	RTC_MODE1_INTENCLR_PER1_Pos 1
	(RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable

#define	RTC_MODE1_INTENCLR_PER1 (_U_(1) << RTC_MODE1_INTENCLR_PER1_Pos)

#define	RTC_MODE1_INTENCLR_PER2_Pos 2
	(RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable

#define	RTC_MODE1_INTENCLR_PER2 (_U_(1) << RTC_MODE1_INTENCLR_PER2_Pos)

#define	RTC_MODE1_INTENCLR_PER3_Pos 3
	(RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable

#define	RTC_MODE1_INTENCLR_PER3 (_U_(1) << RTC_MODE1_INTENCLR_PER3_Pos)

#define	RTC_MODE1_INTENCLR_PER4_Pos 4
	(RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable

#define	RTC_MODE1_INTENCLR_PER4 (_U_(1) << RTC_MODE1_INTENCLR_PER4_Pos)

#define	RTC_MODE1_INTENCLR_PER5_Pos 5
	(RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable

#define	RTC_MODE1_INTENCLR_PER5 (_U_(1) << RTC_MODE1_INTENCLR_PER5_Pos)

#define	RTC_MODE1_INTENCLR_PER6_Pos 6
	(RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable

#define	RTC_MODE1_INTENCLR_PER6 (_U_(1) << RTC_MODE1_INTENCLR_PER6_Pos)

#define	RTC_MODE1_INTENCLR_PER7_Pos 7
	(RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable

#define	RTC_MODE1_INTENCLR_PER7 (_U_(1) << RTC_MODE1_INTENCLR_PER7_Pos)

#define	RTC_MODE1_INTENCLR_PER_Pos 0
	(RTC_MODE1_INTENCLR) Periodic Interval x Interrupt Enable

#define	RTC_MODE1_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE1_INTENCLR_PER_Pos)

#define	RTC_MODE1_INTENCLR_PER(value) (RTC_MODE1_INTENCLR_PER_Msk & ((value) << RTC_MODE1_INTENCLR_PER_Pos))

#define	RTC_MODE1_INTENCLR_CMP0_Pos 8
	(RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable

#define	RTC_MODE1_INTENCLR_CMP0 (_U_(1) << RTC_MODE1_INTENCLR_CMP0_Pos)

#define	RTC_MODE1_INTENCLR_CMP1_Pos 9
	(RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable

#define	RTC_MODE1_INTENCLR_CMP1 (_U_(1) << RTC_MODE1_INTENCLR_CMP1_Pos)

#define	RTC_MODE1_INTENCLR_CMP2_Pos 10
	(RTC_MODE1_INTENCLR) Compare 2 Interrupt Enable

#define	RTC_MODE1_INTENCLR_CMP2 (_U_(1) << RTC_MODE1_INTENCLR_CMP2_Pos)

#define	RTC_MODE1_INTENCLR_CMP3_Pos 11
	(RTC_MODE1_INTENCLR) Compare 3 Interrupt Enable

#define	RTC_MODE1_INTENCLR_CMP3 (_U_(1) << RTC_MODE1_INTENCLR_CMP3_Pos)

#define	RTC_MODE1_INTENCLR_CMP_Pos 8
	(RTC_MODE1_INTENCLR) Compare x Interrupt Enable

#define	RTC_MODE1_INTENCLR_CMP_Msk (_U_(0xF) << RTC_MODE1_INTENCLR_CMP_Pos)

#define	RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))

#define	RTC_MODE1_INTENCLR_TAMPER_Pos 14
	(RTC_MODE1_INTENCLR) Tamper Enable

#define	RTC_MODE1_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE1_INTENCLR_TAMPER_Pos)

#define	RTC_MODE1_INTENCLR_OVF_Pos 15
	(RTC_MODE1_INTENCLR) Overflow Interrupt Enable

#define	RTC_MODE1_INTENCLR_OVF (_U_(0x1) << RTC_MODE1_INTENCLR_OVF_Pos)

#define	RTC_MODE1_INTENCLR_MASK _U_(0xCFFF)
	(RTC_MODE1_INTENCLR) MASK Register

#define	RTC_MODE2_INTENCLR_OFFSET 0x08
	(RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear

#define	RTC_MODE2_INTENCLR_RESETVALUE _U_(0x0000)
	(RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear

#define	RTC_MODE2_INTENCLR_PER0_Pos 0
	(RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable

#define	RTC_MODE2_INTENCLR_PER0 (_U_(1) << RTC_MODE2_INTENCLR_PER0_Pos)

#define	RTC_MODE2_INTENCLR_PER1_Pos 1
	(RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable

#define	RTC_MODE2_INTENCLR_PER1 (_U_(1) << RTC_MODE2_INTENCLR_PER1_Pos)

#define	RTC_MODE2_INTENCLR_PER2_Pos 2
	(RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable

#define	RTC_MODE2_INTENCLR_PER2 (_U_(1) << RTC_MODE2_INTENCLR_PER2_Pos)

#define	RTC_MODE2_INTENCLR_PER3_Pos 3
	(RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable

#define	RTC_MODE2_INTENCLR_PER3 (_U_(1) << RTC_MODE2_INTENCLR_PER3_Pos)

#define	RTC_MODE2_INTENCLR_PER4_Pos 4
	(RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable

#define	RTC_MODE2_INTENCLR_PER4 (_U_(1) << RTC_MODE2_INTENCLR_PER4_Pos)

#define	RTC_MODE2_INTENCLR_PER5_Pos 5
	(RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable

#define	RTC_MODE2_INTENCLR_PER5 (_U_(1) << RTC_MODE2_INTENCLR_PER5_Pos)

#define	RTC_MODE2_INTENCLR_PER6_Pos 6
	(RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable

#define	RTC_MODE2_INTENCLR_PER6 (_U_(1) << RTC_MODE2_INTENCLR_PER6_Pos)

#define	RTC_MODE2_INTENCLR_PER7_Pos 7
	(RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable

#define	RTC_MODE2_INTENCLR_PER7 (_U_(1) << RTC_MODE2_INTENCLR_PER7_Pos)

#define	RTC_MODE2_INTENCLR_PER_Pos 0
	(RTC_MODE2_INTENCLR) Periodic Interval x Interrupt Enable

#define	RTC_MODE2_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE2_INTENCLR_PER_Pos)

#define	RTC_MODE2_INTENCLR_PER(value) (RTC_MODE2_INTENCLR_PER_Msk & ((value) << RTC_MODE2_INTENCLR_PER_Pos))

#define	RTC_MODE2_INTENCLR_ALARM0_Pos 8
	(RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable

#define	RTC_MODE2_INTENCLR_ALARM0 (_U_(1) << RTC_MODE2_INTENCLR_ALARM0_Pos)

#define	RTC_MODE2_INTENCLR_ALARM1_Pos 9
	(RTC_MODE2_INTENCLR) Alarm 1 Interrupt Enable

#define	RTC_MODE2_INTENCLR_ALARM1 (_U_(1) << RTC_MODE2_INTENCLR_ALARM1_Pos)

#define	RTC_MODE2_INTENCLR_ALARM_Pos 8
	(RTC_MODE2_INTENCLR) Alarm x Interrupt Enable

#define	RTC_MODE2_INTENCLR_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENCLR_ALARM_Pos)

#define	RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))

#define	RTC_MODE2_INTENCLR_TAMPER_Pos 14
	(RTC_MODE2_INTENCLR) Tamper Enable

#define	RTC_MODE2_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE2_INTENCLR_TAMPER_Pos)

#define	RTC_MODE2_INTENCLR_OVF_Pos 15
	(RTC_MODE2_INTENCLR) Overflow Interrupt Enable

#define	RTC_MODE2_INTENCLR_OVF (_U_(0x1) << RTC_MODE2_INTENCLR_OVF_Pos)

#define	RTC_MODE2_INTENCLR_MASK _U_(0xC3FF)
	(RTC_MODE2_INTENCLR) MASK Register

#define	RTC_MODE0_INTENSET_OFFSET 0x0A
	(RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set

#define	RTC_MODE0_INTENSET_RESETVALUE _U_(0x0000)
	(RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set

#define	RTC_MODE0_INTENSET_PER0_Pos 0
	(RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable

#define	RTC_MODE0_INTENSET_PER0 (_U_(1) << RTC_MODE0_INTENSET_PER0_Pos)

#define	RTC_MODE0_INTENSET_PER1_Pos 1
	(RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable

#define	RTC_MODE0_INTENSET_PER1 (_U_(1) << RTC_MODE0_INTENSET_PER1_Pos)

#define	RTC_MODE0_INTENSET_PER2_Pos 2
	(RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable

#define	RTC_MODE0_INTENSET_PER2 (_U_(1) << RTC_MODE0_INTENSET_PER2_Pos)

#define	RTC_MODE0_INTENSET_PER3_Pos 3
	(RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable

#define	RTC_MODE0_INTENSET_PER3 (_U_(1) << RTC_MODE0_INTENSET_PER3_Pos)

#define	RTC_MODE0_INTENSET_PER4_Pos 4
	(RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable

#define	RTC_MODE0_INTENSET_PER4 (_U_(1) << RTC_MODE0_INTENSET_PER4_Pos)

#define	RTC_MODE0_INTENSET_PER5_Pos 5
	(RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable

#define	RTC_MODE0_INTENSET_PER5 (_U_(1) << RTC_MODE0_INTENSET_PER5_Pos)

#define	RTC_MODE0_INTENSET_PER6_Pos 6
	(RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable

#define	RTC_MODE0_INTENSET_PER6 (_U_(1) << RTC_MODE0_INTENSET_PER6_Pos)

#define	RTC_MODE0_INTENSET_PER7_Pos 7
	(RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable

#define	RTC_MODE0_INTENSET_PER7 (_U_(1) << RTC_MODE0_INTENSET_PER7_Pos)

#define	RTC_MODE0_INTENSET_PER_Pos 0
	(RTC_MODE0_INTENSET) Periodic Interval x Interrupt Enable

#define	RTC_MODE0_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE0_INTENSET_PER_Pos)

#define	RTC_MODE0_INTENSET_PER(value) (RTC_MODE0_INTENSET_PER_Msk & ((value) << RTC_MODE0_INTENSET_PER_Pos))

#define	RTC_MODE0_INTENSET_CMP0_Pos 8
	(RTC_MODE0_INTENSET) Compare 0 Interrupt Enable

#define	RTC_MODE0_INTENSET_CMP0 (_U_(1) << RTC_MODE0_INTENSET_CMP0_Pos)

#define	RTC_MODE0_INTENSET_CMP1_Pos 9
	(RTC_MODE0_INTENSET) Compare 1 Interrupt Enable

#define	RTC_MODE0_INTENSET_CMP1 (_U_(1) << RTC_MODE0_INTENSET_CMP1_Pos)

#define	RTC_MODE0_INTENSET_CMP_Pos 8
	(RTC_MODE0_INTENSET) Compare x Interrupt Enable

#define	RTC_MODE0_INTENSET_CMP_Msk (_U_(0x3) << RTC_MODE0_INTENSET_CMP_Pos)

#define	RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))

#define	RTC_MODE0_INTENSET_TAMPER_Pos 14
	(RTC_MODE0_INTENSET) Tamper Enable

#define	RTC_MODE0_INTENSET_TAMPER (_U_(0x1) << RTC_MODE0_INTENSET_TAMPER_Pos)

#define	RTC_MODE0_INTENSET_OVF_Pos 15
	(RTC_MODE0_INTENSET) Overflow Interrupt Enable

#define	RTC_MODE0_INTENSET_OVF (_U_(0x1) << RTC_MODE0_INTENSET_OVF_Pos)

#define	RTC_MODE0_INTENSET_MASK _U_(0xC3FF)
	(RTC_MODE0_INTENSET) MASK Register

#define	RTC_MODE1_INTENSET_OFFSET 0x0A
	(RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set

#define	RTC_MODE1_INTENSET_RESETVALUE _U_(0x0000)
	(RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set

#define	RTC_MODE1_INTENSET_PER0_Pos 0
	(RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable

#define	RTC_MODE1_INTENSET_PER0 (_U_(1) << RTC_MODE1_INTENSET_PER0_Pos)

#define	RTC_MODE1_INTENSET_PER1_Pos 1
	(RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable

#define	RTC_MODE1_INTENSET_PER1 (_U_(1) << RTC_MODE1_INTENSET_PER1_Pos)

#define	RTC_MODE1_INTENSET_PER2_Pos 2
	(RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable

#define	RTC_MODE1_INTENSET_PER2 (_U_(1) << RTC_MODE1_INTENSET_PER2_Pos)

#define	RTC_MODE1_INTENSET_PER3_Pos 3
	(RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable

#define	RTC_MODE1_INTENSET_PER3 (_U_(1) << RTC_MODE1_INTENSET_PER3_Pos)

#define	RTC_MODE1_INTENSET_PER4_Pos 4
	(RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable

#define	RTC_MODE1_INTENSET_PER4 (_U_(1) << RTC_MODE1_INTENSET_PER4_Pos)

#define	RTC_MODE1_INTENSET_PER5_Pos 5
	(RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable

#define	RTC_MODE1_INTENSET_PER5 (_U_(1) << RTC_MODE1_INTENSET_PER5_Pos)

#define	RTC_MODE1_INTENSET_PER6_Pos 6
	(RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable

#define	RTC_MODE1_INTENSET_PER6 (_U_(1) << RTC_MODE1_INTENSET_PER6_Pos)

#define	RTC_MODE1_INTENSET_PER7_Pos 7
	(RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable

#define	RTC_MODE1_INTENSET_PER7 (_U_(1) << RTC_MODE1_INTENSET_PER7_Pos)

#define	RTC_MODE1_INTENSET_PER_Pos 0
	(RTC_MODE1_INTENSET) Periodic Interval x Interrupt Enable

#define	RTC_MODE1_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE1_INTENSET_PER_Pos)

#define	RTC_MODE1_INTENSET_PER(value) (RTC_MODE1_INTENSET_PER_Msk & ((value) << RTC_MODE1_INTENSET_PER_Pos))

#define	RTC_MODE1_INTENSET_CMP0_Pos 8
	(RTC_MODE1_INTENSET) Compare 0 Interrupt Enable

#define	RTC_MODE1_INTENSET_CMP0 (_U_(1) << RTC_MODE1_INTENSET_CMP0_Pos)

#define	RTC_MODE1_INTENSET_CMP1_Pos 9
	(RTC_MODE1_INTENSET) Compare 1 Interrupt Enable

#define	RTC_MODE1_INTENSET_CMP1 (_U_(1) << RTC_MODE1_INTENSET_CMP1_Pos)

#define	RTC_MODE1_INTENSET_CMP2_Pos 10
	(RTC_MODE1_INTENSET) Compare 2 Interrupt Enable

#define	RTC_MODE1_INTENSET_CMP2 (_U_(1) << RTC_MODE1_INTENSET_CMP2_Pos)

#define	RTC_MODE1_INTENSET_CMP3_Pos 11
	(RTC_MODE1_INTENSET) Compare 3 Interrupt Enable

#define	RTC_MODE1_INTENSET_CMP3 (_U_(1) << RTC_MODE1_INTENSET_CMP3_Pos)

#define	RTC_MODE1_INTENSET_CMP_Pos 8
	(RTC_MODE1_INTENSET) Compare x Interrupt Enable

#define	RTC_MODE1_INTENSET_CMP_Msk (_U_(0xF) << RTC_MODE1_INTENSET_CMP_Pos)

#define	RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))

#define	RTC_MODE1_INTENSET_TAMPER_Pos 14
	(RTC_MODE1_INTENSET) Tamper Enable

#define	RTC_MODE1_INTENSET_TAMPER (_U_(0x1) << RTC_MODE1_INTENSET_TAMPER_Pos)

#define	RTC_MODE1_INTENSET_OVF_Pos 15
	(RTC_MODE1_INTENSET) Overflow Interrupt Enable

#define	RTC_MODE1_INTENSET_OVF (_U_(0x1) << RTC_MODE1_INTENSET_OVF_Pos)

#define	RTC_MODE1_INTENSET_MASK _U_(0xCFFF)
	(RTC_MODE1_INTENSET) MASK Register

#define	RTC_MODE2_INTENSET_OFFSET 0x0A
	(RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set

#define	RTC_MODE2_INTENSET_RESETVALUE _U_(0x0000)
	(RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set

#define	RTC_MODE2_INTENSET_PER0_Pos 0
	(RTC_MODE2_INTENSET) Periodic Interval 0 Enable

#define	RTC_MODE2_INTENSET_PER0 (_U_(1) << RTC_MODE2_INTENSET_PER0_Pos)

#define	RTC_MODE2_INTENSET_PER1_Pos 1
	(RTC_MODE2_INTENSET) Periodic Interval 1 Enable

#define	RTC_MODE2_INTENSET_PER1 (_U_(1) << RTC_MODE2_INTENSET_PER1_Pos)

#define	RTC_MODE2_INTENSET_PER2_Pos 2
	(RTC_MODE2_INTENSET) Periodic Interval 2 Enable

#define	RTC_MODE2_INTENSET_PER2 (_U_(1) << RTC_MODE2_INTENSET_PER2_Pos)

#define	RTC_MODE2_INTENSET_PER3_Pos 3
	(RTC_MODE2_INTENSET) Periodic Interval 3 Enable

#define	RTC_MODE2_INTENSET_PER3 (_U_(1) << RTC_MODE2_INTENSET_PER3_Pos)

#define	RTC_MODE2_INTENSET_PER4_Pos 4
	(RTC_MODE2_INTENSET) Periodic Interval 4 Enable

#define	RTC_MODE2_INTENSET_PER4 (_U_(1) << RTC_MODE2_INTENSET_PER4_Pos)

#define	RTC_MODE2_INTENSET_PER5_Pos 5
	(RTC_MODE2_INTENSET) Periodic Interval 5 Enable

#define	RTC_MODE2_INTENSET_PER5 (_U_(1) << RTC_MODE2_INTENSET_PER5_Pos)

#define	RTC_MODE2_INTENSET_PER6_Pos 6
	(RTC_MODE2_INTENSET) Periodic Interval 6 Enable

#define	RTC_MODE2_INTENSET_PER6 (_U_(1) << RTC_MODE2_INTENSET_PER6_Pos)

#define	RTC_MODE2_INTENSET_PER7_Pos 7
	(RTC_MODE2_INTENSET) Periodic Interval 7 Enable

#define	RTC_MODE2_INTENSET_PER7 (_U_(1) << RTC_MODE2_INTENSET_PER7_Pos)

#define	RTC_MODE2_INTENSET_PER_Pos 0
	(RTC_MODE2_INTENSET) Periodic Interval x Enable

#define	RTC_MODE2_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE2_INTENSET_PER_Pos)

#define	RTC_MODE2_INTENSET_PER(value) (RTC_MODE2_INTENSET_PER_Msk & ((value) << RTC_MODE2_INTENSET_PER_Pos))

#define	RTC_MODE2_INTENSET_ALARM0_Pos 8
	(RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable

#define	RTC_MODE2_INTENSET_ALARM0 (_U_(1) << RTC_MODE2_INTENSET_ALARM0_Pos)

#define	RTC_MODE2_INTENSET_ALARM1_Pos 9
	(RTC_MODE2_INTENSET) Alarm 1 Interrupt Enable

#define	RTC_MODE2_INTENSET_ALARM1 (_U_(1) << RTC_MODE2_INTENSET_ALARM1_Pos)

#define	RTC_MODE2_INTENSET_ALARM_Pos 8
	(RTC_MODE2_INTENSET) Alarm x Interrupt Enable

#define	RTC_MODE2_INTENSET_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENSET_ALARM_Pos)

#define	RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))

#define	RTC_MODE2_INTENSET_TAMPER_Pos 14
	(RTC_MODE2_INTENSET) Tamper Enable

#define	RTC_MODE2_INTENSET_TAMPER (_U_(0x1) << RTC_MODE2_INTENSET_TAMPER_Pos)

#define	RTC_MODE2_INTENSET_OVF_Pos 15
	(RTC_MODE2_INTENSET) Overflow Interrupt Enable

#define	RTC_MODE2_INTENSET_OVF (_U_(0x1) << RTC_MODE2_INTENSET_OVF_Pos)

#define	RTC_MODE2_INTENSET_MASK _U_(0xC3FF)
	(RTC_MODE2_INTENSET) MASK Register

#define	RTC_MODE0_INTFLAG_OFFSET 0x0C
	(RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear

#define	RTC_MODE0_INTFLAG_RESETVALUE _U_(0x0000)
	(RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear

#define	RTC_MODE0_INTFLAG_PER0_Pos 0
	(RTC_MODE0_INTFLAG) Periodic Interval 0

#define	RTC_MODE0_INTFLAG_PER0 (_U_(1) << RTC_MODE0_INTFLAG_PER0_Pos)

#define	RTC_MODE0_INTFLAG_PER1_Pos 1
	(RTC_MODE0_INTFLAG) Periodic Interval 1

#define	RTC_MODE0_INTFLAG_PER1 (_U_(1) << RTC_MODE0_INTFLAG_PER1_Pos)

#define	RTC_MODE0_INTFLAG_PER2_Pos 2
	(RTC_MODE0_INTFLAG) Periodic Interval 2

#define	RTC_MODE0_INTFLAG_PER2 (_U_(1) << RTC_MODE0_INTFLAG_PER2_Pos)

#define	RTC_MODE0_INTFLAG_PER3_Pos 3
	(RTC_MODE0_INTFLAG) Periodic Interval 3

#define	RTC_MODE0_INTFLAG_PER3 (_U_(1) << RTC_MODE0_INTFLAG_PER3_Pos)

#define	RTC_MODE0_INTFLAG_PER4_Pos 4
	(RTC_MODE0_INTFLAG) Periodic Interval 4

#define	RTC_MODE0_INTFLAG_PER4 (_U_(1) << RTC_MODE0_INTFLAG_PER4_Pos)

#define	RTC_MODE0_INTFLAG_PER5_Pos 5
	(RTC_MODE0_INTFLAG) Periodic Interval 5

#define	RTC_MODE0_INTFLAG_PER5 (_U_(1) << RTC_MODE0_INTFLAG_PER5_Pos)

#define	RTC_MODE0_INTFLAG_PER6_Pos 6
	(RTC_MODE0_INTFLAG) Periodic Interval 6

#define	RTC_MODE0_INTFLAG_PER6 (_U_(1) << RTC_MODE0_INTFLAG_PER6_Pos)

#define	RTC_MODE0_INTFLAG_PER7_Pos 7
	(RTC_MODE0_INTFLAG) Periodic Interval 7

#define	RTC_MODE0_INTFLAG_PER7 (_U_(1) << RTC_MODE0_INTFLAG_PER7_Pos)

#define	RTC_MODE0_INTFLAG_PER_Pos 0
	(RTC_MODE0_INTFLAG) Periodic Interval x

#define	RTC_MODE0_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE0_INTFLAG_PER_Pos)

#define	RTC_MODE0_INTFLAG_PER(value) (RTC_MODE0_INTFLAG_PER_Msk & ((value) << RTC_MODE0_INTFLAG_PER_Pos))

#define	RTC_MODE0_INTFLAG_CMP0_Pos 8
	(RTC_MODE0_INTFLAG) Compare 0

#define	RTC_MODE0_INTFLAG_CMP0 (_U_(1) << RTC_MODE0_INTFLAG_CMP0_Pos)

#define	RTC_MODE0_INTFLAG_CMP1_Pos 9
	(RTC_MODE0_INTFLAG) Compare 1

#define	RTC_MODE0_INTFLAG_CMP1 (_U_(1) << RTC_MODE0_INTFLAG_CMP1_Pos)

#define	RTC_MODE0_INTFLAG_CMP_Pos 8
	(RTC_MODE0_INTFLAG) Compare x

#define	RTC_MODE0_INTFLAG_CMP_Msk (_U_(0x3) << RTC_MODE0_INTFLAG_CMP_Pos)

#define	RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))

#define	RTC_MODE0_INTFLAG_TAMPER_Pos 14
	(RTC_MODE0_INTFLAG) Tamper

#define	RTC_MODE0_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE0_INTFLAG_TAMPER_Pos)

#define	RTC_MODE0_INTFLAG_OVF_Pos 15
	(RTC_MODE0_INTFLAG) Overflow

#define	RTC_MODE0_INTFLAG_OVF (_U_(0x1) << RTC_MODE0_INTFLAG_OVF_Pos)

#define	RTC_MODE0_INTFLAG_MASK _U_(0xC3FF)
	(RTC_MODE0_INTFLAG) MASK Register

#define	RTC_MODE1_INTFLAG_OFFSET 0x0C
	(RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear

#define	RTC_MODE1_INTFLAG_RESETVALUE _U_(0x0000)
	(RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear

#define	RTC_MODE1_INTFLAG_PER0_Pos 0
	(RTC_MODE1_INTFLAG) Periodic Interval 0

#define	RTC_MODE1_INTFLAG_PER0 (_U_(1) << RTC_MODE1_INTFLAG_PER0_Pos)

#define	RTC_MODE1_INTFLAG_PER1_Pos 1
	(RTC_MODE1_INTFLAG) Periodic Interval 1

#define	RTC_MODE1_INTFLAG_PER1 (_U_(1) << RTC_MODE1_INTFLAG_PER1_Pos)

#define	RTC_MODE1_INTFLAG_PER2_Pos 2
	(RTC_MODE1_INTFLAG) Periodic Interval 2

#define	RTC_MODE1_INTFLAG_PER2 (_U_(1) << RTC_MODE1_INTFLAG_PER2_Pos)

#define	RTC_MODE1_INTFLAG_PER3_Pos 3
	(RTC_MODE1_INTFLAG) Periodic Interval 3

#define	RTC_MODE1_INTFLAG_PER3 (_U_(1) << RTC_MODE1_INTFLAG_PER3_Pos)

#define	RTC_MODE1_INTFLAG_PER4_Pos 4
	(RTC_MODE1_INTFLAG) Periodic Interval 4

#define	RTC_MODE1_INTFLAG_PER4 (_U_(1) << RTC_MODE1_INTFLAG_PER4_Pos)

#define	RTC_MODE1_INTFLAG_PER5_Pos 5
	(RTC_MODE1_INTFLAG) Periodic Interval 5

#define	RTC_MODE1_INTFLAG_PER5 (_U_(1) << RTC_MODE1_INTFLAG_PER5_Pos)

#define	RTC_MODE1_INTFLAG_PER6_Pos 6
	(RTC_MODE1_INTFLAG) Periodic Interval 6

#define	RTC_MODE1_INTFLAG_PER6 (_U_(1) << RTC_MODE1_INTFLAG_PER6_Pos)

#define	RTC_MODE1_INTFLAG_PER7_Pos 7
	(RTC_MODE1_INTFLAG) Periodic Interval 7

#define	RTC_MODE1_INTFLAG_PER7 (_U_(1) << RTC_MODE1_INTFLAG_PER7_Pos)

#define	RTC_MODE1_INTFLAG_PER_Pos 0
	(RTC_MODE1_INTFLAG) Periodic Interval x

#define	RTC_MODE1_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE1_INTFLAG_PER_Pos)

#define	RTC_MODE1_INTFLAG_PER(value) (RTC_MODE1_INTFLAG_PER_Msk & ((value) << RTC_MODE1_INTFLAG_PER_Pos))

#define	RTC_MODE1_INTFLAG_CMP0_Pos 8
	(RTC_MODE1_INTFLAG) Compare 0

#define	RTC_MODE1_INTFLAG_CMP0 (_U_(1) << RTC_MODE1_INTFLAG_CMP0_Pos)

#define	RTC_MODE1_INTFLAG_CMP1_Pos 9
	(RTC_MODE1_INTFLAG) Compare 1

#define	RTC_MODE1_INTFLAG_CMP1 (_U_(1) << RTC_MODE1_INTFLAG_CMP1_Pos)

#define	RTC_MODE1_INTFLAG_CMP2_Pos 10
	(RTC_MODE1_INTFLAG) Compare 2

#define	RTC_MODE1_INTFLAG_CMP2 (_U_(1) << RTC_MODE1_INTFLAG_CMP2_Pos)

#define	RTC_MODE1_INTFLAG_CMP3_Pos 11
	(RTC_MODE1_INTFLAG) Compare 3

#define	RTC_MODE1_INTFLAG_CMP3 (_U_(1) << RTC_MODE1_INTFLAG_CMP3_Pos)

#define	RTC_MODE1_INTFLAG_CMP_Pos 8
	(RTC_MODE1_INTFLAG) Compare x

#define	RTC_MODE1_INTFLAG_CMP_Msk (_U_(0xF) << RTC_MODE1_INTFLAG_CMP_Pos)

#define	RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))

#define	RTC_MODE1_INTFLAG_TAMPER_Pos 14
	(RTC_MODE1_INTFLAG) Tamper

#define	RTC_MODE1_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE1_INTFLAG_TAMPER_Pos)

#define	RTC_MODE1_INTFLAG_OVF_Pos 15
	(RTC_MODE1_INTFLAG) Overflow

#define	RTC_MODE1_INTFLAG_OVF (_U_(0x1) << RTC_MODE1_INTFLAG_OVF_Pos)

#define	RTC_MODE1_INTFLAG_MASK _U_(0xCFFF)
	(RTC_MODE1_INTFLAG) MASK Register

#define	RTC_MODE2_INTFLAG_OFFSET 0x0C
	(RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear

#define	RTC_MODE2_INTFLAG_RESETVALUE _U_(0x0000)
	(RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear

#define	RTC_MODE2_INTFLAG_PER0_Pos 0
	(RTC_MODE2_INTFLAG) Periodic Interval 0

#define	RTC_MODE2_INTFLAG_PER0 (_U_(1) << RTC_MODE2_INTFLAG_PER0_Pos)

#define	RTC_MODE2_INTFLAG_PER1_Pos 1
	(RTC_MODE2_INTFLAG) Periodic Interval 1

#define	RTC_MODE2_INTFLAG_PER1 (_U_(1) << RTC_MODE2_INTFLAG_PER1_Pos)

#define	RTC_MODE2_INTFLAG_PER2_Pos 2
	(RTC_MODE2_INTFLAG) Periodic Interval 2

#define	RTC_MODE2_INTFLAG_PER2 (_U_(1) << RTC_MODE2_INTFLAG_PER2_Pos)

#define	RTC_MODE2_INTFLAG_PER3_Pos 3
	(RTC_MODE2_INTFLAG) Periodic Interval 3

#define	RTC_MODE2_INTFLAG_PER3 (_U_(1) << RTC_MODE2_INTFLAG_PER3_Pos)

#define	RTC_MODE2_INTFLAG_PER4_Pos 4
	(RTC_MODE2_INTFLAG) Periodic Interval 4

#define	RTC_MODE2_INTFLAG_PER4 (_U_(1) << RTC_MODE2_INTFLAG_PER4_Pos)

#define	RTC_MODE2_INTFLAG_PER5_Pos 5
	(RTC_MODE2_INTFLAG) Periodic Interval 5

#define	RTC_MODE2_INTFLAG_PER5 (_U_(1) << RTC_MODE2_INTFLAG_PER5_Pos)

#define	RTC_MODE2_INTFLAG_PER6_Pos 6
	(RTC_MODE2_INTFLAG) Periodic Interval 6

#define	RTC_MODE2_INTFLAG_PER6 (_U_(1) << RTC_MODE2_INTFLAG_PER6_Pos)

#define	RTC_MODE2_INTFLAG_PER7_Pos 7
	(RTC_MODE2_INTFLAG) Periodic Interval 7

#define	RTC_MODE2_INTFLAG_PER7 (_U_(1) << RTC_MODE2_INTFLAG_PER7_Pos)

#define	RTC_MODE2_INTFLAG_PER_Pos 0
	(RTC_MODE2_INTFLAG) Periodic Interval x

#define	RTC_MODE2_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE2_INTFLAG_PER_Pos)

#define	RTC_MODE2_INTFLAG_PER(value) (RTC_MODE2_INTFLAG_PER_Msk & ((value) << RTC_MODE2_INTFLAG_PER_Pos))

#define	RTC_MODE2_INTFLAG_ALARM0_Pos 8
	(RTC_MODE2_INTFLAG) Alarm 0

#define	RTC_MODE2_INTFLAG_ALARM0 (_U_(1) << RTC_MODE2_INTFLAG_ALARM0_Pos)

#define	RTC_MODE2_INTFLAG_ALARM1_Pos 9
	(RTC_MODE2_INTFLAG) Alarm 1

#define	RTC_MODE2_INTFLAG_ALARM1 (_U_(1) << RTC_MODE2_INTFLAG_ALARM1_Pos)

#define	RTC_MODE2_INTFLAG_ALARM_Pos 8
	(RTC_MODE2_INTFLAG) Alarm x

#define	RTC_MODE2_INTFLAG_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTFLAG_ALARM_Pos)

#define	RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))

#define	RTC_MODE2_INTFLAG_TAMPER_Pos 14
	(RTC_MODE2_INTFLAG) Tamper

#define	RTC_MODE2_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE2_INTFLAG_TAMPER_Pos)

#define	RTC_MODE2_INTFLAG_OVF_Pos 15
	(RTC_MODE2_INTFLAG) Overflow

#define	RTC_MODE2_INTFLAG_OVF (_U_(0x1) << RTC_MODE2_INTFLAG_OVF_Pos)

#define	RTC_MODE2_INTFLAG_MASK _U_(0xC3FF)
	(RTC_MODE2_INTFLAG) MASK Register

#define	RTC_DBGCTRL_OFFSET 0x0E
	(RTC_DBGCTRL offset) Debug Control

#define	RTC_DBGCTRL_RESETVALUE _U_(0x00)
	(RTC_DBGCTRL reset_value) Debug Control

#define	RTC_DBGCTRL_DBGRUN_Pos 0
	(RTC_DBGCTRL) Run During Debug

#define	RTC_DBGCTRL_DBGRUN (_U_(0x1) << RTC_DBGCTRL_DBGRUN_Pos)

#define	RTC_DBGCTRL_MASK _U_(0x01)
	(RTC_DBGCTRL) MASK Register

#define	RTC_MODE0_SYNCBUSY_OFFSET 0x10
	(RTC_MODE0_SYNCBUSY offset) MODE0 Synchronization Busy Status

#define	RTC_MODE0_SYNCBUSY_RESETVALUE _U_(0x00000000)
	(RTC_MODE0_SYNCBUSY reset_value) MODE0 Synchronization Busy Status

#define	RTC_MODE0_SYNCBUSY_SWRST_Pos 0
	(RTC_MODE0_SYNCBUSY) Software Reset Busy

#define	RTC_MODE0_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE0_SYNCBUSY_SWRST_Pos)

#define	RTC_MODE0_SYNCBUSY_ENABLE_Pos 1
	(RTC_MODE0_SYNCBUSY) Enable Bit Busy

#define	RTC_MODE0_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE0_SYNCBUSY_ENABLE_Pos)

#define	RTC_MODE0_SYNCBUSY_FREQCORR_Pos 2
	(RTC_MODE0_SYNCBUSY) FREQCORR Register Busy

#define	RTC_MODE0_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos)

#define	RTC_MODE0_SYNCBUSY_COUNT_Pos 3
	(RTC_MODE0_SYNCBUSY) COUNT Register Busy

#define	RTC_MODE0_SYNCBUSY_COUNT (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNT_Pos)

#define	RTC_MODE0_SYNCBUSY_COMP0_Pos 5
	(RTC_MODE0_SYNCBUSY) COMP 0 Register Busy

#define	RTC_MODE0_SYNCBUSY_COMP0 (_U_(1) << RTC_MODE0_SYNCBUSY_COMP0_Pos)

#define	RTC_MODE0_SYNCBUSY_COMP1_Pos 6
	(RTC_MODE0_SYNCBUSY) COMP 1 Register Busy

#define	RTC_MODE0_SYNCBUSY_COMP1 (_U_(1) << RTC_MODE0_SYNCBUSY_COMP1_Pos)

#define	RTC_MODE0_SYNCBUSY_COMP_Pos 5
	(RTC_MODE0_SYNCBUSY) COMP x Register Busy

#define	RTC_MODE0_SYNCBUSY_COMP_Msk (_U_(0x3) << RTC_MODE0_SYNCBUSY_COMP_Pos)

#define	RTC_MODE0_SYNCBUSY_COMP(value) (RTC_MODE0_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE0_SYNCBUSY_COMP_Pos))

#define	RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos 15
	(RTC_MODE0_SYNCBUSY) Count Synchronization Enable Bit Busy

#define	RTC_MODE0_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos)

#define	RTC_MODE0_SYNCBUSY_GP0_Pos 16
	(RTC_MODE0_SYNCBUSY) General Purpose 0 Register Busy

#define	RTC_MODE0_SYNCBUSY_GP0 (_U_(1) << RTC_MODE0_SYNCBUSY_GP0_Pos)

#define	RTC_MODE0_SYNCBUSY_GP1_Pos 17
	(RTC_MODE0_SYNCBUSY) General Purpose 1 Register Busy

#define	RTC_MODE0_SYNCBUSY_GP1 (_U_(1) << RTC_MODE0_SYNCBUSY_GP1_Pos)

#define	RTC_MODE0_SYNCBUSY_GP2_Pos 18
	(RTC_MODE0_SYNCBUSY) General Purpose 2 Register Busy

#define	RTC_MODE0_SYNCBUSY_GP2 (_U_(1) << RTC_MODE0_SYNCBUSY_GP2_Pos)

#define	RTC_MODE0_SYNCBUSY_GP3_Pos 19
	(RTC_MODE0_SYNCBUSY) General Purpose 3 Register Busy

#define	RTC_MODE0_SYNCBUSY_GP3 (_U_(1) << RTC_MODE0_SYNCBUSY_GP3_Pos)

#define	RTC_MODE0_SYNCBUSY_GP_Pos 16
	(RTC_MODE0_SYNCBUSY) General Purpose x Register Busy

#define	RTC_MODE0_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE0_SYNCBUSY_GP_Pos)

#define	RTC_MODE0_SYNCBUSY_GP(value) (RTC_MODE0_SYNCBUSY_GP_Msk & ((value) << RTC_MODE0_SYNCBUSY_GP_Pos))

#define	RTC_MODE0_SYNCBUSY_MASK _U_(0x000F806F)
	(RTC_MODE0_SYNCBUSY) MASK Register

#define	RTC_MODE1_SYNCBUSY_OFFSET 0x10
	(RTC_MODE1_SYNCBUSY offset) MODE1 Synchronization Busy Status

#define	RTC_MODE1_SYNCBUSY_RESETVALUE _U_(0x00000000)
	(RTC_MODE1_SYNCBUSY reset_value) MODE1 Synchronization Busy Status

#define	RTC_MODE1_SYNCBUSY_SWRST_Pos 0
	(RTC_MODE1_SYNCBUSY) Software Reset Bit Busy

#define	RTC_MODE1_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE1_SYNCBUSY_SWRST_Pos)

#define	RTC_MODE1_SYNCBUSY_ENABLE_Pos 1
	(RTC_MODE1_SYNCBUSY) Enable Bit Busy

#define	RTC_MODE1_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE1_SYNCBUSY_ENABLE_Pos)

#define	RTC_MODE1_SYNCBUSY_FREQCORR_Pos 2
	(RTC_MODE1_SYNCBUSY) FREQCORR Register Busy

#define	RTC_MODE1_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos)

#define	RTC_MODE1_SYNCBUSY_COUNT_Pos 3
	(RTC_MODE1_SYNCBUSY) COUNT Register Busy

#define	RTC_MODE1_SYNCBUSY_COUNT (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNT_Pos)

#define	RTC_MODE1_SYNCBUSY_PER_Pos 4
	(RTC_MODE1_SYNCBUSY) PER Register Busy

#define	RTC_MODE1_SYNCBUSY_PER (_U_(0x1) << RTC_MODE1_SYNCBUSY_PER_Pos)

#define	RTC_MODE1_SYNCBUSY_COMP0_Pos 5
	(RTC_MODE1_SYNCBUSY) COMP 0 Register Busy

#define	RTC_MODE1_SYNCBUSY_COMP0 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP0_Pos)

#define	RTC_MODE1_SYNCBUSY_COMP1_Pos 6
	(RTC_MODE1_SYNCBUSY) COMP 1 Register Busy

#define	RTC_MODE1_SYNCBUSY_COMP1 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP1_Pos)

#define	RTC_MODE1_SYNCBUSY_COMP2_Pos 7
	(RTC_MODE1_SYNCBUSY) COMP 2 Register Busy

#define	RTC_MODE1_SYNCBUSY_COMP2 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP2_Pos)

#define	RTC_MODE1_SYNCBUSY_COMP3_Pos 8
	(RTC_MODE1_SYNCBUSY) COMP 3 Register Busy

#define	RTC_MODE1_SYNCBUSY_COMP3 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP3_Pos)

#define	RTC_MODE1_SYNCBUSY_COMP_Pos 5
	(RTC_MODE1_SYNCBUSY) COMP x Register Busy

#define	RTC_MODE1_SYNCBUSY_COMP_Msk (_U_(0xF) << RTC_MODE1_SYNCBUSY_COMP_Pos)

#define	RTC_MODE1_SYNCBUSY_COMP(value) (RTC_MODE1_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE1_SYNCBUSY_COMP_Pos))

#define	RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos 15
	(RTC_MODE1_SYNCBUSY) Count Synchronization Enable Bit Busy

#define	RTC_MODE1_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos)

#define	RTC_MODE1_SYNCBUSY_GP0_Pos 16
	(RTC_MODE1_SYNCBUSY) General Purpose 0 Register Busy

#define	RTC_MODE1_SYNCBUSY_GP0 (_U_(1) << RTC_MODE1_SYNCBUSY_GP0_Pos)

#define	RTC_MODE1_SYNCBUSY_GP1_Pos 17
	(RTC_MODE1_SYNCBUSY) General Purpose 1 Register Busy

#define	RTC_MODE1_SYNCBUSY_GP1 (_U_(1) << RTC_MODE1_SYNCBUSY_GP1_Pos)

#define	RTC_MODE1_SYNCBUSY_GP2_Pos 18
	(RTC_MODE1_SYNCBUSY) General Purpose 2 Register Busy

#define	RTC_MODE1_SYNCBUSY_GP2 (_U_(1) << RTC_MODE1_SYNCBUSY_GP2_Pos)

#define	RTC_MODE1_SYNCBUSY_GP3_Pos 19
	(RTC_MODE1_SYNCBUSY) General Purpose 3 Register Busy

#define	RTC_MODE1_SYNCBUSY_GP3 (_U_(1) << RTC_MODE1_SYNCBUSY_GP3_Pos)

#define	RTC_MODE1_SYNCBUSY_GP_Pos 16
	(RTC_MODE1_SYNCBUSY) General Purpose x Register Busy

#define	RTC_MODE1_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE1_SYNCBUSY_GP_Pos)

#define	RTC_MODE1_SYNCBUSY_GP(value) (RTC_MODE1_SYNCBUSY_GP_Msk & ((value) << RTC_MODE1_SYNCBUSY_GP_Pos))

#define	RTC_MODE1_SYNCBUSY_MASK _U_(0x000F81FF)
	(RTC_MODE1_SYNCBUSY) MASK Register

#define	RTC_MODE2_SYNCBUSY_OFFSET 0x10
	(RTC_MODE2_SYNCBUSY offset) MODE2 Synchronization Busy Status

#define	RTC_MODE2_SYNCBUSY_RESETVALUE _U_(0x00000000)
	(RTC_MODE2_SYNCBUSY reset_value) MODE2 Synchronization Busy Status

#define	RTC_MODE2_SYNCBUSY_SWRST_Pos 0
	(RTC_MODE2_SYNCBUSY) Software Reset Bit Busy

#define	RTC_MODE2_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE2_SYNCBUSY_SWRST_Pos)

#define	RTC_MODE2_SYNCBUSY_ENABLE_Pos 1
	(RTC_MODE2_SYNCBUSY) Enable Bit Busy

#define	RTC_MODE2_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE2_SYNCBUSY_ENABLE_Pos)

#define	RTC_MODE2_SYNCBUSY_FREQCORR_Pos 2
	(RTC_MODE2_SYNCBUSY) FREQCORR Register Busy

#define	RTC_MODE2_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos)

#define	RTC_MODE2_SYNCBUSY_CLOCK_Pos 3
	(RTC_MODE2_SYNCBUSY) CLOCK Register Busy

#define	RTC_MODE2_SYNCBUSY_CLOCK (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCK_Pos)

#define	RTC_MODE2_SYNCBUSY_ALARM0_Pos 5
	(RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy

#define	RTC_MODE2_SYNCBUSY_ALARM0 (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM0_Pos)

#define	RTC_MODE2_SYNCBUSY_ALARM1_Pos 6
	(RTC_MODE2_SYNCBUSY) ALARM 1 Register Busy

#define	RTC_MODE2_SYNCBUSY_ALARM1 (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM1_Pos)

#define	RTC_MODE2_SYNCBUSY_ALARM_Pos 5
	(RTC_MODE2_SYNCBUSY) ALARM x Register Busy

#define	RTC_MODE2_SYNCBUSY_ALARM_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_ALARM_Pos)

#define	RTC_MODE2_SYNCBUSY_ALARM(value) (RTC_MODE2_SYNCBUSY_ALARM_Msk & ((value) << RTC_MODE2_SYNCBUSY_ALARM_Pos))

#define	RTC_MODE2_SYNCBUSY_MASK0_Pos 11
	(RTC_MODE2_SYNCBUSY) MASK 0 Register Busy

#define	RTC_MODE2_SYNCBUSY_MASK0 (_U_(1) << RTC_MODE2_SYNCBUSY_MASK0_Pos)

#define	RTC_MODE2_SYNCBUSY_MASK1_Pos 12
	(RTC_MODE2_SYNCBUSY) MASK 1 Register Busy

#define	RTC_MODE2_SYNCBUSY_MASK1 (_U_(1) << RTC_MODE2_SYNCBUSY_MASK1_Pos)

#define	RTC_MODE2_SYNCBUSY_MASK_Pos 11
	(RTC_MODE2_SYNCBUSY) MASK x Register Busy

#define	RTC_MODE2_SYNCBUSY_MASK_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_MASK_Pos)

#define	RTC_MODE2_SYNCBUSY_MASK(value) (RTC_MODE2_SYNCBUSY_MASK_Msk & ((value) << RTC_MODE2_SYNCBUSY_MASK_Pos))

#define	RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos 15
	(RTC_MODE2_SYNCBUSY) Clock Synchronization Enable Bit Busy

#define	RTC_MODE2_SYNCBUSY_CLOCKSYNC (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos)

#define	RTC_MODE2_SYNCBUSY_GP0_Pos 16
	(RTC_MODE2_SYNCBUSY) General Purpose 0 Register Busy

#define	RTC_MODE2_SYNCBUSY_GP0 (_U_(1) << RTC_MODE2_SYNCBUSY_GP0_Pos)

#define	RTC_MODE2_SYNCBUSY_GP1_Pos 17
	(RTC_MODE2_SYNCBUSY) General Purpose 1 Register Busy

#define	RTC_MODE2_SYNCBUSY_GP1 (_U_(1) << RTC_MODE2_SYNCBUSY_GP1_Pos)

#define	RTC_MODE2_SYNCBUSY_GP2_Pos 18
	(RTC_MODE2_SYNCBUSY) General Purpose 2 Register Busy

#define	RTC_MODE2_SYNCBUSY_GP2 (_U_(1) << RTC_MODE2_SYNCBUSY_GP2_Pos)

#define	RTC_MODE2_SYNCBUSY_GP3_Pos 19
	(RTC_MODE2_SYNCBUSY) General Purpose 3 Register Busy

#define	RTC_MODE2_SYNCBUSY_GP3 (_U_(1) << RTC_MODE2_SYNCBUSY_GP3_Pos)

#define	RTC_MODE2_SYNCBUSY_GP_Pos 16
	(RTC_MODE2_SYNCBUSY) General Purpose x Register Busy

#define	RTC_MODE2_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE2_SYNCBUSY_GP_Pos)

#define	RTC_MODE2_SYNCBUSY_GP(value) (RTC_MODE2_SYNCBUSY_GP_Msk & ((value) << RTC_MODE2_SYNCBUSY_GP_Pos))

#define	RTC_MODE2_SYNCBUSY_MASK_ _U_(0x000F986F)
	(RTC_MODE2_SYNCBUSY) MASK Register

#define	RTC_FREQCORR_OFFSET 0x14
	(RTC_FREQCORR offset) Frequency Correction

#define	RTC_FREQCORR_RESETVALUE _U_(0x00)
	(RTC_FREQCORR reset_value) Frequency Correction

#define	RTC_FREQCORR_VALUE_Pos 0
	(RTC_FREQCORR) Correction Value

#define	RTC_FREQCORR_VALUE_Msk (_U_(0x7F) << RTC_FREQCORR_VALUE_Pos)

#define	RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))

#define	RTC_FREQCORR_SIGN_Pos 7
	(RTC_FREQCORR) Correction Sign

#define	RTC_FREQCORR_SIGN (_U_(0x1) << RTC_FREQCORR_SIGN_Pos)

#define	RTC_FREQCORR_MASK _U_(0xFF)
	(RTC_FREQCORR) MASK Register

#define	RTC_MODE0_COUNT_OFFSET 0x18
	(RTC_MODE0_COUNT offset) MODE0 Counter Value

#define	RTC_MODE0_COUNT_RESETVALUE _U_(0x00000000)
	(RTC_MODE0_COUNT reset_value) MODE0 Counter Value

#define	RTC_MODE0_COUNT_COUNT_Pos 0
	(RTC_MODE0_COUNT) Counter Value

#define	RTC_MODE0_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos)

#define	RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))

#define	RTC_MODE0_COUNT_MASK _U_(0xFFFFFFFF)
	(RTC_MODE0_COUNT) MASK Register

#define	RTC_MODE1_COUNT_OFFSET 0x18
	(RTC_MODE1_COUNT offset) MODE1 Counter Value

#define	RTC_MODE1_COUNT_RESETVALUE _U_(0x0000)
	(RTC_MODE1_COUNT reset_value) MODE1 Counter Value

#define	RTC_MODE1_COUNT_COUNT_Pos 0
	(RTC_MODE1_COUNT) Counter Value

#define	RTC_MODE1_COUNT_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos)

#define	RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))

#define	RTC_MODE1_COUNT_MASK _U_(0xFFFF)
	(RTC_MODE1_COUNT) MASK Register

#define	RTC_MODE2_CLOCK_OFFSET 0x18
	(RTC_MODE2_CLOCK offset) MODE2 Clock Value

#define	RTC_MODE2_CLOCK_RESETVALUE _U_(0x00000000)
	(RTC_MODE2_CLOCK reset_value) MODE2 Clock Value

#define	RTC_MODE2_CLOCK_SECOND_Pos 0
	(RTC_MODE2_CLOCK) Second

#define	RTC_MODE2_CLOCK_SECOND_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos)

#define	RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))

#define	RTC_MODE2_CLOCK_MINUTE_Pos 6
	(RTC_MODE2_CLOCK) Minute

#define	RTC_MODE2_CLOCK_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos)

#define	RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))

#define	RTC_MODE2_CLOCK_HOUR_Pos 12
	(RTC_MODE2_CLOCK) Hour

#define	RTC_MODE2_CLOCK_HOUR_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos)

#define	RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))

#define	RTC_MODE2_CLOCK_HOUR_AM_Val _U_(0x0)
	(RTC_MODE2_CLOCK) AM when CLKREP in 12-hour

#define	RTC_MODE2_CLOCK_HOUR_PM_Val _U_(0x10)
	(RTC_MODE2_CLOCK) PM when CLKREP in 12-hour

#define	RTC_MODE2_CLOCK_HOUR_AM (RTC_MODE2_CLOCK_HOUR_AM_Val << RTC_MODE2_CLOCK_HOUR_Pos)

#define	RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)

#define	RTC_MODE2_CLOCK_DAY_Pos 17
	(RTC_MODE2_CLOCK) Day

#define	RTC_MODE2_CLOCK_DAY_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_DAY_Pos)

#define	RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))

#define	RTC_MODE2_CLOCK_MONTH_Pos 22
	(RTC_MODE2_CLOCK) Month

#define	RTC_MODE2_CLOCK_MONTH_Msk (_U_(0xF) << RTC_MODE2_CLOCK_MONTH_Pos)

#define	RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))

#define	RTC_MODE2_CLOCK_YEAR_Pos 26
	(RTC_MODE2_CLOCK) Year

#define	RTC_MODE2_CLOCK_YEAR_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos)

#define	RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))

#define	RTC_MODE2_CLOCK_MASK _U_(0xFFFFFFFF)
	(RTC_MODE2_CLOCK) MASK Register

#define	RTC_MODE1_PER_OFFSET 0x1C
	(RTC_MODE1_PER offset) MODE1 Counter Period

#define	RTC_MODE1_PER_RESETVALUE _U_(0x0000)
	(RTC_MODE1_PER reset_value) MODE1 Counter Period

#define	RTC_MODE1_PER_PER_Pos 0
	(RTC_MODE1_PER) Counter Period

#define	RTC_MODE1_PER_PER_Msk (_U_(0xFFFF) << RTC_MODE1_PER_PER_Pos)

#define	RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))

#define	RTC_MODE1_PER_MASK _U_(0xFFFF)
	(RTC_MODE1_PER) MASK Register

#define	RTC_MODE0_COMP_OFFSET 0x20
	(RTC_MODE0_COMP offset) MODE0 Compare n Value

#define	RTC_MODE0_COMP_RESETVALUE _U_(0x00000000)
	(RTC_MODE0_COMP reset_value) MODE0 Compare n Value

#define	RTC_MODE0_COMP_COMP_Pos 0
	(RTC_MODE0_COMP) Compare Value

#define	RTC_MODE0_COMP_COMP_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos)

#define	RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))

#define	RTC_MODE0_COMP_MASK _U_(0xFFFFFFFF)
	(RTC_MODE0_COMP) MASK Register

#define	RTC_MODE1_COMP_OFFSET 0x20
	(RTC_MODE1_COMP offset) MODE1 Compare n Value

#define	RTC_MODE1_COMP_RESETVALUE _U_(0x0000)
	(RTC_MODE1_COMP reset_value) MODE1 Compare n Value

#define	RTC_MODE1_COMP_COMP_Pos 0
	(RTC_MODE1_COMP) Compare Value

#define	RTC_MODE1_COMP_COMP_Msk (_U_(0xFFFF) << RTC_MODE1_COMP_COMP_Pos)

#define	RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))

#define	RTC_MODE1_COMP_MASK _U_(0xFFFF)
	(RTC_MODE1_COMP) MASK Register

#define	RTC_MODE2_ALARM_OFFSET 0x20
	(RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value

#define	RTC_MODE2_ALARM_RESETVALUE _U_(0x00000000)
	(RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value

#define	RTC_MODE2_ALARM_SECOND_Pos 0
	(RTC_MODE2_ALARM) Second

#define	RTC_MODE2_ALARM_SECOND_Msk (_U_(0x3F) << RTC_MODE2_ALARM_SECOND_Pos)

#define	RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))

#define	RTC_MODE2_ALARM_MINUTE_Pos 6
	(RTC_MODE2_ALARM) Minute

#define	RTC_MODE2_ALARM_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos)

#define	RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))

#define	RTC_MODE2_ALARM_HOUR_Pos 12
	(RTC_MODE2_ALARM) Hour

#define	RTC_MODE2_ALARM_HOUR_Msk (_U_(0x1F) << RTC_MODE2_ALARM_HOUR_Pos)

#define	RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))

#define	RTC_MODE2_ALARM_HOUR_AM_Val _U_(0x0)
	(RTC_MODE2_ALARM) Morning hour

#define	RTC_MODE2_ALARM_HOUR_PM_Val _U_(0x10)
	(RTC_MODE2_ALARM) Afternoon hour

#define	RTC_MODE2_ALARM_HOUR_AM (RTC_MODE2_ALARM_HOUR_AM_Val << RTC_MODE2_ALARM_HOUR_Pos)

#define	RTC_MODE2_ALARM_HOUR_PM (RTC_MODE2_ALARM_HOUR_PM_Val << RTC_MODE2_ALARM_HOUR_Pos)

#define	RTC_MODE2_ALARM_DAY_Pos 17
	(RTC_MODE2_ALARM) Day

#define	RTC_MODE2_ALARM_DAY_Msk (_U_(0x1F) << RTC_MODE2_ALARM_DAY_Pos)

#define	RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))

#define	RTC_MODE2_ALARM_MONTH_Pos 22
	(RTC_MODE2_ALARM) Month

#define	RTC_MODE2_ALARM_MONTH_Msk (_U_(0xF) << RTC_MODE2_ALARM_MONTH_Pos)

#define	RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))

#define	RTC_MODE2_ALARM_YEAR_Pos 26
	(RTC_MODE2_ALARM) Year

#define	RTC_MODE2_ALARM_YEAR_Msk (_U_(0x3F) << RTC_MODE2_ALARM_YEAR_Pos)

#define	RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))

#define	RTC_MODE2_ALARM_MASK _U_(0xFFFFFFFF)
	(RTC_MODE2_ALARM) MASK Register

#define	RTC_MODE2_MASK_OFFSET 0x24
	(RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask

#define	RTC_MODE2_MASK_RESETVALUE _U_(0x00)
	(RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask

#define	RTC_MODE2_MASK_SEL_Pos 0
	(RTC_MODE2_MASK) Alarm Mask Selection

#define	RTC_MODE2_MASK_SEL_Msk (_U_(0x7) << RTC_MODE2_MASK_SEL_Pos)

#define	RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))

#define	RTC_MODE2_MASK_SEL_OFF_Val _U_(0x0)
	(RTC_MODE2_MASK) Alarm Disabled

#define	RTC_MODE2_MASK_SEL_SS_Val _U_(0x1)
	(RTC_MODE2_MASK) Match seconds only

#define	RTC_MODE2_MASK_SEL_MMSS_Val _U_(0x2)
	(RTC_MODE2_MASK) Match seconds and minutes only

#define	RTC_MODE2_MASK_SEL_HHMMSS_Val _U_(0x3)
	(RTC_MODE2_MASK) Match seconds, minutes, and hours only

#define	RTC_MODE2_MASK_SEL_DDHHMMSS_Val _U_(0x4)
	(RTC_MODE2_MASK) Match seconds, minutes, hours, and days only

#define	RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U_(0x5)
	(RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only

#define	RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U_(0x6)
	(RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years

#define	RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos)

#define	RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos)

#define	RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos)

#define	RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)

#define	RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)

#define	RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)

#define	RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)

#define	RTC_MODE2_MASK_MASK _U_(0x07)
	(RTC_MODE2_MASK) MASK Register

#define	RTC_GP_OFFSET 0x40
	(RTC_GP offset) General Purpose

#define	RTC_GP_RESETVALUE _U_(0x00000000)
	(RTC_GP reset_value) General Purpose

#define	RTC_GP_GP_Pos 0
	(RTC_GP) General Purpose

#define	RTC_GP_GP_Msk (_U_(0xFFFFFFFF) << RTC_GP_GP_Pos)

#define	RTC_GP_GP(value) (RTC_GP_GP_Msk & ((value) << RTC_GP_GP_Pos))

#define	RTC_GP_MASK _U_(0xFFFFFFFF)
	(RTC_GP) MASK Register

#define	RTC_TAMPCTRL_OFFSET 0x60
	(RTC_TAMPCTRL offset) Tamper Control

#define	RTC_TAMPCTRL_RESETVALUE _U_(0x00000000)
	(RTC_TAMPCTRL reset_value) Tamper Control

#define	RTC_TAMPCTRL_IN0ACT_Pos 0
	(RTC_TAMPCTRL) Tamper Input 0 Action

#define	RTC_TAMPCTRL_IN0ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN0ACT_Pos)

#define	RTC_TAMPCTRL_IN0ACT(value) (RTC_TAMPCTRL_IN0ACT_Msk & ((value) << RTC_TAMPCTRL_IN0ACT_Pos))

#define	RTC_TAMPCTRL_IN0ACT_OFF_Val _U_(0x0)
	(RTC_TAMPCTRL) Off (Disabled)

#define	RTC_TAMPCTRL_IN0ACT_WAKE_Val _U_(0x1)
	(RTC_TAMPCTRL) Wake without timestamp

#define	RTC_TAMPCTRL_IN0ACT_CAPTURE_Val _U_(0x2)
	(RTC_TAMPCTRL) Capture timestamp

#define	RTC_TAMPCTRL_IN0ACT_ACTL_Val _U_(0x3)
	(RTC_TAMPCTRL) Compare IN0 to OUT

#define	RTC_TAMPCTRL_IN0ACT_OFF (RTC_TAMPCTRL_IN0ACT_OFF_Val << RTC_TAMPCTRL_IN0ACT_Pos)

#define	RTC_TAMPCTRL_IN0ACT_WAKE (RTC_TAMPCTRL_IN0ACT_WAKE_Val << RTC_TAMPCTRL_IN0ACT_Pos)

#define	RTC_TAMPCTRL_IN0ACT_CAPTURE (RTC_TAMPCTRL_IN0ACT_CAPTURE_Val << RTC_TAMPCTRL_IN0ACT_Pos)

#define	RTC_TAMPCTRL_IN0ACT_ACTL (RTC_TAMPCTRL_IN0ACT_ACTL_Val << RTC_TAMPCTRL_IN0ACT_Pos)

#define	RTC_TAMPCTRL_IN1ACT_Pos 2
	(RTC_TAMPCTRL) Tamper Input 1 Action

#define	RTC_TAMPCTRL_IN1ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN1ACT_Pos)

#define	RTC_TAMPCTRL_IN1ACT(value) (RTC_TAMPCTRL_IN1ACT_Msk & ((value) << RTC_TAMPCTRL_IN1ACT_Pos))

#define	RTC_TAMPCTRL_IN1ACT_OFF_Val _U_(0x0)
	(RTC_TAMPCTRL) Off (Disabled)

#define	RTC_TAMPCTRL_IN1ACT_WAKE_Val _U_(0x1)
	(RTC_TAMPCTRL) Wake without timestamp

#define	RTC_TAMPCTRL_IN1ACT_CAPTURE_Val _U_(0x2)
	(RTC_TAMPCTRL) Capture timestamp

#define	RTC_TAMPCTRL_IN1ACT_ACTL_Val _U_(0x3)
	(RTC_TAMPCTRL) Compare IN1 to OUT

#define	RTC_TAMPCTRL_IN1ACT_OFF (RTC_TAMPCTRL_IN1ACT_OFF_Val << RTC_TAMPCTRL_IN1ACT_Pos)

#define	RTC_TAMPCTRL_IN1ACT_WAKE (RTC_TAMPCTRL_IN1ACT_WAKE_Val << RTC_TAMPCTRL_IN1ACT_Pos)

#define	RTC_TAMPCTRL_IN1ACT_CAPTURE (RTC_TAMPCTRL_IN1ACT_CAPTURE_Val << RTC_TAMPCTRL_IN1ACT_Pos)

#define	RTC_TAMPCTRL_IN1ACT_ACTL (RTC_TAMPCTRL_IN1ACT_ACTL_Val << RTC_TAMPCTRL_IN1ACT_Pos)

#define	RTC_TAMPCTRL_IN2ACT_Pos 4
	(RTC_TAMPCTRL) Tamper Input 2 Action

#define	RTC_TAMPCTRL_IN2ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN2ACT_Pos)

#define	RTC_TAMPCTRL_IN2ACT(value) (RTC_TAMPCTRL_IN2ACT_Msk & ((value) << RTC_TAMPCTRL_IN2ACT_Pos))

#define	RTC_TAMPCTRL_IN2ACT_OFF_Val _U_(0x0)
	(RTC_TAMPCTRL) Off (Disabled)

#define	RTC_TAMPCTRL_IN2ACT_WAKE_Val _U_(0x1)
	(RTC_TAMPCTRL) Wake without timestamp

#define	RTC_TAMPCTRL_IN2ACT_CAPTURE_Val _U_(0x2)
	(RTC_TAMPCTRL) Capture timestamp

#define	RTC_TAMPCTRL_IN2ACT_ACTL_Val _U_(0x3)
	(RTC_TAMPCTRL) Compare IN2 to OUT

#define	RTC_TAMPCTRL_IN2ACT_OFF (RTC_TAMPCTRL_IN2ACT_OFF_Val << RTC_TAMPCTRL_IN2ACT_Pos)

#define	RTC_TAMPCTRL_IN2ACT_WAKE (RTC_TAMPCTRL_IN2ACT_WAKE_Val << RTC_TAMPCTRL_IN2ACT_Pos)

#define	RTC_TAMPCTRL_IN2ACT_CAPTURE (RTC_TAMPCTRL_IN2ACT_CAPTURE_Val << RTC_TAMPCTRL_IN2ACT_Pos)

#define	RTC_TAMPCTRL_IN2ACT_ACTL (RTC_TAMPCTRL_IN2ACT_ACTL_Val << RTC_TAMPCTRL_IN2ACT_Pos)

#define	RTC_TAMPCTRL_IN3ACT_Pos 6
	(RTC_TAMPCTRL) Tamper Input 3 Action

#define	RTC_TAMPCTRL_IN3ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN3ACT_Pos)

#define	RTC_TAMPCTRL_IN3ACT(value) (RTC_TAMPCTRL_IN3ACT_Msk & ((value) << RTC_TAMPCTRL_IN3ACT_Pos))

#define	RTC_TAMPCTRL_IN3ACT_OFF_Val _U_(0x0)
	(RTC_TAMPCTRL) Off (Disabled)

#define	RTC_TAMPCTRL_IN3ACT_WAKE_Val _U_(0x1)
	(RTC_TAMPCTRL) Wake without timestamp

#define	RTC_TAMPCTRL_IN3ACT_CAPTURE_Val _U_(0x2)
	(RTC_TAMPCTRL) Capture timestamp

#define	RTC_TAMPCTRL_IN3ACT_ACTL_Val _U_(0x3)
	(RTC_TAMPCTRL) Compare IN3 to OUT

#define	RTC_TAMPCTRL_IN3ACT_OFF (RTC_TAMPCTRL_IN3ACT_OFF_Val << RTC_TAMPCTRL_IN3ACT_Pos)

#define	RTC_TAMPCTRL_IN3ACT_WAKE (RTC_TAMPCTRL_IN3ACT_WAKE_Val << RTC_TAMPCTRL_IN3ACT_Pos)

#define	RTC_TAMPCTRL_IN3ACT_CAPTURE (RTC_TAMPCTRL_IN3ACT_CAPTURE_Val << RTC_TAMPCTRL_IN3ACT_Pos)

#define	RTC_TAMPCTRL_IN3ACT_ACTL (RTC_TAMPCTRL_IN3ACT_ACTL_Val << RTC_TAMPCTRL_IN3ACT_Pos)

#define	RTC_TAMPCTRL_IN4ACT_Pos 8
	(RTC_TAMPCTRL) Tamper Input 4 Action

#define	RTC_TAMPCTRL_IN4ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN4ACT_Pos)

#define	RTC_TAMPCTRL_IN4ACT(value) (RTC_TAMPCTRL_IN4ACT_Msk & ((value) << RTC_TAMPCTRL_IN4ACT_Pos))

#define	RTC_TAMPCTRL_IN4ACT_OFF_Val _U_(0x0)
	(RTC_TAMPCTRL) Off (Disabled)

#define	RTC_TAMPCTRL_IN4ACT_WAKE_Val _U_(0x1)
	(RTC_TAMPCTRL) Wake without timestamp

#define	RTC_TAMPCTRL_IN4ACT_CAPTURE_Val _U_(0x2)
	(RTC_TAMPCTRL) Capture timestamp

#define	RTC_TAMPCTRL_IN4ACT_ACTL_Val _U_(0x3)
	(RTC_TAMPCTRL) Compare IN4 to OUT

#define	RTC_TAMPCTRL_IN4ACT_OFF (RTC_TAMPCTRL_IN4ACT_OFF_Val << RTC_TAMPCTRL_IN4ACT_Pos)

#define	RTC_TAMPCTRL_IN4ACT_WAKE (RTC_TAMPCTRL_IN4ACT_WAKE_Val << RTC_TAMPCTRL_IN4ACT_Pos)

#define	RTC_TAMPCTRL_IN4ACT_CAPTURE (RTC_TAMPCTRL_IN4ACT_CAPTURE_Val << RTC_TAMPCTRL_IN4ACT_Pos)

#define	RTC_TAMPCTRL_IN4ACT_ACTL (RTC_TAMPCTRL_IN4ACT_ACTL_Val << RTC_TAMPCTRL_IN4ACT_Pos)

#define	RTC_TAMPCTRL_TAMLVL0_Pos 16
	(RTC_TAMPCTRL) Tamper Level Select 0

#define	RTC_TAMPCTRL_TAMLVL0 (_U_(1) << RTC_TAMPCTRL_TAMLVL0_Pos)

#define	RTC_TAMPCTRL_TAMLVL1_Pos 17
	(RTC_TAMPCTRL) Tamper Level Select 1

#define	RTC_TAMPCTRL_TAMLVL1 (_U_(1) << RTC_TAMPCTRL_TAMLVL1_Pos)

#define	RTC_TAMPCTRL_TAMLVL2_Pos 18
	(RTC_TAMPCTRL) Tamper Level Select 2

#define	RTC_TAMPCTRL_TAMLVL2 (_U_(1) << RTC_TAMPCTRL_TAMLVL2_Pos)

#define	RTC_TAMPCTRL_TAMLVL3_Pos 19
	(RTC_TAMPCTRL) Tamper Level Select 3

#define	RTC_TAMPCTRL_TAMLVL3 (_U_(1) << RTC_TAMPCTRL_TAMLVL3_Pos)

#define	RTC_TAMPCTRL_TAMLVL4_Pos 20
	(RTC_TAMPCTRL) Tamper Level Select 4

#define	RTC_TAMPCTRL_TAMLVL4 (_U_(1) << RTC_TAMPCTRL_TAMLVL4_Pos)

#define	RTC_TAMPCTRL_TAMLVL_Pos 16
	(RTC_TAMPCTRL) Tamper Level Select x

#define	RTC_TAMPCTRL_TAMLVL_Msk (_U_(0x1F) << RTC_TAMPCTRL_TAMLVL_Pos)

#define	RTC_TAMPCTRL_TAMLVL(value) (RTC_TAMPCTRL_TAMLVL_Msk & ((value) << RTC_TAMPCTRL_TAMLVL_Pos))

#define	RTC_TAMPCTRL_DEBNC0_Pos 24
	(RTC_TAMPCTRL) Debouncer Enable 0

#define	RTC_TAMPCTRL_DEBNC0 (_U_(1) << RTC_TAMPCTRL_DEBNC0_Pos)

#define	RTC_TAMPCTRL_DEBNC1_Pos 25
	(RTC_TAMPCTRL) Debouncer Enable 1

#define	RTC_TAMPCTRL_DEBNC1 (_U_(1) << RTC_TAMPCTRL_DEBNC1_Pos)

#define	RTC_TAMPCTRL_DEBNC2_Pos 26
	(RTC_TAMPCTRL) Debouncer Enable 2

#define	RTC_TAMPCTRL_DEBNC2 (_U_(1) << RTC_TAMPCTRL_DEBNC2_Pos)

#define	RTC_TAMPCTRL_DEBNC3_Pos 27
	(RTC_TAMPCTRL) Debouncer Enable 3

#define	RTC_TAMPCTRL_DEBNC3 (_U_(1) << RTC_TAMPCTRL_DEBNC3_Pos)

#define	RTC_TAMPCTRL_DEBNC4_Pos 28
	(RTC_TAMPCTRL) Debouncer Enable 4

#define	RTC_TAMPCTRL_DEBNC4 (_U_(1) << RTC_TAMPCTRL_DEBNC4_Pos)

#define	RTC_TAMPCTRL_DEBNC_Pos 24
	(RTC_TAMPCTRL) Debouncer Enable x

#define	RTC_TAMPCTRL_DEBNC_Msk (_U_(0x1F) << RTC_TAMPCTRL_DEBNC_Pos)

#define	RTC_TAMPCTRL_DEBNC(value) (RTC_TAMPCTRL_DEBNC_Msk & ((value) << RTC_TAMPCTRL_DEBNC_Pos))

#define	RTC_TAMPCTRL_MASK _U_(0x1F1F03FF)
	(RTC_TAMPCTRL) MASK Register

#define	RTC_MODE0_TIMESTAMP_OFFSET 0x64
	(RTC_MODE0_TIMESTAMP offset) MODE0 Timestamp

#define	RTC_MODE0_TIMESTAMP_RESETVALUE _U_(0x00000000)
	(RTC_MODE0_TIMESTAMP reset_value) MODE0 Timestamp

#define	RTC_MODE0_TIMESTAMP_COUNT_Pos 0
	(RTC_MODE0_TIMESTAMP) Count Timestamp Value

#define	RTC_MODE0_TIMESTAMP_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_TIMESTAMP_COUNT_Pos)

#define	RTC_MODE0_TIMESTAMP_COUNT(value) (RTC_MODE0_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE0_TIMESTAMP_COUNT_Pos))

#define	RTC_MODE0_TIMESTAMP_MASK _U_(0xFFFFFFFF)
	(RTC_MODE0_TIMESTAMP) MASK Register

#define	RTC_MODE1_TIMESTAMP_OFFSET 0x64
	(RTC_MODE1_TIMESTAMP offset) MODE1 Timestamp

#define	RTC_MODE1_TIMESTAMP_RESETVALUE _U_(0x00000000)
	(RTC_MODE1_TIMESTAMP reset_value) MODE1 Timestamp

#define	RTC_MODE1_TIMESTAMP_COUNT_Pos 0
	(RTC_MODE1_TIMESTAMP) Count Timestamp Value

#define	RTC_MODE1_TIMESTAMP_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_TIMESTAMP_COUNT_Pos)

#define	RTC_MODE1_TIMESTAMP_COUNT(value) (RTC_MODE1_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE1_TIMESTAMP_COUNT_Pos))

#define	RTC_MODE1_TIMESTAMP_MASK _U_(0x0000FFFF)
	(RTC_MODE1_TIMESTAMP) MASK Register

#define	RTC_MODE2_TIMESTAMP_OFFSET 0x64
	(RTC_MODE2_TIMESTAMP offset) MODE2 Timestamp

#define	RTC_MODE2_TIMESTAMP_RESETVALUE _U_(0x00000000)
	(RTC_MODE2_TIMESTAMP reset_value) MODE2 Timestamp

#define	RTC_MODE2_TIMESTAMP_SECOND_Pos 0
	(RTC_MODE2_TIMESTAMP) Second Timestamp Value

#define	RTC_MODE2_TIMESTAMP_SECOND_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_SECOND_Pos)

#define	RTC_MODE2_TIMESTAMP_SECOND(value) (RTC_MODE2_TIMESTAMP_SECOND_Msk & ((value) << RTC_MODE2_TIMESTAMP_SECOND_Pos))

#define	RTC_MODE2_TIMESTAMP_MINUTE_Pos 6
	(RTC_MODE2_TIMESTAMP) Minute Timestamp Value

#define	RTC_MODE2_TIMESTAMP_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_MINUTE_Pos)

#define	RTC_MODE2_TIMESTAMP_MINUTE(value) (RTC_MODE2_TIMESTAMP_MINUTE_Msk & ((value) << RTC_MODE2_TIMESTAMP_MINUTE_Pos))

#define	RTC_MODE2_TIMESTAMP_HOUR_Pos 12
	(RTC_MODE2_TIMESTAMP) Hour Timestamp Value

#define	RTC_MODE2_TIMESTAMP_HOUR_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_HOUR_Pos)

#define	RTC_MODE2_TIMESTAMP_HOUR(value) (RTC_MODE2_TIMESTAMP_HOUR_Msk & ((value) << RTC_MODE2_TIMESTAMP_HOUR_Pos))

#define	RTC_MODE2_TIMESTAMP_HOUR_AM_Val _U_(0x0)
	(RTC_MODE2_TIMESTAMP) AM when CLKREP in 12-hour

#define	RTC_MODE2_TIMESTAMP_HOUR_PM_Val _U_(0x10)
	(RTC_MODE2_TIMESTAMP) PM when CLKREP in 12-hour

#define	RTC_MODE2_TIMESTAMP_HOUR_AM (RTC_MODE2_TIMESTAMP_HOUR_AM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)

#define	RTC_MODE2_TIMESTAMP_HOUR_PM (RTC_MODE2_TIMESTAMP_HOUR_PM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)

#define	RTC_MODE2_TIMESTAMP_DAY_Pos 17
	(RTC_MODE2_TIMESTAMP) Day Timestamp Value

#define	RTC_MODE2_TIMESTAMP_DAY_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_DAY_Pos)

#define	RTC_MODE2_TIMESTAMP_DAY(value) (RTC_MODE2_TIMESTAMP_DAY_Msk & ((value) << RTC_MODE2_TIMESTAMP_DAY_Pos))

#define	RTC_MODE2_TIMESTAMP_MONTH_Pos 22
	(RTC_MODE2_TIMESTAMP) Month Timestamp Value

#define	RTC_MODE2_TIMESTAMP_MONTH_Msk (_U_(0xF) << RTC_MODE2_TIMESTAMP_MONTH_Pos)

#define	RTC_MODE2_TIMESTAMP_MONTH(value) (RTC_MODE2_TIMESTAMP_MONTH_Msk & ((value) << RTC_MODE2_TIMESTAMP_MONTH_Pos))

#define	RTC_MODE2_TIMESTAMP_YEAR_Pos 26
	(RTC_MODE2_TIMESTAMP) Year Timestamp Value

#define	RTC_MODE2_TIMESTAMP_YEAR_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_YEAR_Pos)

#define	RTC_MODE2_TIMESTAMP_YEAR(value) (RTC_MODE2_TIMESTAMP_YEAR_Msk & ((value) << RTC_MODE2_TIMESTAMP_YEAR_Pos))

#define	RTC_MODE2_TIMESTAMP_MASK _U_(0xFFFFFFFF)
	(RTC_MODE2_TIMESTAMP) MASK Register

#define	RTC_TAMPID_OFFSET 0x68
	(RTC_TAMPID offset) Tamper ID

#define	RTC_TAMPID_RESETVALUE _U_(0x00000000)
	(RTC_TAMPID reset_value) Tamper ID

#define	RTC_TAMPID_TAMPID0_Pos 0
	(RTC_TAMPID) Tamper Input 0 Detected

#define	RTC_TAMPID_TAMPID0 (_U_(1) << RTC_TAMPID_TAMPID0_Pos)

#define	RTC_TAMPID_TAMPID1_Pos 1
	(RTC_TAMPID) Tamper Input 1 Detected

#define	RTC_TAMPID_TAMPID1 (_U_(1) << RTC_TAMPID_TAMPID1_Pos)

#define	RTC_TAMPID_TAMPID2_Pos 2
	(RTC_TAMPID) Tamper Input 2 Detected

#define	RTC_TAMPID_TAMPID2 (_U_(1) << RTC_TAMPID_TAMPID2_Pos)

#define	RTC_TAMPID_TAMPID3_Pos 3
	(RTC_TAMPID) Tamper Input 3 Detected

#define	RTC_TAMPID_TAMPID3 (_U_(1) << RTC_TAMPID_TAMPID3_Pos)

#define	RTC_TAMPID_TAMPID4_Pos 4
	(RTC_TAMPID) Tamper Input 4 Detected

#define	RTC_TAMPID_TAMPID4 (_U_(1) << RTC_TAMPID_TAMPID4_Pos)

#define	RTC_TAMPID_TAMPID_Pos 0
	(RTC_TAMPID) Tamper Input x Detected

#define	RTC_TAMPID_TAMPID_Msk (_U_(0x1F) << RTC_TAMPID_TAMPID_Pos)

#define	RTC_TAMPID_TAMPID(value) (RTC_TAMPID_TAMPID_Msk & ((value) << RTC_TAMPID_TAMPID_Pos))

#define	RTC_TAMPID_TAMPEVT_Pos 31
	(RTC_TAMPID) Tamper Event Detected

#define	RTC_TAMPID_TAMPEVT (_U_(0x1) << RTC_TAMPID_TAMPEVT_Pos)

#define	RTC_TAMPID_MASK _U_(0x8000001F)
	(RTC_TAMPID) MASK Register

#define	RTC_BKUP_OFFSET 0x80
	(RTC_BKUP offset) Backup

#define	RTC_BKUP_RESETVALUE _U_(0x00000000)
	(RTC_BKUP reset_value) Backup

#define	RTC_BKUP_BKUP_Pos 0
	(RTC_BKUP) Backup

#define	RTC_BKUP_BKUP_Msk (_U_(0xFFFFFFFF) << RTC_BKUP_BKUP_Pos)

#define	RTC_BKUP_BKUP(value) (RTC_BKUP_BKUP_Msk & ((value) << RTC_BKUP_BKUP_Pos))

#define	RTC_BKUP_MASK _U_(0xFFFFFFFF)
	(RTC_BKUP) MASK Register

Detailed Description

Component description for RTC.

\asf_license_start

Definition in file rtc.h.

Data Structures

Macros

Detailed Description