SAME54P20A Test Project
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Component description for FREQM. More...
Go to the source code of this file.
Data Structures | |
union | FREQM_CTRLA_Type |
union | FREQM_CTRLB_Type |
union | FREQM_CFGA_Type |
union | FREQM_INTENCLR_Type |
union | FREQM_INTENSET_Type |
union | FREQM_INTFLAG_Type |
union | FREQM_STATUS_Type |
union | FREQM_SYNCBUSY_Type |
union | FREQM_VALUE_Type |
struct | Freqm |
FREQM hardware registers. More... | |
Macros | |
#define | FREQM_U2257 |
#define | REV_FREQM 0x110 |
#define | FREQM_CTRLA_OFFSET 0x00 |
(FREQM_CTRLA offset) Control A Register | |
#define | FREQM_CTRLA_RESETVALUE _U_(0x00) |
(FREQM_CTRLA reset_value) Control A Register | |
#define | FREQM_CTRLA_SWRST_Pos 0 |
(FREQM_CTRLA) Software Reset | |
#define | FREQM_CTRLA_SWRST (_U_(0x1) << FREQM_CTRLA_SWRST_Pos) |
#define | FREQM_CTRLA_ENABLE_Pos 1 |
(FREQM_CTRLA) Enable | |
#define | FREQM_CTRLA_ENABLE (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos) |
#define | FREQM_CTRLA_MASK _U_(0x03) |
(FREQM_CTRLA) MASK Register | |
#define | FREQM_CTRLB_OFFSET 0x01 |
(FREQM_CTRLB offset) Control B Register | |
#define | FREQM_CTRLB_RESETVALUE _U_(0x00) |
(FREQM_CTRLB reset_value) Control B Register | |
#define | FREQM_CTRLB_START_Pos 0 |
(FREQM_CTRLB) Start Measurement | |
#define | FREQM_CTRLB_START (_U_(0x1) << FREQM_CTRLB_START_Pos) |
#define | FREQM_CTRLB_MASK _U_(0x01) |
(FREQM_CTRLB) MASK Register | |
#define | FREQM_CFGA_OFFSET 0x02 |
(FREQM_CFGA offset) Config A register | |
#define | FREQM_CFGA_RESETVALUE _U_(0x0000) |
(FREQM_CFGA reset_value) Config A register | |
#define | FREQM_CFGA_REFNUM_Pos 0 |
(FREQM_CFGA) Number of Reference Clock Cycles | |
#define | FREQM_CFGA_REFNUM_Msk (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos) |
#define | FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos)) |
#define | FREQM_CFGA_MASK _U_(0x00FF) |
(FREQM_CFGA) MASK Register | |
#define | FREQM_INTENCLR_OFFSET 0x08 |
(FREQM_INTENCLR offset) Interrupt Enable Clear Register | |
#define | FREQM_INTENCLR_RESETVALUE _U_(0x00) |
(FREQM_INTENCLR reset_value) Interrupt Enable Clear Register | |
#define | FREQM_INTENCLR_DONE_Pos 0 |
(FREQM_INTENCLR) Measurement Done Interrupt Enable | |
#define | FREQM_INTENCLR_DONE (_U_(0x1) << FREQM_INTENCLR_DONE_Pos) |
#define | FREQM_INTENCLR_MASK _U_(0x01) |
(FREQM_INTENCLR) MASK Register | |
#define | FREQM_INTENSET_OFFSET 0x09 |
(FREQM_INTENSET offset) Interrupt Enable Set Register | |
#define | FREQM_INTENSET_RESETVALUE _U_(0x00) |
(FREQM_INTENSET reset_value) Interrupt Enable Set Register | |
#define | FREQM_INTENSET_DONE_Pos 0 |
(FREQM_INTENSET) Measurement Done Interrupt Enable | |
#define | FREQM_INTENSET_DONE (_U_(0x1) << FREQM_INTENSET_DONE_Pos) |
#define | FREQM_INTENSET_MASK _U_(0x01) |
(FREQM_INTENSET) MASK Register | |
#define | FREQM_INTFLAG_OFFSET 0x0A |
(FREQM_INTFLAG offset) Interrupt Flag Register | |
#define | FREQM_INTFLAG_RESETVALUE _U_(0x00) |
(FREQM_INTFLAG reset_value) Interrupt Flag Register | |
#define | FREQM_INTFLAG_DONE_Pos 0 |
(FREQM_INTFLAG) Measurement Done | |
#define | FREQM_INTFLAG_DONE (_U_(0x1) << FREQM_INTFLAG_DONE_Pos) |
#define | FREQM_INTFLAG_MASK _U_(0x01) |
(FREQM_INTFLAG) MASK Register | |
#define | FREQM_STATUS_OFFSET 0x0B |
(FREQM_STATUS offset) Status Register | |
#define | FREQM_STATUS_RESETVALUE _U_(0x00) |
(FREQM_STATUS reset_value) Status Register | |
#define | FREQM_STATUS_BUSY_Pos 0 |
(FREQM_STATUS) FREQM Status | |
#define | FREQM_STATUS_BUSY (_U_(0x1) << FREQM_STATUS_BUSY_Pos) |
#define | FREQM_STATUS_OVF_Pos 1 |
(FREQM_STATUS) Sticky Count Value Overflow | |
#define | FREQM_STATUS_OVF (_U_(0x1) << FREQM_STATUS_OVF_Pos) |
#define | FREQM_STATUS_MASK _U_(0x03) |
(FREQM_STATUS) MASK Register | |
#define | FREQM_SYNCBUSY_OFFSET 0x0C |
(FREQM_SYNCBUSY offset) Synchronization Busy Register | |
#define | FREQM_SYNCBUSY_RESETVALUE _U_(0x00000000) |
(FREQM_SYNCBUSY reset_value) Synchronization Busy Register | |
#define | FREQM_SYNCBUSY_SWRST_Pos 0 |
(FREQM_SYNCBUSY) Software Reset | |
#define | FREQM_SYNCBUSY_SWRST (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos) |
#define | FREQM_SYNCBUSY_ENABLE_Pos 1 |
(FREQM_SYNCBUSY) Enable | |
#define | FREQM_SYNCBUSY_ENABLE (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos) |
#define | FREQM_SYNCBUSY_MASK _U_(0x00000003) |
(FREQM_SYNCBUSY) MASK Register | |
#define | FREQM_VALUE_OFFSET 0x10 |
(FREQM_VALUE offset) Count Value Register | |
#define | FREQM_VALUE_RESETVALUE _U_(0x00000000) |
(FREQM_VALUE reset_value) Count Value Register | |
#define | FREQM_VALUE_VALUE_Pos 0 |
(FREQM_VALUE) Measurement Value | |
#define | FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos) |
#define | FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos)) |
#define | FREQM_VALUE_MASK _U_(0x00FFFFFF) |
(FREQM_VALUE) MASK Register | |
Component description for FREQM.
Copyright (c) 2019 Microchip Technology Inc.
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Definition in file freqm.h.