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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">TcCount32 Struct Reference</div> </div>
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<p>TC_COUNT32 hardware registers.
<a href="structTcCount32.html#details">More...</a></p>
<p><code>#include <<a class="el" href="tc_8h_source.html">tc.h</a>></code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a61a55f6a4d2840eca59afee25ca7b410"><td class="memItemLeft" align="right" valign="top"><a id="a61a55f6a4d2840eca59afee25ca7b410"></a>
__IO <a class="el" href="unionTC__CTRLA__Type.html">TC_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#a61a55f6a4d2840eca59afee25ca7b410">CTRLA</a></td></tr>
<tr class="memdesc:a61a55f6a4d2840eca59afee25ca7b410"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 32) Control A. <br /></td></tr>
<tr class="separator:a61a55f6a4d2840eca59afee25ca7b410"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a757bc243ef27207e5a2f2a6ba46829ff"><td class="memItemLeft" align="right" valign="top"><a id="a757bc243ef27207e5a2f2a6ba46829ff"></a>
__IO <a class="el" href="unionTC__CTRLBCLR__Type.html">TC_CTRLBCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#a757bc243ef27207e5a2f2a6ba46829ff">CTRLBCLR</a></td></tr>
<tr class="memdesc:a757bc243ef27207e5a2f2a6ba46829ff"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 8) Control B Clear. <br /></td></tr>
<tr class="separator:a757bc243ef27207e5a2f2a6ba46829ff"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af95274ac7cdedd0ba52b925fbf8c0a89"><td class="memItemLeft" align="right" valign="top"><a id="af95274ac7cdedd0ba52b925fbf8c0a89"></a>
__IO <a class="el" href="unionTC__CTRLBSET__Type.html">TC_CTRLBSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#af95274ac7cdedd0ba52b925fbf8c0a89">CTRLBSET</a></td></tr>
<tr class="memdesc:af95274ac7cdedd0ba52b925fbf8c0a89"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x05 (R/W 8) Control B Set. <br /></td></tr>
<tr class="separator:af95274ac7cdedd0ba52b925fbf8c0a89"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0d8f9972396d794945edc76c89944d88"><td class="memItemLeft" align="right" valign="top"><a id="a0d8f9972396d794945edc76c89944d88"></a>
__IO <a class="el" href="unionTC__EVCTRL__Type.html">TC_EVCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#a0d8f9972396d794945edc76c89944d88">EVCTRL</a></td></tr>
<tr class="memdesc:a0d8f9972396d794945edc76c89944d88"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x06 (R/W 16) Event Control. <br /></td></tr>
<tr class="separator:a0d8f9972396d794945edc76c89944d88"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a560faa7e8989670e03c078573074fced"><td class="memItemLeft" align="right" valign="top"><a id="a560faa7e8989670e03c078573074fced"></a>
__IO <a class="el" href="unionTC__INTENCLR__Type.html">TC_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#a560faa7e8989670e03c078573074fced">INTENCLR</a></td></tr>
<tr class="memdesc:a560faa7e8989670e03c078573074fced"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 8) Interrupt Enable Clear. <br /></td></tr>
<tr class="separator:a560faa7e8989670e03c078573074fced"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4ae24c9eb71be0ae92a249947757ac08"><td class="memItemLeft" align="right" valign="top"><a id="a4ae24c9eb71be0ae92a249947757ac08"></a>
__IO <a class="el" href="unionTC__INTENSET__Type.html">TC_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#a4ae24c9eb71be0ae92a249947757ac08">INTENSET</a></td></tr>
<tr class="memdesc:a4ae24c9eb71be0ae92a249947757ac08"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x09 (R/W 8) Interrupt Enable Set. <br /></td></tr>
<tr class="separator:a4ae24c9eb71be0ae92a249947757ac08"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a99b72f5ad94076184f44f42cfebe49bf"><td class="memItemLeft" align="right" valign="top"><a id="a99b72f5ad94076184f44f42cfebe49bf"></a>
__IO <a class="el" href="unionTC__INTFLAG__Type.html">TC_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#a99b72f5ad94076184f44f42cfebe49bf">INTFLAG</a></td></tr>
<tr class="memdesc:a99b72f5ad94076184f44f42cfebe49bf"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear. <br /></td></tr>
<tr class="separator:a99b72f5ad94076184f44f42cfebe49bf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af2b3c39212572d028392e6557f3af1af"><td class="memItemLeft" align="right" valign="top"><a id="af2b3c39212572d028392e6557f3af1af"></a>
__IO <a class="el" href="unionTC__STATUS__Type.html">TC_STATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#af2b3c39212572d028392e6557f3af1af">STATUS</a></td></tr>
<tr class="memdesc:af2b3c39212572d028392e6557f3af1af"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0B (R/W 8) Status. <br /></td></tr>
<tr class="separator:af2b3c39212572d028392e6557f3af1af"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a77ae55a0715bbc421cc5731a7d8d9477"><td class="memItemLeft" align="right" valign="top"><a id="a77ae55a0715bbc421cc5731a7d8d9477"></a>
__IO <a class="el" href="unionTC__WAVE__Type.html">TC_WAVE_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#a77ae55a0715bbc421cc5731a7d8d9477">WAVE</a></td></tr>
<tr class="memdesc:a77ae55a0715bbc421cc5731a7d8d9477"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 8) Waveform Generation Control. <br /></td></tr>
<tr class="separator:a77ae55a0715bbc421cc5731a7d8d9477"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aea000a0340fae9958f9098fab1958047"><td class="memItemLeft" align="right" valign="top"><a id="aea000a0340fae9958f9098fab1958047"></a>
__IO <a class="el" href="unionTC__DRVCTRL__Type.html">TC_DRVCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#aea000a0340fae9958f9098fab1958047">DRVCTRL</a></td></tr>
<tr class="memdesc:aea000a0340fae9958f9098fab1958047"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0D (R/W 8) Control C. <br /></td></tr>
<tr class="separator:aea000a0340fae9958f9098fab1958047"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a594bf4ded7c4540cb0be1bc1885ebbf3"><td class="memItemLeft" align="right" valign="top"><a id="a594bf4ded7c4540cb0be1bc1885ebbf3"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x1]</td></tr>
<tr class="separator:a594bf4ded7c4540cb0be1bc1885ebbf3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a17dbd050d2660f89e828bcedced91dea"><td class="memItemLeft" align="right" valign="top"><a id="a17dbd050d2660f89e828bcedced91dea"></a>
__IO <a class="el" href="unionTC__DBGCTRL__Type.html">TC_DBGCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#a17dbd050d2660f89e828bcedced91dea">DBGCTRL</a></td></tr>
<tr class="memdesc:a17dbd050d2660f89e828bcedced91dea"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0F (R/W 8) Debug Control. <br /></td></tr>
<tr class="separator:a17dbd050d2660f89e828bcedced91dea"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a98942d0eeb6ecdee75ab47cf36dfedda"><td class="memItemLeft" align="right" valign="top"><a id="a98942d0eeb6ecdee75ab47cf36dfedda"></a>
__I <a class="el" href="unionTC__SYNCBUSY__Type.html">TC_SYNCBUSY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#a98942d0eeb6ecdee75ab47cf36dfedda">SYNCBUSY</a></td></tr>
<tr class="memdesc:a98942d0eeb6ecdee75ab47cf36dfedda"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/ 32) Synchronization Status. <br /></td></tr>
<tr class="separator:a98942d0eeb6ecdee75ab47cf36dfedda"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a03065901d7c4f3effcf6b4d3e24bb1ea"><td class="memItemLeft" align="right" valign="top"><a id="a03065901d7c4f3effcf6b4d3e24bb1ea"></a>
__IO <a class="el" href="unionTC__COUNT32__COUNT__Type.html">TC_COUNT32_COUNT_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#a03065901d7c4f3effcf6b4d3e24bb1ea">COUNT</a></td></tr>
<tr class="memdesc:a03065901d7c4f3effcf6b4d3e24bb1ea"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 32) COUNT32 Count. <br /></td></tr>
<tr class="separator:a03065901d7c4f3effcf6b4d3e24bb1ea"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5df72d81eb8db05be611ee9237c14f2c"><td class="memItemLeft" align="right" valign="top"><a id="a5df72d81eb8db05be611ee9237c14f2c"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x4]</td></tr>
<tr class="separator:a5df72d81eb8db05be611ee9237c14f2c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a92ca2067ad99a0ee2727cc44353e3b2e"><td class="memItemLeft" align="right" valign="top"><a id="a92ca2067ad99a0ee2727cc44353e3b2e"></a>
__IO <a class="el" href="unionTC__COUNT32__CC__Type.html">TC_COUNT32_CC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#a92ca2067ad99a0ee2727cc44353e3b2e">CC</a> [2]</td></tr>
<tr class="memdesc:a92ca2067ad99a0ee2727cc44353e3b2e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1C (R/W 32) COUNT32 Compare and Capture. <br /></td></tr>
<tr class="separator:a92ca2067ad99a0ee2727cc44353e3b2e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad5da299871ed88083a1cdce87447d490"><td class="memItemLeft" align="right" valign="top"><a id="ad5da299871ed88083a1cdce87447d490"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0xC]</td></tr>
<tr class="separator:ad5da299871ed88083a1cdce87447d490"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab7595232389bedb3261380eafffc3bda"><td class="memItemLeft" align="right" valign="top"><a id="ab7595232389bedb3261380eafffc3bda"></a>
__IO <a class="el" href="unionTC__COUNT32__CCBUF__Type.html">TC_COUNT32_CCBUF_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount32.html#ab7595232389bedb3261380eafffc3bda">CCBUF</a> [2]</td></tr>
<tr class="memdesc:ab7595232389bedb3261380eafffc3bda"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer. <br /></td></tr>
<tr class="separator:ab7595232389bedb3261380eafffc3bda"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>TC_COUNT32 hardware registers. </p>
<p class="definition">Definition at line <a class="el" href="tc_8h_source.html#l00819">819</a> of file <a class="el" href="tc_8h_source.html">tc.h</a>.</p>
</div><hr/>The documentation for this struct was generated from the following file:<ul>
<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="tc_8h_source.html">tc.h</a></li>
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