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SAME54P20A Test Project
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DmacChannel hardware registers. More...
#include <dmac.h>
Data Fields | |
| __IO DMAC_CHCTRLA_Type | CHCTRLA |
| Offset: 0x00 (R/W 32) Channel n Control A. | |
| __IO DMAC_CHCTRLB_Type | CHCTRLB |
| Offset: 0x04 (R/W 8) Channel n Control B. | |
| __IO DMAC_CHPRILVL_Type | CHPRILVL |
| Offset: 0x05 (R/W 8) Channel n Priority Level. | |
| __IO DMAC_CHEVCTRL_Type | CHEVCTRL |
| Offset: 0x06 (R/W 8) Channel n Event Control. | |
| RoReg8 | Reserved1 [0x5] |
| __IO DMAC_CHINTENCLR_Type | CHINTENCLR |
| Offset: 0x0C (R/W 8) Channel n Interrupt Enable Clear. | |
| __IO DMAC_CHINTENSET_Type | CHINTENSET |
| Offset: 0x0D (R/W 8) Channel n Interrupt Enable Set. | |
| __IO DMAC_CHINTFLAG_Type | CHINTFLAG |
| Offset: 0x0E (R/W 8) Channel n Interrupt Flag Status and Clear. | |
| __IO DMAC_CHSTATUS_Type | CHSTATUS |
| Offset: 0x0F (R/W 8) Channel n Status. | |
DmacChannel hardware registers.
1.8.20