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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Ramecc Struct Reference</div> </div>
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<p>RAMECC hardware registers.
<a href="structRamecc.html#details">More...</a></p>
<p><code>#include <<a class="el" href="component_2ramecc_8h_source.html">ramecc.h</a>></code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a0ab08cb00c7dbb1928723621a5c2e98b"><td class="memItemLeft" align="right" valign="top"><a id="a0ab08cb00c7dbb1928723621a5c2e98b"></a>
__IO <a class="el" href="unionRAMECC__INTENCLR__Type.html">RAMECC_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structRamecc.html#a0ab08cb00c7dbb1928723621a5c2e98b">INTENCLR</a></td></tr>
<tr class="memdesc:a0ab08cb00c7dbb1928723621a5c2e98b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0 (R/W 8) Interrupt Enable Clear. <br /></td></tr>
<tr class="separator:a0ab08cb00c7dbb1928723621a5c2e98b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac8dad5ebd0322b3dea84ab8838109e3a"><td class="memItemLeft" align="right" valign="top"><a id="ac8dad5ebd0322b3dea84ab8838109e3a"></a>
__IO <a class="el" href="unionRAMECC__INTENSET__Type.html">RAMECC_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structRamecc.html#ac8dad5ebd0322b3dea84ab8838109e3a">INTENSET</a></td></tr>
<tr class="memdesc:ac8dad5ebd0322b3dea84ab8838109e3a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1 (R/W 8) Interrupt Enable Set. <br /></td></tr>
<tr class="separator:ac8dad5ebd0322b3dea84ab8838109e3a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa8b70758e67cb15f134ef1a0ae8a3513"><td class="memItemLeft" align="right" valign="top"><a id="aa8b70758e67cb15f134ef1a0ae8a3513"></a>
__IO <a class="el" href="unionRAMECC__INTFLAG__Type.html">RAMECC_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structRamecc.html#aa8b70758e67cb15f134ef1a0ae8a3513">INTFLAG</a></td></tr>
<tr class="memdesc:aa8b70758e67cb15f134ef1a0ae8a3513"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x2 (R/W 8) Interrupt Flag. <br /></td></tr>
<tr class="separator:aa8b70758e67cb15f134ef1a0ae8a3513"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af5cf55200d059eff323c18a8d8636332"><td class="memItemLeft" align="right" valign="top"><a id="af5cf55200d059eff323c18a8d8636332"></a>
__I <a class="el" href="unionRAMECC__STATUS__Type.html">RAMECC_STATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structRamecc.html#af5cf55200d059eff323c18a8d8636332">STATUS</a></td></tr>
<tr class="memdesc:af5cf55200d059eff323c18a8d8636332"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x3 (R/ 8) Status. <br /></td></tr>
<tr class="separator:af5cf55200d059eff323c18a8d8636332"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae8ee769b2af7eb4f37263a301cd8e53b"><td class="memItemLeft" align="right" valign="top"><a id="ae8ee769b2af7eb4f37263a301cd8e53b"></a>
__I <a class="el" href="unionRAMECC__ERRADDR__Type.html">RAMECC_ERRADDR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structRamecc.html#ae8ee769b2af7eb4f37263a301cd8e53b">ERRADDR</a></td></tr>
<tr class="memdesc:ae8ee769b2af7eb4f37263a301cd8e53b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x4 (R/ 32) Error Address. <br /></td></tr>
<tr class="separator:ae8ee769b2af7eb4f37263a301cd8e53b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad19f17e853707f4fe4ef97bdb548076b"><td class="memItemLeft" align="right" valign="top"><a id="ad19f17e853707f4fe4ef97bdb548076b"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x7]</td></tr>
<tr class="separator:ad19f17e853707f4fe4ef97bdb548076b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac8796cbdb0b3d610174ba0e025a9fb56"><td class="memItemLeft" align="right" valign="top"><a id="ac8796cbdb0b3d610174ba0e025a9fb56"></a>
__IO <a class="el" href="unionRAMECC__DBGCTRL__Type.html">RAMECC_DBGCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structRamecc.html#ac8796cbdb0b3d610174ba0e025a9fb56">DBGCTRL</a></td></tr>
<tr class="memdesc:ac8796cbdb0b3d610174ba0e025a9fb56"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xF (R/W 8) Debug Control. <br /></td></tr>
<tr class="separator:ac8796cbdb0b3d610174ba0e025a9fb56"><td class="memSeparator" colspan="2"> </td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>RAMECC hardware registers. </p>
<p class="definition">Definition at line <a class="el" href="component_2ramecc_8h_source.html#l00165">165</a> of file <a class="el" href="component_2ramecc_8h_source.html">ramecc.h</a>.</p>
</div><hr/>The documentation for this struct was generated from the following file:<ul>
<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2ramecc_8h_source.html">ramecc.h</a></li>
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