SAME54P20A Test Project
|
Instance description for RAMECC. More...
Go to the source code of this file.
Macros | |
#define | REG_RAMECC_INTENCLR (*(RwReg8 *)0x41020000UL) |
(RAMECC) Interrupt Enable Clear | |
#define | REG_RAMECC_INTENSET (*(RwReg8 *)0x41020001UL) |
(RAMECC) Interrupt Enable Set | |
#define | REG_RAMECC_INTFLAG (*(RwReg8 *)0x41020002UL) |
(RAMECC) Interrupt Flag | |
#define | REG_RAMECC_STATUS (*(RoReg8 *)0x41020003UL) |
(RAMECC) Status | |
#define | REG_RAMECC_ERRADDR (*(RoReg *)0x41020004UL) |
(RAMECC) Error Address | |
#define | REG_RAMECC_DBGCTRL (*(RwReg8 *)0x4102000FUL) |
(RAMECC) Debug Control | |
#define | RAMECC_RAMADDR_BITS 13 |
#define | RAMECC_RAMBANK_NUM 4 |
Instance description for RAMECC.
Copyright (c) 2019 Microchip Technology Inc.
\asf_license_start
Definition in file ramecc.h.