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SAME54P20A Test Project
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SERCOM_I2CM hardware registers. More...
#include <sercom.h>
Data Fields | |
| __IO SERCOM_I2CM_CTRLA_Type | CTRLA |
| Offset: 0x00 (R/W 32) I2CM Control A. | |
| __IO SERCOM_I2CM_CTRLB_Type | CTRLB |
| Offset: 0x04 (R/W 32) I2CM Control B. | |
| __IO SERCOM_I2CM_CTRLC_Type | CTRLC |
| Offset: 0x08 (R/W 32) I2CM Control C. | |
| __IO SERCOM_I2CM_BAUD_Type | BAUD |
| Offset: 0x0C (R/W 32) I2CM Baud Rate. | |
| RoReg8 | Reserved1 [0x4] |
| __IO SERCOM_I2CM_INTENCLR_Type | INTENCLR |
| Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear. | |
| RoReg8 | Reserved2 [0x1] |
| __IO SERCOM_I2CM_INTENSET_Type | INTENSET |
| Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set. | |
| RoReg8 | Reserved3 [0x1] |
| __IO SERCOM_I2CM_INTFLAG_Type | INTFLAG |
| Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear. | |
| RoReg8 | Reserved4 [0x1] |
| __IO SERCOM_I2CM_STATUS_Type | STATUS |
| Offset: 0x1A (R/W 16) I2CM Status. | |
| __I SERCOM_I2CM_SYNCBUSY_Type | SYNCBUSY |
| Offset: 0x1C (R/ 32) I2CM Synchronization Busy. | |
| RoReg8 | Reserved5 [0x4] |
| __IO SERCOM_I2CM_ADDR_Type | ADDR |
| Offset: 0x24 (R/W 32) I2CM Address. | |
| __IO SERCOM_I2CM_DATA_Type | DATA |
| Offset: 0x28 (R/W 32) I2CM Data. | |
| RoReg8 | Reserved6 [0x4] |
| __IO SERCOM_I2CM_DBGCTRL_Type | DBGCTRL |
| Offset: 0x30 (R/W 8) I2CM Debug Control. | |
1.8.20