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SAME54P20A Test Project
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RTC_MODE1 hardware registers. More...
#include <rtc.h>
Data Fields | |
| __IO RTC_MODE1_CTRLA_Type | CTRLA |
| Offset: 0x00 (R/W 16) MODE1 Control A. | |
| __IO RTC_MODE1_CTRLB_Type | CTRLB |
| Offset: 0x02 (R/W 16) MODE1 Control B. | |
| __IO RTC_MODE1_EVCTRL_Type | EVCTRL |
| Offset: 0x04 (R/W 32) MODE1 Event Control. | |
| __IO RTC_MODE1_INTENCLR_Type | INTENCLR |
| Offset: 0x08 (R/W 16) MODE1 Interrupt Enable Clear. | |
| __IO RTC_MODE1_INTENSET_Type | INTENSET |
| Offset: 0x0A (R/W 16) MODE1 Interrupt Enable Set. | |
| __IO RTC_MODE1_INTFLAG_Type | INTFLAG |
| Offset: 0x0C (R/W 16) MODE1 Interrupt Flag Status and Clear. | |
| __IO RTC_DBGCTRL_Type | DBGCTRL |
| Offset: 0x0E (R/W 8) Debug Control. | |
| RoReg8 | Reserved1 [0x1] |
| __I RTC_MODE1_SYNCBUSY_Type | SYNCBUSY |
| Offset: 0x10 (R/ 32) MODE1 Synchronization Busy Status. | |
| __IO RTC_FREQCORR_Type | FREQCORR |
| Offset: 0x14 (R/W 8) Frequency Correction. | |
| RoReg8 | Reserved2 [0x3] |
| __IO RTC_MODE1_COUNT_Type | COUNT |
| Offset: 0x18 (R/W 16) MODE1 Counter Value. | |
| RoReg8 | Reserved3 [0x2] |
| __IO RTC_MODE1_PER_Type | PER |
| Offset: 0x1C (R/W 16) MODE1 Counter Period. | |
| RoReg8 | Reserved4 [0x2] |
| __IO RTC_MODE1_COMP_Type | COMP [4] |
| Offset: 0x20 (R/W 16) MODE1 Compare n Value. | |
| RoReg8 | Reserved5 [0x18] |
| __IO RTC_GP_Type | GP [4] |
| Offset: 0x40 (R/W 32) General Purpose. | |
| RoReg8 | Reserved6 [0x10] |
| __IO RTC_TAMPCTRL_Type | TAMPCTRL |
| Offset: 0x60 (R/W 32) Tamper Control. | |
| __I RTC_MODE1_TIMESTAMP_Type | TIMESTAMP |
| Offset: 0x64 (R/ 32) MODE1 Timestamp. | |
| __IO RTC_TAMPID_Type | TAMPID |
| Offset: 0x68 (R/W 32) Tamper ID. | |
| RoReg8 | Reserved7 [0x14] |
| __IO RTC_BKUP_Type | BKUP [8] |
| Offset: 0x80 (R/W 32) Backup. | |
1.8.20