RAMECC hardware registers. More...

#include <ramecc.h>

Data Fields
__IO RAMECC_INTENCLR_Type	INTENCLR
	Offset: 0x0 (R/W 8) Interrupt Enable Clear.

__IO RAMECC_INTENSET_Type	INTENSET
	Offset: 0x1 (R/W 8) Interrupt Enable Set.

__IO RAMECC_INTFLAG_Type	INTFLAG
	Offset: 0x2 (R/W 8) Interrupt Flag.

__I RAMECC_STATUS_Type	STATUS
	Offset: 0x3 (R/ 8) Status.

__I RAMECC_ERRADDR_Type	ERRADDR
	Offset: 0x4 (R/ 32) Error Address.

RoReg8	Reserved1 [0x7]

__IO RAMECC_DBGCTRL_Type	DBGCTRL
	Offset: 0xF (R/W 8) Debug Control.

Detailed Description

RAMECC hardware registers.

Definition at line 165 of file ramecc.h.

The documentation for this struct was generated from the following file:

/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/ramecc.h

Data Fields