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SAME54P20A Test Project
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PICOP hardware registers. More...
#include <picop.h>
Data Fields | |
| __IO PICOP_ID_Type | ID [8] |
| Offset: 0x000 (R/W 32) ID n. | |
| __IO PICOP_CONFIG_Type | CONFIG |
| Offset: 0x020 (R/W 32) Configuration. | |
| __IO PICOP_CTRL_Type | CTRL |
| Offset: 0x024 (R/W 32) Control. | |
| __IO PICOP_CMD_Type | CMD |
| Offset: 0x028 (R/W 32) Command. | |
| __IO PICOP_PC_Type | PC |
| Offset: 0x02C (R/W 32) Program Counter. | |
| __IO PICOP_HF_Type | HF |
| Offset: 0x030 (R/W 32) Host Flags. | |
| __IO PICOP_HFCTRL_Type | HFCTRL |
| Offset: 0x034 (R/W 32) Host Flag Control. | |
| __IO PICOP_HFSETCLR0_Type | HFSETCLR0 |
| Offset: 0x038 (R/W 32) Host Flags Set/Clr. | |
| __IO PICOP_HFSETCLR1_Type | HFSETCLR1 |
| Offset: 0x03C (R/W 32) Host Flags Set/Clr. | |
| RoReg8 | Reserved1 [0x10] |
| __IO PICOP_OCDCONFIG_Type | OCDCONFIG |
| Offset: 0x050 (R/W 32) OCD Configuration. | |
| __IO PICOP_OCDCONTROL_Type | OCDCONTROL |
| Offset: 0x054 (R/W 32) OCD Control. | |
| __IO PICOP_OCDSTATUS_Type | OCDSTATUS |
| Offset: 0x058 (R/W 32) OCD Status and Command. | |
| __IO PICOP_OCDPC_Type | OCDPC |
| Offset: 0x05C (R/W 32) ODC Program Counter. | |
| __IO PICOP_OCDFEAT_Type | OCDFEAT |
| Offset: 0x060 (R/W 32) OCD Features. | |
| RoReg8 | Reserved2 [0x4] |
| __IO PICOP_OCDCCNT_Type | OCDCCNT |
| Offset: 0x068 (R/W 32) OCD Cycle Counter. | |
| RoReg8 | Reserved3 [0x4] |
| __IO PICOP_OCDBPGEN_Type | OCDBPGEN [4] |
| Offset: 0x070 (R/W 32) OCD Breakpoint Generator n. | |
| __IO PICOP_R3R0_Type | R3R0 |
| Offset: 0x080 (R/W 32) R3 to 0. | |
| __IO PICOP_R7R4_Type | R7R4 |
| Offset: 0x084 (R/W 32) R7 to 4. | |
| __IO PICOP_R11R8_Type | R11R8 |
| Offset: 0x088 (R/W 32) R11 to 8. | |
| __IO PICOP_R15R12_Type | R15R12 |
| Offset: 0x08C (R/W 32) R15 to 12. | |
| __IO PICOP_R19R16_Type | R19R16 |
| Offset: 0x090 (R/W 32) R19 to 16. | |
| __IO PICOP_R23R20_Type | R23R20 |
| Offset: 0x094 (R/W 32) R23 to 20. | |
| __IO PICOP_R27R24_Type | R27R24 |
| Offset: 0x098 (R/W 32) R27 to 24: XH, XL, R25, R24. | |
| __IO PICOP_R31R28_Type | R31R28 |
| Offset: 0x09C (R/W 32) R31 to 28: ZH, ZL, YH, YL. | |
| __IO PICOP_S1S0_Type | S1S0 |
| Offset: 0x0A0 (R/W 32) System Regs 1 to 0: SR. | |
| __IO PICOP_S3S2_Type | S3S2 |
| Offset: 0x0A4 (R/W 32) System Regs 3 to 2: CTRL. | |
| __IO PICOP_S5S4_Type | S5S4 |
| Offset: 0x0A8 (R/W 32) System Regs 5 to 4: SREG, CCR. | |
| RoReg8 | Reserved4 [0x8] |
| __IO PICOP_S11S10_Type | S11S10 |
| Offset: 0x0B4 (R/W 32) System Regs 11 to 10: Immediate. | |
| __IO PICOP_LINK_Type | LINK |
| Offset: 0x0B8 (R/W 32) Link. | |
| __IO PICOP_SP_Type | SP |
| Offset: 0x0BC (R/W 32) Stack Pointer. | |
| RoReg8 | Reserved5 [0x40] |
| __IO PICOP_MMUFLASH_Type | MMUFLASH |
| Offset: 0x100 (R/W 32) MMU mapping for flash. | |
| RoReg8 | Reserved6 [0x14] |
| __IO PICOP_MMU0_Type | MMU0 |
| Offset: 0x118 (R/W 32) MMU mapping user 0. | |
| __IO PICOP_MMU1_Type | MMU1 |
| Offset: 0x11C (R/W 32) MMU mapping user 1. | |
| __IO PICOP_MMUCTRL_Type | MMUCTRL |
| Offset: 0x120 (R/W 32) MMU Control. | |
| RoReg8 | Reserved7 [0x5C] |
| __IO PICOP_ICACHE_Type | ICACHE |
| Offset: 0x180 (R/W 32) Instruction Cache Control. | |
| __IO PICOP_ICACHELRU_Type | ICACHELRU |
| Offset: 0x184 (R/W 32) Instruction Cache LRU. | |
| RoReg8 | Reserved8 [0x78] |
| __IO PICOP_QOSCTRL_Type | QOSCTRL |
| Offset: 0x200 (R/W 32) QOS Control. | |
1.8.20