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SAME54P20A Test Project
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NVMCTRL APB hardware registers. More...
#include <nvmctrl.h>
Data Fields | |
| __IO NVMCTRL_CTRLA_Type | CTRLA |
| Offset: 0x00 (R/W 16) Control A. | |
| RoReg8 | Reserved1 [0x2] |
| __O NVMCTRL_CTRLB_Type | CTRLB |
| Offset: 0x04 ( /W 16) Control B. | |
| RoReg8 | Reserved2 [0x2] |
| __I NVMCTRL_PARAM_Type | PARAM |
| Offset: 0x08 (R/ 32) NVM Parameter. | |
| __IO NVMCTRL_INTENCLR_Type | INTENCLR |
| Offset: 0x0C (R/W 16) Interrupt Enable Clear. | |
| __IO NVMCTRL_INTENSET_Type | INTENSET |
| Offset: 0x0E (R/W 16) Interrupt Enable Set. | |
| __IO NVMCTRL_INTFLAG_Type | INTFLAG |
| Offset: 0x10 (R/W 16) Interrupt Flag Status and Clear. | |
| __I NVMCTRL_STATUS_Type | STATUS |
| Offset: 0x12 (R/ 16) Status. | |
| __IO NVMCTRL_ADDR_Type | ADDR |
| Offset: 0x14 (R/W 32) Address. | |
| __I NVMCTRL_RUNLOCK_Type | RUNLOCK |
| Offset: 0x18 (R/ 32) Lock Section. | |
| __I NVMCTRL_PBLDATA_Type | PBLDATA [2] |
| Offset: 0x1C (R/ 32) Page Buffer Load Data x. | |
| __I NVMCTRL_ECCERR_Type | ECCERR |
| Offset: 0x24 (R/ 32) ECC Error Status Register. | |
| __IO NVMCTRL_DBGCTRL_Type | DBGCTRL |
| Offset: 0x28 (R/W 8) Debug Control. | |
| RoReg8 | Reserved3 [0x1] |
| __IO NVMCTRL_SEECFG_Type | SEECFG |
| Offset: 0x2A (R/W 8) SmartEEPROM Configuration Register. | |
| RoReg8 | Reserved4 [0x1] |
| __I NVMCTRL_SEESTAT_Type | SEESTAT |
| Offset: 0x2C (R/ 32) SmartEEPROM Status Register. | |
1.8.20