Component description for SUPC. More...

Data Structures
union	SUPC_INTENCLR_Type

union	SUPC_INTENSET_Type

union	SUPC_INTFLAG_Type

union	SUPC_STATUS_Type

union	SUPC_BOD33_Type

union	SUPC_VREG_Type

union	SUPC_VREF_Type

union	SUPC_BBPS_Type

union	SUPC_BKOUT_Type

union	SUPC_BKIN_Type

struct	Supc
	SUPC hardware registers. More...

Macros
#define	SUPC_U2407

#define	REV_SUPC 0x110

#define	SUPC_INTENCLR_OFFSET 0x00
	(SUPC_INTENCLR offset) Interrupt Enable Clear

#define	SUPC_INTENCLR_RESETVALUE _U_(0x00000000)
	(SUPC_INTENCLR reset_value) Interrupt Enable Clear

#define	SUPC_INTENCLR_BOD33RDY_Pos 0
	(SUPC_INTENCLR) BOD33 Ready

#define	SUPC_INTENCLR_BOD33RDY (_U_(0x1) << SUPC_INTENCLR_BOD33RDY_Pos)

#define	SUPC_INTENCLR_BOD33DET_Pos 1
	(SUPC_INTENCLR) BOD33 Detection

#define	SUPC_INTENCLR_BOD33DET (_U_(0x1) << SUPC_INTENCLR_BOD33DET_Pos)

#define	SUPC_INTENCLR_B33SRDY_Pos 2
	(SUPC_INTENCLR) BOD33 Synchronization Ready

#define	SUPC_INTENCLR_B33SRDY (_U_(0x1) << SUPC_INTENCLR_B33SRDY_Pos)

#define	SUPC_INTENCLR_VREGRDY_Pos 8
	(SUPC_INTENCLR) Voltage Regulator Ready

#define	SUPC_INTENCLR_VREGRDY (_U_(0x1) << SUPC_INTENCLR_VREGRDY_Pos)

#define	SUPC_INTENCLR_VCORERDY_Pos 10
	(SUPC_INTENCLR) VDDCORE Ready

#define	SUPC_INTENCLR_VCORERDY (_U_(0x1) << SUPC_INTENCLR_VCORERDY_Pos)

#define	SUPC_INTENCLR_MASK _U_(0x00000507)
	(SUPC_INTENCLR) MASK Register

#define	SUPC_INTENSET_OFFSET 0x04
	(SUPC_INTENSET offset) Interrupt Enable Set

#define	SUPC_INTENSET_RESETVALUE _U_(0x00000000)
	(SUPC_INTENSET reset_value) Interrupt Enable Set

#define	SUPC_INTENSET_BOD33RDY_Pos 0
	(SUPC_INTENSET) BOD33 Ready

#define	SUPC_INTENSET_BOD33RDY (_U_(0x1) << SUPC_INTENSET_BOD33RDY_Pos)

#define	SUPC_INTENSET_BOD33DET_Pos 1
	(SUPC_INTENSET) BOD33 Detection

#define	SUPC_INTENSET_BOD33DET (_U_(0x1) << SUPC_INTENSET_BOD33DET_Pos)

#define	SUPC_INTENSET_B33SRDY_Pos 2
	(SUPC_INTENSET) BOD33 Synchronization Ready

#define	SUPC_INTENSET_B33SRDY (_U_(0x1) << SUPC_INTENSET_B33SRDY_Pos)

#define	SUPC_INTENSET_VREGRDY_Pos 8
	(SUPC_INTENSET) Voltage Regulator Ready

#define	SUPC_INTENSET_VREGRDY (_U_(0x1) << SUPC_INTENSET_VREGRDY_Pos)

#define	SUPC_INTENSET_VCORERDY_Pos 10
	(SUPC_INTENSET) VDDCORE Ready

#define	SUPC_INTENSET_VCORERDY (_U_(0x1) << SUPC_INTENSET_VCORERDY_Pos)

#define	SUPC_INTENSET_MASK _U_(0x00000507)
	(SUPC_INTENSET) MASK Register

#define	SUPC_INTFLAG_OFFSET 0x08
	(SUPC_INTFLAG offset) Interrupt Flag Status and Clear

#define	SUPC_INTFLAG_RESETVALUE _U_(0x00000000)
	(SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear

#define	SUPC_INTFLAG_BOD33RDY_Pos 0
	(SUPC_INTFLAG) BOD33 Ready

#define	SUPC_INTFLAG_BOD33RDY (_U_(0x1) << SUPC_INTFLAG_BOD33RDY_Pos)

#define	SUPC_INTFLAG_BOD33DET_Pos 1
	(SUPC_INTFLAG) BOD33 Detection

#define	SUPC_INTFLAG_BOD33DET (_U_(0x1) << SUPC_INTFLAG_BOD33DET_Pos)

#define	SUPC_INTFLAG_B33SRDY_Pos 2
	(SUPC_INTFLAG) BOD33 Synchronization Ready

#define	SUPC_INTFLAG_B33SRDY (_U_(0x1) << SUPC_INTFLAG_B33SRDY_Pos)

#define	SUPC_INTFLAG_VREGRDY_Pos 8
	(SUPC_INTFLAG) Voltage Regulator Ready

#define	SUPC_INTFLAG_VREGRDY (_U_(0x1) << SUPC_INTFLAG_VREGRDY_Pos)

#define	SUPC_INTFLAG_VCORERDY_Pos 10
	(SUPC_INTFLAG) VDDCORE Ready

#define	SUPC_INTFLAG_VCORERDY (_U_(0x1) << SUPC_INTFLAG_VCORERDY_Pos)

#define	SUPC_INTFLAG_MASK _U_(0x00000507)
	(SUPC_INTFLAG) MASK Register

#define	SUPC_STATUS_OFFSET 0x0C
	(SUPC_STATUS offset) Power and Clocks Status

#define	SUPC_STATUS_RESETVALUE _U_(0x00000000)
	(SUPC_STATUS reset_value) Power and Clocks Status

#define	SUPC_STATUS_BOD33RDY_Pos 0
	(SUPC_STATUS) BOD33 Ready

#define	SUPC_STATUS_BOD33RDY (_U_(0x1) << SUPC_STATUS_BOD33RDY_Pos)

#define	SUPC_STATUS_BOD33DET_Pos 1
	(SUPC_STATUS) BOD33 Detection

#define	SUPC_STATUS_BOD33DET (_U_(0x1) << SUPC_STATUS_BOD33DET_Pos)

#define	SUPC_STATUS_B33SRDY_Pos 2
	(SUPC_STATUS) BOD33 Synchronization Ready

#define	SUPC_STATUS_B33SRDY (_U_(0x1) << SUPC_STATUS_B33SRDY_Pos)

#define	SUPC_STATUS_VREGRDY_Pos 8
	(SUPC_STATUS) Voltage Regulator Ready

#define	SUPC_STATUS_VREGRDY (_U_(0x1) << SUPC_STATUS_VREGRDY_Pos)

#define	SUPC_STATUS_VCORERDY_Pos 10
	(SUPC_STATUS) VDDCORE Ready

#define	SUPC_STATUS_VCORERDY (_U_(0x1) << SUPC_STATUS_VCORERDY_Pos)

#define	SUPC_STATUS_MASK _U_(0x00000507)
	(SUPC_STATUS) MASK Register

#define	SUPC_BOD33_OFFSET 0x10
	(SUPC_BOD33 offset) BOD33 Control

#define	SUPC_BOD33_RESETVALUE _U_(0x00000000)
	(SUPC_BOD33 reset_value) BOD33 Control

#define	SUPC_BOD33_ENABLE_Pos 1
	(SUPC_BOD33) Enable

#define	SUPC_BOD33_ENABLE (_U_(0x1) << SUPC_BOD33_ENABLE_Pos)

#define	SUPC_BOD33_ACTION_Pos 2
	(SUPC_BOD33) Action when Threshold Crossed

#define	SUPC_BOD33_ACTION_Msk (_U_(0x3) << SUPC_BOD33_ACTION_Pos)

#define	SUPC_BOD33_ACTION(value) (SUPC_BOD33_ACTION_Msk & ((value) << SUPC_BOD33_ACTION_Pos))

#define	SUPC_BOD33_ACTION_NONE_Val _U_(0x0)
	(SUPC_BOD33) No action

#define	SUPC_BOD33_ACTION_RESET_Val _U_(0x1)
	(SUPC_BOD33) The BOD33 generates a reset

#define	SUPC_BOD33_ACTION_INT_Val _U_(0x2)
	(SUPC_BOD33) The BOD33 generates an interrupt

#define	SUPC_BOD33_ACTION_BKUP_Val _U_(0x3)
	(SUPC_BOD33) The BOD33 puts the device in backup sleep mode

#define	SUPC_BOD33_ACTION_NONE (SUPC_BOD33_ACTION_NONE_Val << SUPC_BOD33_ACTION_Pos)

#define	SUPC_BOD33_ACTION_RESET (SUPC_BOD33_ACTION_RESET_Val << SUPC_BOD33_ACTION_Pos)

#define	SUPC_BOD33_ACTION_INT (SUPC_BOD33_ACTION_INT_Val << SUPC_BOD33_ACTION_Pos)

#define	SUPC_BOD33_ACTION_BKUP (SUPC_BOD33_ACTION_BKUP_Val << SUPC_BOD33_ACTION_Pos)

#define	SUPC_BOD33_STDBYCFG_Pos 4
	(SUPC_BOD33) Configuration in Standby mode

#define	SUPC_BOD33_STDBYCFG (_U_(0x1) << SUPC_BOD33_STDBYCFG_Pos)

#define	SUPC_BOD33_RUNSTDBY_Pos 5
	(SUPC_BOD33) Run in Standby mode

#define	SUPC_BOD33_RUNSTDBY (_U_(0x1) << SUPC_BOD33_RUNSTDBY_Pos)

#define	SUPC_BOD33_RUNHIB_Pos 6
	(SUPC_BOD33) Run in Hibernate mode

#define	SUPC_BOD33_RUNHIB (_U_(0x1) << SUPC_BOD33_RUNHIB_Pos)

#define	SUPC_BOD33_RUNBKUP_Pos 7
	(SUPC_BOD33) Run in Backup mode

#define	SUPC_BOD33_RUNBKUP (_U_(0x1) << SUPC_BOD33_RUNBKUP_Pos)

#define	SUPC_BOD33_HYST_Pos 8
	(SUPC_BOD33) Hysteresis value

#define	SUPC_BOD33_HYST_Msk (_U_(0xF) << SUPC_BOD33_HYST_Pos)

#define	SUPC_BOD33_HYST(value) (SUPC_BOD33_HYST_Msk & ((value) << SUPC_BOD33_HYST_Pos))

#define	SUPC_BOD33_PSEL_Pos 12
	(SUPC_BOD33) Prescaler Select

#define	SUPC_BOD33_PSEL_Msk (_U_(0x7) << SUPC_BOD33_PSEL_Pos)

#define	SUPC_BOD33_PSEL(value) (SUPC_BOD33_PSEL_Msk & ((value) << SUPC_BOD33_PSEL_Pos))

#define	SUPC_BOD33_PSEL_NODIV_Val _U_(0x0)
	(SUPC_BOD33) Not divided

#define	SUPC_BOD33_PSEL_DIV4_Val _U_(0x1)
	(SUPC_BOD33) Divide clock by 4

#define	SUPC_BOD33_PSEL_DIV8_Val _U_(0x2)
	(SUPC_BOD33) Divide clock by 8

#define	SUPC_BOD33_PSEL_DIV16_Val _U_(0x3)
	(SUPC_BOD33) Divide clock by 16

#define	SUPC_BOD33_PSEL_DIV32_Val _U_(0x4)
	(SUPC_BOD33) Divide clock by 32

#define	SUPC_BOD33_PSEL_DIV64_Val _U_(0x5)
	(SUPC_BOD33) Divide clock by 64

#define	SUPC_BOD33_PSEL_DIV128_Val _U_(0x6)
	(SUPC_BOD33) Divide clock by 128

#define	SUPC_BOD33_PSEL_DIV256_Val _U_(0x7)
	(SUPC_BOD33) Divide clock by 256

#define	SUPC_BOD33_PSEL_NODIV (SUPC_BOD33_PSEL_NODIV_Val << SUPC_BOD33_PSEL_Pos)

#define	SUPC_BOD33_PSEL_DIV4 (SUPC_BOD33_PSEL_DIV4_Val << SUPC_BOD33_PSEL_Pos)

#define	SUPC_BOD33_PSEL_DIV8 (SUPC_BOD33_PSEL_DIV8_Val << SUPC_BOD33_PSEL_Pos)

#define	SUPC_BOD33_PSEL_DIV16 (SUPC_BOD33_PSEL_DIV16_Val << SUPC_BOD33_PSEL_Pos)

#define	SUPC_BOD33_PSEL_DIV32 (SUPC_BOD33_PSEL_DIV32_Val << SUPC_BOD33_PSEL_Pos)

#define	SUPC_BOD33_PSEL_DIV64 (SUPC_BOD33_PSEL_DIV64_Val << SUPC_BOD33_PSEL_Pos)

#define	SUPC_BOD33_PSEL_DIV128 (SUPC_BOD33_PSEL_DIV128_Val << SUPC_BOD33_PSEL_Pos)

#define	SUPC_BOD33_PSEL_DIV256 (SUPC_BOD33_PSEL_DIV256_Val << SUPC_BOD33_PSEL_Pos)

#define	SUPC_BOD33_LEVEL_Pos 16
	(SUPC_BOD33) Threshold Level for VDD

#define	SUPC_BOD33_LEVEL_Msk (_U_(0xFF) << SUPC_BOD33_LEVEL_Pos)

#define	SUPC_BOD33_LEVEL(value) (SUPC_BOD33_LEVEL_Msk & ((value) << SUPC_BOD33_LEVEL_Pos))

#define	SUPC_BOD33_VBATLEVEL_Pos 24
	(SUPC_BOD33) Threshold Level in battery backup sleep mode for VBAT

#define	SUPC_BOD33_VBATLEVEL_Msk (_U_(0xFF) << SUPC_BOD33_VBATLEVEL_Pos)

#define	SUPC_BOD33_VBATLEVEL(value) (SUPC_BOD33_VBATLEVEL_Msk & ((value) << SUPC_BOD33_VBATLEVEL_Pos))

#define	SUPC_BOD33_MASK _U_(0xFFFF7FFE)
	(SUPC_BOD33) MASK Register

#define	SUPC_VREG_OFFSET 0x18
	(SUPC_VREG offset) VREG Control

#define	SUPC_VREG_RESETVALUE _U_(0x00000002)
	(SUPC_VREG reset_value) VREG Control

#define	SUPC_VREG_ENABLE_Pos 1
	(SUPC_VREG) Enable

#define	SUPC_VREG_ENABLE (_U_(0x1) << SUPC_VREG_ENABLE_Pos)

#define	SUPC_VREG_SEL_Pos 2
	(SUPC_VREG) Voltage Regulator Selection

#define	SUPC_VREG_SEL (_U_(0x1) << SUPC_VREG_SEL_Pos)

#define	SUPC_VREG_SEL_LDO_Val _U_(0x0)
	(SUPC_VREG) LDO selection

#define	SUPC_VREG_SEL_BUCK_Val _U_(0x1)
	(SUPC_VREG) Buck selection

#define	SUPC_VREG_SEL_LDO (SUPC_VREG_SEL_LDO_Val << SUPC_VREG_SEL_Pos)

#define	SUPC_VREG_SEL_BUCK (SUPC_VREG_SEL_BUCK_Val << SUPC_VREG_SEL_Pos)

#define	SUPC_VREG_RUNBKUP_Pos 7
	(SUPC_VREG) Run in Backup mode

#define	SUPC_VREG_RUNBKUP (_U_(0x1) << SUPC_VREG_RUNBKUP_Pos)

#define	SUPC_VREG_VSEN_Pos 16
	(SUPC_VREG) Voltage Scaling Enable

#define	SUPC_VREG_VSEN (_U_(0x1) << SUPC_VREG_VSEN_Pos)

#define	SUPC_VREG_VSPER_Pos 24
	(SUPC_VREG) Voltage Scaling Period

#define	SUPC_VREG_VSPER_Msk (_U_(0x7) << SUPC_VREG_VSPER_Pos)

#define	SUPC_VREG_VSPER(value) (SUPC_VREG_VSPER_Msk & ((value) << SUPC_VREG_VSPER_Pos))

#define	SUPC_VREG_MASK _U_(0x07010086)
	(SUPC_VREG) MASK Register

#define	SUPC_VREF_OFFSET 0x1C
	(SUPC_VREF offset) VREF Control

#define	SUPC_VREF_RESETVALUE _U_(0x00000000)
	(SUPC_VREF reset_value) VREF Control

#define	SUPC_VREF_TSEN_Pos 1
	(SUPC_VREF) Temperature Sensor Output Enable

#define	SUPC_VREF_TSEN (_U_(0x1) << SUPC_VREF_TSEN_Pos)

#define	SUPC_VREF_VREFOE_Pos 2
	(SUPC_VREF) Voltage Reference Output Enable

#define	SUPC_VREF_VREFOE (_U_(0x1) << SUPC_VREF_VREFOE_Pos)

#define	SUPC_VREF_TSSEL_Pos 3
	(SUPC_VREF) Temperature Sensor Selection

#define	SUPC_VREF_TSSEL (_U_(0x1) << SUPC_VREF_TSSEL_Pos)

#define	SUPC_VREF_RUNSTDBY_Pos 6
	(SUPC_VREF) Run during Standby

#define	SUPC_VREF_RUNSTDBY (_U_(0x1) << SUPC_VREF_RUNSTDBY_Pos)

#define	SUPC_VREF_ONDEMAND_Pos 7
	(SUPC_VREF) On Demand Contrl

#define	SUPC_VREF_ONDEMAND (_U_(0x1) << SUPC_VREF_ONDEMAND_Pos)

#define	SUPC_VREF_SEL_Pos 16
	(SUPC_VREF) Voltage Reference Selection

#define	SUPC_VREF_SEL_Msk (_U_(0xF) << SUPC_VREF_SEL_Pos)

#define	SUPC_VREF_SEL(value) (SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos))

#define	SUPC_VREF_SEL_1V0_Val _U_(0x0)
	(SUPC_VREF) 1.0V voltage reference typical value

#define	SUPC_VREF_SEL_1V1_Val _U_(0x1)
	(SUPC_VREF) 1.1V voltage reference typical value

#define	SUPC_VREF_SEL_1V2_Val _U_(0x2)
	(SUPC_VREF) 1.2V voltage reference typical value

#define	SUPC_VREF_SEL_1V25_Val _U_(0x3)
	(SUPC_VREF) 1.25V voltage reference typical value

#define	SUPC_VREF_SEL_2V0_Val _U_(0x4)
	(SUPC_VREF) 2.0V voltage reference typical value

#define	SUPC_VREF_SEL_2V2_Val _U_(0x5)
	(SUPC_VREF) 2.2V voltage reference typical value

#define	SUPC_VREF_SEL_2V4_Val _U_(0x6)
	(SUPC_VREF) 2.4V voltage reference typical value

#define	SUPC_VREF_SEL_2V5_Val _U_(0x7)
	(SUPC_VREF) 2.5V voltage reference typical value

#define	SUPC_VREF_SEL_1V0 (SUPC_VREF_SEL_1V0_Val << SUPC_VREF_SEL_Pos)

#define	SUPC_VREF_SEL_1V1 (SUPC_VREF_SEL_1V1_Val << SUPC_VREF_SEL_Pos)

#define	SUPC_VREF_SEL_1V2 (SUPC_VREF_SEL_1V2_Val << SUPC_VREF_SEL_Pos)

#define	SUPC_VREF_SEL_1V25 (SUPC_VREF_SEL_1V25_Val << SUPC_VREF_SEL_Pos)

#define	SUPC_VREF_SEL_2V0 (SUPC_VREF_SEL_2V0_Val << SUPC_VREF_SEL_Pos)

#define	SUPC_VREF_SEL_2V2 (SUPC_VREF_SEL_2V2_Val << SUPC_VREF_SEL_Pos)

#define	SUPC_VREF_SEL_2V4 (SUPC_VREF_SEL_2V4_Val << SUPC_VREF_SEL_Pos)

#define	SUPC_VREF_SEL_2V5 (SUPC_VREF_SEL_2V5_Val << SUPC_VREF_SEL_Pos)

#define	SUPC_VREF_MASK _U_(0x000F00CE)
	(SUPC_VREF) MASK Register

#define	SUPC_BBPS_OFFSET 0x20
	(SUPC_BBPS offset) Battery Backup Power Switch

#define	SUPC_BBPS_RESETVALUE _U_(0x00000000)
	(SUPC_BBPS reset_value) Battery Backup Power Switch

#define	SUPC_BBPS_CONF_Pos 0
	(SUPC_BBPS) Battery Backup Configuration

#define	SUPC_BBPS_CONF (_U_(0x1) << SUPC_BBPS_CONF_Pos)

#define	SUPC_BBPS_CONF_BOD33_Val _U_(0x0)
	(SUPC_BBPS) The power switch is handled by the BOD33

#define	SUPC_BBPS_CONF_FORCED_Val _U_(0x1)
	(SUPC_BBPS) In Backup Domain, the backup domain is always supplied by battery backup power

#define	SUPC_BBPS_CONF_BOD33 (SUPC_BBPS_CONF_BOD33_Val << SUPC_BBPS_CONF_Pos)

#define	SUPC_BBPS_CONF_FORCED (SUPC_BBPS_CONF_FORCED_Val << SUPC_BBPS_CONF_Pos)

#define	SUPC_BBPS_WAKEEN_Pos 2
	(SUPC_BBPS) Wake Enable

#define	SUPC_BBPS_WAKEEN (_U_(0x1) << SUPC_BBPS_WAKEEN_Pos)

#define	SUPC_BBPS_MASK _U_(0x00000005)
	(SUPC_BBPS) MASK Register

#define	SUPC_BKOUT_OFFSET 0x24
	(SUPC_BKOUT offset) Backup Output Control

#define	SUPC_BKOUT_RESETVALUE _U_(0x00000000)
	(SUPC_BKOUT reset_value) Backup Output Control

#define	SUPC_BKOUT_EN_Pos 0
	(SUPC_BKOUT) Enable Output

#define	SUPC_BKOUT_EN_Msk (_U_(0x3) << SUPC_BKOUT_EN_Pos)

#define	SUPC_BKOUT_EN(value) (SUPC_BKOUT_EN_Msk & ((value) << SUPC_BKOUT_EN_Pos))

#define	SUPC_BKOUT_CLR_Pos 8
	(SUPC_BKOUT) Clear Output

#define	SUPC_BKOUT_CLR_Msk (_U_(0x3) << SUPC_BKOUT_CLR_Pos)

#define	SUPC_BKOUT_CLR(value) (SUPC_BKOUT_CLR_Msk & ((value) << SUPC_BKOUT_CLR_Pos))

#define	SUPC_BKOUT_SET_Pos 16
	(SUPC_BKOUT) Set Output

#define	SUPC_BKOUT_SET_Msk (_U_(0x3) << SUPC_BKOUT_SET_Pos)

#define	SUPC_BKOUT_SET(value) (SUPC_BKOUT_SET_Msk & ((value) << SUPC_BKOUT_SET_Pos))

#define	SUPC_BKOUT_RTCTGL_Pos 24
	(SUPC_BKOUT) RTC Toggle Output

#define	SUPC_BKOUT_RTCTGL_Msk (_U_(0x3) << SUPC_BKOUT_RTCTGL_Pos)

#define	SUPC_BKOUT_RTCTGL(value) (SUPC_BKOUT_RTCTGL_Msk & ((value) << SUPC_BKOUT_RTCTGL_Pos))

#define	SUPC_BKOUT_MASK _U_(0x03030303)
	(SUPC_BKOUT) MASK Register

#define	SUPC_BKIN_OFFSET 0x28
	(SUPC_BKIN offset) Backup Input Control

#define	SUPC_BKIN_RESETVALUE _U_(0x00000000)
	(SUPC_BKIN reset_value) Backup Input Control

#define	SUPC_BKIN_BKIN_Pos 0
	(SUPC_BKIN) Backup Input Value

#define	SUPC_BKIN_BKIN_Msk (_U_(0xFF) << SUPC_BKIN_BKIN_Pos)

#define	SUPC_BKIN_BKIN(value) (SUPC_BKIN_BKIN_Msk & ((value) << SUPC_BKIN_BKIN_Pos))

#define	SUPC_BKIN_MASK _U_(0x000000FF)
	(SUPC_BKIN) MASK Register

Detailed Description

Component description for SUPC.

\asf_license_start

Definition in file supc.h.

Data Structures

Macros

Detailed Description