Component description for OSCCTRL. More...

Data Structures
union	OSCCTRL_EVCTRL_Type

union	OSCCTRL_INTENCLR_Type

union	OSCCTRL_INTENSET_Type

union	OSCCTRL_INTFLAG_Type

union	OSCCTRL_STATUS_Type

union	OSCCTRL_XOSCCTRL_Type

union	OSCCTRL_DFLLCTRLA_Type

union	OSCCTRL_DFLLCTRLB_Type

union	OSCCTRL_DFLLVAL_Type

union	OSCCTRL_DFLLMUL_Type

union	OSCCTRL_DFLLSYNC_Type

union	OSCCTRL_DPLLCTRLA_Type

union	OSCCTRL_DPLLRATIO_Type

union	OSCCTRL_DPLLCTRLB_Type

union	OSCCTRL_DPLLSYNCBUSY_Type

union	OSCCTRL_DPLLSTATUS_Type

struct	OscctrlDpll
	OscctrlDpll hardware registers. More...

struct	Oscctrl
	OSCCTRL hardware registers. More...

Macros
#define	OSCCTRL_U2401

#define	REV_OSCCTRL 0x100

#define	OSCCTRL_EVCTRL_OFFSET 0x00
	(OSCCTRL_EVCTRL offset) Event Control

#define	OSCCTRL_EVCTRL_RESETVALUE _U_(0x00)
	(OSCCTRL_EVCTRL reset_value) Event Control

#define	OSCCTRL_EVCTRL_CFDEO0_Pos 0
	(OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable

#define	OSCCTRL_EVCTRL_CFDEO0 (_U_(1) << OSCCTRL_EVCTRL_CFDEO0_Pos)

#define	OSCCTRL_EVCTRL_CFDEO1_Pos 1
	(OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable

#define	OSCCTRL_EVCTRL_CFDEO1 (_U_(1) << OSCCTRL_EVCTRL_CFDEO1_Pos)

#define	OSCCTRL_EVCTRL_CFDEO_Pos 0
	(OSCCTRL_EVCTRL) Clock x Failure Detector Event Output Enable

#define	OSCCTRL_EVCTRL_CFDEO_Msk (_U_(0x3) << OSCCTRL_EVCTRL_CFDEO_Pos)

#define	OSCCTRL_EVCTRL_CFDEO(value) (OSCCTRL_EVCTRL_CFDEO_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO_Pos))

#define	OSCCTRL_EVCTRL_MASK _U_(0x03)
	(OSCCTRL_EVCTRL) MASK Register

#define	OSCCTRL_INTENCLR_OFFSET 0x04
	(OSCCTRL_INTENCLR offset) Interrupt Enable Clear

#define	OSCCTRL_INTENCLR_RESETVALUE _U_(0x00000000)
	(OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear

#define	OSCCTRL_INTENCLR_XOSCRDY0_Pos 0
	(OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable

#define	OSCCTRL_INTENCLR_XOSCRDY0 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY0_Pos)

#define	OSCCTRL_INTENCLR_XOSCRDY1_Pos 1
	(OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable

#define	OSCCTRL_INTENCLR_XOSCRDY1 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY1_Pos)

#define	OSCCTRL_INTENCLR_XOSCRDY_Pos 0
	(OSCCTRL_INTENCLR) XOSC x Ready Interrupt Enable

#define	OSCCTRL_INTENCLR_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCRDY_Pos)

#define	OSCCTRL_INTENCLR_XOSCRDY(value) (OSCCTRL_INTENCLR_XOSCRDY_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY_Pos))

#define	OSCCTRL_INTENCLR_XOSCFAIL0_Pos 2
	(OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable

#define	OSCCTRL_INTENCLR_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos)

#define	OSCCTRL_INTENCLR_XOSCFAIL1_Pos 3
	(OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable

#define	OSCCTRL_INTENCLR_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos)

#define	OSCCTRL_INTENCLR_XOSCFAIL_Pos 2
	(OSCCTRL_INTENCLR) XOSC x Clock Failure Detector Interrupt Enable

#define	OSCCTRL_INTENCLR_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)

#define	OSCCTRL_INTENCLR_XOSCFAIL(value) (OSCCTRL_INTENCLR_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos))

#define	OSCCTRL_INTENCLR_DFLLRDY_Pos 8
	(OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable

#define	OSCCTRL_INTENCLR_DFLLRDY (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos)

#define	OSCCTRL_INTENCLR_DFLLOOB_Pos 9
	(OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable

#define	OSCCTRL_INTENCLR_DFLLOOB (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos)

#define	OSCCTRL_INTENCLR_DFLLLCKF_Pos 10
	(OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable

#define	OSCCTRL_INTENCLR_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos)

#define	OSCCTRL_INTENCLR_DFLLLCKC_Pos 11
	(OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable

#define	OSCCTRL_INTENCLR_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos)

#define	OSCCTRL_INTENCLR_DFLLRCS_Pos 12
	(OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable

#define	OSCCTRL_INTENCLR_DFLLRCS (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos)

#define	OSCCTRL_INTENCLR_DPLL0LCKR_Pos 16
	(OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable

#define	OSCCTRL_INTENCLR_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos)

#define	OSCCTRL_INTENCLR_DPLL0LCKF_Pos 17
	(OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable

#define	OSCCTRL_INTENCLR_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos)

#define	OSCCTRL_INTENCLR_DPLL0LTO_Pos 18
	(OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable

#define	OSCCTRL_INTENCLR_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LTO_Pos)

#define	OSCCTRL_INTENCLR_DPLL0LDRTO_Pos 19
	(OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable

#define	OSCCTRL_INTENCLR_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos)

#define	OSCCTRL_INTENCLR_DPLL1LCKR_Pos 24
	(OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable

#define	OSCCTRL_INTENCLR_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos)

#define	OSCCTRL_INTENCLR_DPLL1LCKF_Pos 25
	(OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable

#define	OSCCTRL_INTENCLR_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos)

#define	OSCCTRL_INTENCLR_DPLL1LTO_Pos 26
	(OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable

#define	OSCCTRL_INTENCLR_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LTO_Pos)

#define	OSCCTRL_INTENCLR_DPLL1LDRTO_Pos 27
	(OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable

#define	OSCCTRL_INTENCLR_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos)

#define	OSCCTRL_INTENCLR_MASK _U_(0x0F0F1F0F)
	(OSCCTRL_INTENCLR) MASK Register

#define	OSCCTRL_INTENSET_OFFSET 0x08
	(OSCCTRL_INTENSET offset) Interrupt Enable Set

#define	OSCCTRL_INTENSET_RESETVALUE _U_(0x00000000)
	(OSCCTRL_INTENSET reset_value) Interrupt Enable Set

#define	OSCCTRL_INTENSET_XOSCRDY0_Pos 0
	(OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable

#define	OSCCTRL_INTENSET_XOSCRDY0 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY0_Pos)

#define	OSCCTRL_INTENSET_XOSCRDY1_Pos 1
	(OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable

#define	OSCCTRL_INTENSET_XOSCRDY1 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY1_Pos)

#define	OSCCTRL_INTENSET_XOSCRDY_Pos 0
	(OSCCTRL_INTENSET) XOSC x Ready Interrupt Enable

#define	OSCCTRL_INTENSET_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCRDY_Pos)

#define	OSCCTRL_INTENSET_XOSCRDY(value) (OSCCTRL_INTENSET_XOSCRDY_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY_Pos))

#define	OSCCTRL_INTENSET_XOSCFAIL0_Pos 2
	(OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable

#define	OSCCTRL_INTENSET_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL0_Pos)

#define	OSCCTRL_INTENSET_XOSCFAIL1_Pos 3
	(OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable

#define	OSCCTRL_INTENSET_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL1_Pos)

#define	OSCCTRL_INTENSET_XOSCFAIL_Pos 2
	(OSCCTRL_INTENSET) XOSC x Clock Failure Detector Interrupt Enable

#define	OSCCTRL_INTENSET_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCFAIL_Pos)

#define	OSCCTRL_INTENSET_XOSCFAIL(value) (OSCCTRL_INTENSET_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL_Pos))

#define	OSCCTRL_INTENSET_DFLLRDY_Pos 8
	(OSCCTRL_INTENSET) DFLL Ready Interrupt Enable

#define	OSCCTRL_INTENSET_DFLLRDY (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos)

#define	OSCCTRL_INTENSET_DFLLOOB_Pos 9
	(OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable

#define	OSCCTRL_INTENSET_DFLLOOB (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos)

#define	OSCCTRL_INTENSET_DFLLLCKF_Pos 10
	(OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable

#define	OSCCTRL_INTENSET_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos)

#define	OSCCTRL_INTENSET_DFLLLCKC_Pos 11
	(OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable

#define	OSCCTRL_INTENSET_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos)

#define	OSCCTRL_INTENSET_DFLLRCS_Pos 12
	(OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable

#define	OSCCTRL_INTENSET_DFLLRCS (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos)

#define	OSCCTRL_INTENSET_DPLL0LCKR_Pos 16
	(OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable

#define	OSCCTRL_INTENSET_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKR_Pos)

#define	OSCCTRL_INTENSET_DPLL0LCKF_Pos 17
	(OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable

#define	OSCCTRL_INTENSET_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKF_Pos)

#define	OSCCTRL_INTENSET_DPLL0LTO_Pos 18
	(OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable

#define	OSCCTRL_INTENSET_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LTO_Pos)

#define	OSCCTRL_INTENSET_DPLL0LDRTO_Pos 19
	(OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable

#define	OSCCTRL_INTENSET_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos)

#define	OSCCTRL_INTENSET_DPLL1LCKR_Pos 24
	(OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable

#define	OSCCTRL_INTENSET_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKR_Pos)

#define	OSCCTRL_INTENSET_DPLL1LCKF_Pos 25
	(OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable

#define	OSCCTRL_INTENSET_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKF_Pos)

#define	OSCCTRL_INTENSET_DPLL1LTO_Pos 26
	(OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable

#define	OSCCTRL_INTENSET_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LTO_Pos)

#define	OSCCTRL_INTENSET_DPLL1LDRTO_Pos 27
	(OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable

#define	OSCCTRL_INTENSET_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos)

#define	OSCCTRL_INTENSET_MASK _U_(0x0F0F1F0F)
	(OSCCTRL_INTENSET) MASK Register

#define	OSCCTRL_INTFLAG_OFFSET 0x0C
	(OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear

#define	OSCCTRL_INTFLAG_RESETVALUE _U_(0x00000000)
	(OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear

#define	OSCCTRL_INTFLAG_XOSCRDY0_Pos 0
	(OSCCTRL_INTFLAG) XOSC 0 Ready

#define	OSCCTRL_INTFLAG_XOSCRDY0 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY0_Pos)

#define	OSCCTRL_INTFLAG_XOSCRDY1_Pos 1
	(OSCCTRL_INTFLAG) XOSC 1 Ready

#define	OSCCTRL_INTFLAG_XOSCRDY1 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY1_Pos)

#define	OSCCTRL_INTFLAG_XOSCRDY_Pos 0
	(OSCCTRL_INTFLAG) XOSC x Ready

#define	OSCCTRL_INTFLAG_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCRDY_Pos)

#define	OSCCTRL_INTFLAG_XOSCRDY(value) (OSCCTRL_INTFLAG_XOSCRDY_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY_Pos))

#define	OSCCTRL_INTFLAG_XOSCFAIL0_Pos 2
	(OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector

#define	OSCCTRL_INTFLAG_XOSCFAIL0 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos)

#define	OSCCTRL_INTFLAG_XOSCFAIL1_Pos 3
	(OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector

#define	OSCCTRL_INTFLAG_XOSCFAIL1 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos)

#define	OSCCTRL_INTFLAG_XOSCFAIL_Pos 2
	(OSCCTRL_INTFLAG) XOSC x Clock Failure Detector

#define	OSCCTRL_INTFLAG_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)

#define	OSCCTRL_INTFLAG_XOSCFAIL(value) (OSCCTRL_INTFLAG_XOSCFAIL_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos))

#define	OSCCTRL_INTFLAG_DFLLRDY_Pos 8
	(OSCCTRL_INTFLAG) DFLL Ready

#define	OSCCTRL_INTFLAG_DFLLRDY (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos)

#define	OSCCTRL_INTFLAG_DFLLOOB_Pos 9
	(OSCCTRL_INTFLAG) DFLL Out Of Bounds

#define	OSCCTRL_INTFLAG_DFLLOOB (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos)

#define	OSCCTRL_INTFLAG_DFLLLCKF_Pos 10
	(OSCCTRL_INTFLAG) DFLL Lock Fine

#define	OSCCTRL_INTFLAG_DFLLLCKF (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos)

#define	OSCCTRL_INTFLAG_DFLLLCKC_Pos 11
	(OSCCTRL_INTFLAG) DFLL Lock Coarse

#define	OSCCTRL_INTFLAG_DFLLLCKC (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos)

#define	OSCCTRL_INTFLAG_DFLLRCS_Pos 12
	(OSCCTRL_INTFLAG) DFLL Reference Clock Stopped

#define	OSCCTRL_INTFLAG_DFLLRCS (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos)

#define	OSCCTRL_INTFLAG_DPLL0LCKR_Pos 16
	(OSCCTRL_INTFLAG) DPLL0 Lock Rise

#define	OSCCTRL_INTFLAG_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos)

#define	OSCCTRL_INTFLAG_DPLL0LCKF_Pos 17
	(OSCCTRL_INTFLAG) DPLL0 Lock Fall

#define	OSCCTRL_INTFLAG_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos)

#define	OSCCTRL_INTFLAG_DPLL0LTO_Pos 18
	(OSCCTRL_INTFLAG) DPLL0 Lock Timeout

#define	OSCCTRL_INTFLAG_DPLL0LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LTO_Pos)

#define	OSCCTRL_INTFLAG_DPLL0LDRTO_Pos 19
	(OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete

#define	OSCCTRL_INTFLAG_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos)

#define	OSCCTRL_INTFLAG_DPLL1LCKR_Pos 24
	(OSCCTRL_INTFLAG) DPLL1 Lock Rise

#define	OSCCTRL_INTFLAG_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos)

#define	OSCCTRL_INTFLAG_DPLL1LCKF_Pos 25
	(OSCCTRL_INTFLAG) DPLL1 Lock Fall

#define	OSCCTRL_INTFLAG_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos)

#define	OSCCTRL_INTFLAG_DPLL1LTO_Pos 26
	(OSCCTRL_INTFLAG) DPLL1 Lock Timeout

#define	OSCCTRL_INTFLAG_DPLL1LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LTO_Pos)

#define	OSCCTRL_INTFLAG_DPLL1LDRTO_Pos 27
	(OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete

#define	OSCCTRL_INTFLAG_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos)

#define	OSCCTRL_INTFLAG_MASK _U_(0x0F0F1F0F)
	(OSCCTRL_INTFLAG) MASK Register

#define	OSCCTRL_STATUS_OFFSET 0x10
	(OSCCTRL_STATUS offset) Status

#define	OSCCTRL_STATUS_RESETVALUE _U_(0x00000000)
	(OSCCTRL_STATUS reset_value) Status

#define	OSCCTRL_STATUS_XOSCRDY0_Pos 0
	(OSCCTRL_STATUS) XOSC 0 Ready

#define	OSCCTRL_STATUS_XOSCRDY0 (_U_(1) << OSCCTRL_STATUS_XOSCRDY0_Pos)

#define	OSCCTRL_STATUS_XOSCRDY1_Pos 1
	(OSCCTRL_STATUS) XOSC 1 Ready

#define	OSCCTRL_STATUS_XOSCRDY1 (_U_(1) << OSCCTRL_STATUS_XOSCRDY1_Pos)

#define	OSCCTRL_STATUS_XOSCRDY_Pos 0
	(OSCCTRL_STATUS) XOSC x Ready

#define	OSCCTRL_STATUS_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCRDY_Pos)

#define	OSCCTRL_STATUS_XOSCRDY(value) (OSCCTRL_STATUS_XOSCRDY_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY_Pos))

#define	OSCCTRL_STATUS_XOSCFAIL0_Pos 2
	(OSCCTRL_STATUS) XOSC 0 Clock Failure Detector

#define	OSCCTRL_STATUS_XOSCFAIL0 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL0_Pos)

#define	OSCCTRL_STATUS_XOSCFAIL1_Pos 3
	(OSCCTRL_STATUS) XOSC 1 Clock Failure Detector

#define	OSCCTRL_STATUS_XOSCFAIL1 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL1_Pos)

#define	OSCCTRL_STATUS_XOSCFAIL_Pos 2
	(OSCCTRL_STATUS) XOSC x Clock Failure Detector

#define	OSCCTRL_STATUS_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCFAIL_Pos)

#define	OSCCTRL_STATUS_XOSCFAIL(value) (OSCCTRL_STATUS_XOSCFAIL_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL_Pos))

#define	OSCCTRL_STATUS_XOSCCKSW0_Pos 4
	(OSCCTRL_STATUS) XOSC 0 Clock Switch

#define	OSCCTRL_STATUS_XOSCCKSW0 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW0_Pos)

#define	OSCCTRL_STATUS_XOSCCKSW1_Pos 5
	(OSCCTRL_STATUS) XOSC 1 Clock Switch

#define	OSCCTRL_STATUS_XOSCCKSW1 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW1_Pos)

#define	OSCCTRL_STATUS_XOSCCKSW_Pos 4
	(OSCCTRL_STATUS) XOSC x Clock Switch

#define	OSCCTRL_STATUS_XOSCCKSW_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCCKSW_Pos)

#define	OSCCTRL_STATUS_XOSCCKSW(value) (OSCCTRL_STATUS_XOSCCKSW_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW_Pos))

#define	OSCCTRL_STATUS_DFLLRDY_Pos 8
	(OSCCTRL_STATUS) DFLL Ready

#define	OSCCTRL_STATUS_DFLLRDY (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos)

#define	OSCCTRL_STATUS_DFLLOOB_Pos 9
	(OSCCTRL_STATUS) DFLL Out Of Bounds

#define	OSCCTRL_STATUS_DFLLOOB (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos)

#define	OSCCTRL_STATUS_DFLLLCKF_Pos 10
	(OSCCTRL_STATUS) DFLL Lock Fine

#define	OSCCTRL_STATUS_DFLLLCKF (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos)

#define	OSCCTRL_STATUS_DFLLLCKC_Pos 11
	(OSCCTRL_STATUS) DFLL Lock Coarse

#define	OSCCTRL_STATUS_DFLLLCKC (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos)

#define	OSCCTRL_STATUS_DFLLRCS_Pos 12
	(OSCCTRL_STATUS) DFLL Reference Clock Stopped

#define	OSCCTRL_STATUS_DFLLRCS (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos)

#define	OSCCTRL_STATUS_DPLL0LCKR_Pos 16
	(OSCCTRL_STATUS) DPLL0 Lock Rise

#define	OSCCTRL_STATUS_DPLL0LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKR_Pos)

#define	OSCCTRL_STATUS_DPLL0LCKF_Pos 17
	(OSCCTRL_STATUS) DPLL0 Lock Fall

#define	OSCCTRL_STATUS_DPLL0LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKF_Pos)

#define	OSCCTRL_STATUS_DPLL0TO_Pos 18
	(OSCCTRL_STATUS) DPLL0 Timeout

#define	OSCCTRL_STATUS_DPLL0TO (_U_(0x1) << OSCCTRL_STATUS_DPLL0TO_Pos)

#define	OSCCTRL_STATUS_DPLL0LDRTO_Pos 19
	(OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete

#define	OSCCTRL_STATUS_DPLL0LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL0LDRTO_Pos)

#define	OSCCTRL_STATUS_DPLL1LCKR_Pos 24
	(OSCCTRL_STATUS) DPLL1 Lock Rise

#define	OSCCTRL_STATUS_DPLL1LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKR_Pos)

#define	OSCCTRL_STATUS_DPLL1LCKF_Pos 25
	(OSCCTRL_STATUS) DPLL1 Lock Fall

#define	OSCCTRL_STATUS_DPLL1LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKF_Pos)

#define	OSCCTRL_STATUS_DPLL1TO_Pos 26
	(OSCCTRL_STATUS) DPLL1 Timeout

#define	OSCCTRL_STATUS_DPLL1TO (_U_(0x1) << OSCCTRL_STATUS_DPLL1TO_Pos)

#define	OSCCTRL_STATUS_DPLL1LDRTO_Pos 27
	(OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete

#define	OSCCTRL_STATUS_DPLL1LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL1LDRTO_Pos)

#define	OSCCTRL_STATUS_MASK _U_(0x0F0F1F3F)
	(OSCCTRL_STATUS) MASK Register

#define	OSCCTRL_XOSCCTRL_OFFSET 0x14
	(OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator Control

#define	OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x00000080)
	(OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator Control

#define	OSCCTRL_XOSCCTRL_ENABLE_Pos 1
	(OSCCTRL_XOSCCTRL) Oscillator Enable

#define	OSCCTRL_XOSCCTRL_ENABLE (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos)

#define	OSCCTRL_XOSCCTRL_XTALEN_Pos 2
	(OSCCTRL_XOSCCTRL) Crystal Oscillator Enable

#define	OSCCTRL_XOSCCTRL_XTALEN (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos)

#define	OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6
	(OSCCTRL_XOSCCTRL) Run in Standby

#define	OSCCTRL_XOSCCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)

#define	OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7
	(OSCCTRL_XOSCCTRL) On Demand Control

#define	OSCCTRL_XOSCCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos)

#define	OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos 8
	(OSCCTRL_XOSCCTRL) Low Buffer Gain Enable

#define	OSCCTRL_XOSCCTRL_LOWBUFGAIN (_U_(0x1) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)

#define	OSCCTRL_XOSCCTRL_IPTAT_Pos 9
	(OSCCTRL_XOSCCTRL) Oscillator Current Reference

#define	OSCCTRL_XOSCCTRL_IPTAT_Msk (_U_(0x3) << OSCCTRL_XOSCCTRL_IPTAT_Pos)

#define	OSCCTRL_XOSCCTRL_IPTAT(value) (OSCCTRL_XOSCCTRL_IPTAT_Msk & ((value) << OSCCTRL_XOSCCTRL_IPTAT_Pos))

#define	OSCCTRL_XOSCCTRL_IMULT_Pos 11
	(OSCCTRL_XOSCCTRL) Oscillator Current Multiplier

#define	OSCCTRL_XOSCCTRL_IMULT_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_IMULT_Pos)

#define	OSCCTRL_XOSCCTRL_IMULT(value) (OSCCTRL_XOSCCTRL_IMULT_Msk & ((value) << OSCCTRL_XOSCCTRL_IMULT_Pos))

#define	OSCCTRL_XOSCCTRL_ENALC_Pos 15
	(OSCCTRL_XOSCCTRL) Automatic Loop Control Enable

#define	OSCCTRL_XOSCCTRL_ENALC (_U_(0x1) << OSCCTRL_XOSCCTRL_ENALC_Pos)

#define	OSCCTRL_XOSCCTRL_CFDEN_Pos 16
	(OSCCTRL_XOSCCTRL) Clock Failure Detector Enable

#define	OSCCTRL_XOSCCTRL_CFDEN (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos)

#define	OSCCTRL_XOSCCTRL_SWBEN_Pos 17
	(OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable

#define	OSCCTRL_XOSCCTRL_SWBEN (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos)

#define	OSCCTRL_XOSCCTRL_STARTUP_Pos 20
	(OSCCTRL_XOSCCTRL) Start-Up Time

#define	OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos)

#define	OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))

#define	OSCCTRL_XOSCCTRL_CFDPRESC_Pos 24
	(OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler

#define	OSCCTRL_XOSCCTRL_CFDPRESC_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos)

#define	OSCCTRL_XOSCCTRL_CFDPRESC(value) (OSCCTRL_XOSCCTRL_CFDPRESC_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos))

#define	OSCCTRL_XOSCCTRL_MASK _U_(0x0FF3FFC6)
	(OSCCTRL_XOSCCTRL) MASK Register

#define	OSCCTRL_DFLLCTRLA_OFFSET 0x1C
	(OSCCTRL_DFLLCTRLA offset) DFLL48M Control A

#define	OSCCTRL_DFLLCTRLA_RESETVALUE _U_(0x82)
	(OSCCTRL_DFLLCTRLA reset_value) DFLL48M Control A

#define	OSCCTRL_DFLLCTRLA_ENABLE_Pos 1
	(OSCCTRL_DFLLCTRLA) DFLL Enable

#define	OSCCTRL_DFLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos)

#define	OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos 6
	(OSCCTRL_DFLLCTRLA) Run in Standby

#define	OSCCTRL_DFLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos)

#define	OSCCTRL_DFLLCTRLA_ONDEMAND_Pos 7
	(OSCCTRL_DFLLCTRLA) On Demand Control

#define	OSCCTRL_DFLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos)

#define	OSCCTRL_DFLLCTRLA_MASK _U_(0xC2)
	(OSCCTRL_DFLLCTRLA) MASK Register

#define	OSCCTRL_DFLLCTRLB_OFFSET 0x20
	(OSCCTRL_DFLLCTRLB offset) DFLL48M Control B

#define	OSCCTRL_DFLLCTRLB_RESETVALUE _U_(0x00)
	(OSCCTRL_DFLLCTRLB reset_value) DFLL48M Control B

#define	OSCCTRL_DFLLCTRLB_MODE_Pos 0
	(OSCCTRL_DFLLCTRLB) Operating Mode Selection

#define	OSCCTRL_DFLLCTRLB_MODE (_U_(0x1) << OSCCTRL_DFLLCTRLB_MODE_Pos)

#define	OSCCTRL_DFLLCTRLB_STABLE_Pos 1
	(OSCCTRL_DFLLCTRLB) Stable DFLL Frequency

#define	OSCCTRL_DFLLCTRLB_STABLE (_U_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos)

#define	OSCCTRL_DFLLCTRLB_LLAW_Pos 2
	(OSCCTRL_DFLLCTRLB) Lose Lock After Wake

#define	OSCCTRL_DFLLCTRLB_LLAW (_U_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos)

#define	OSCCTRL_DFLLCTRLB_USBCRM_Pos 3
	(OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode

#define	OSCCTRL_DFLLCTRLB_USBCRM (_U_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos)

#define	OSCCTRL_DFLLCTRLB_CCDIS_Pos 4
	(OSCCTRL_DFLLCTRLB) Chill Cycle Disable

#define	OSCCTRL_DFLLCTRLB_CCDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos)

#define	OSCCTRL_DFLLCTRLB_QLDIS_Pos 5
	(OSCCTRL_DFLLCTRLB) Quick Lock Disable

#define	OSCCTRL_DFLLCTRLB_QLDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos)

#define	OSCCTRL_DFLLCTRLB_BPLCKC_Pos 6
	(OSCCTRL_DFLLCTRLB) Bypass Coarse Lock

#define	OSCCTRL_DFLLCTRLB_BPLCKC (_U_(0x1) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)

#define	OSCCTRL_DFLLCTRLB_WAITLOCK_Pos 7
	(OSCCTRL_DFLLCTRLB) Wait Lock

#define	OSCCTRL_DFLLCTRLB_WAITLOCK (_U_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos)

#define	OSCCTRL_DFLLCTRLB_MASK _U_(0xFF)
	(OSCCTRL_DFLLCTRLB) MASK Register

#define	OSCCTRL_DFLLVAL_OFFSET 0x24
	(OSCCTRL_DFLLVAL offset) DFLL48M Value

#define	OSCCTRL_DFLLVAL_RESETVALUE _U_(0x00000000)
	(OSCCTRL_DFLLVAL reset_value) DFLL48M Value

#define	OSCCTRL_DFLLVAL_FINE_Pos 0
	(OSCCTRL_DFLLVAL) Fine Value

#define	OSCCTRL_DFLLVAL_FINE_Msk (_U_(0xFF) << OSCCTRL_DFLLVAL_FINE_Pos)

#define	OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))

#define	OSCCTRL_DFLLVAL_COARSE_Pos 10
	(OSCCTRL_DFLLVAL) Coarse Value

#define	OSCCTRL_DFLLVAL_COARSE_Msk (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos)

#define	OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))

#define	OSCCTRL_DFLLVAL_DIFF_Pos 16
	(OSCCTRL_DFLLVAL) Multiplication Ratio Difference

#define	OSCCTRL_DFLLVAL_DIFF_Msk (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos)

#define	OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))

#define	OSCCTRL_DFLLVAL_MASK _U_(0xFFFFFCFF)
	(OSCCTRL_DFLLVAL) MASK Register

#define	OSCCTRL_DFLLMUL_OFFSET 0x28
	(OSCCTRL_DFLLMUL offset) DFLL48M Multiplier

#define	OSCCTRL_DFLLMUL_RESETVALUE _U_(0x00000000)
	(OSCCTRL_DFLLMUL reset_value) DFLL48M Multiplier

#define	OSCCTRL_DFLLMUL_MUL_Pos 0
	(OSCCTRL_DFLLMUL) DFLL Multiply Factor

#define	OSCCTRL_DFLLMUL_MUL_Msk (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos)

#define	OSCCTRL_DFLLMUL_MUL(value) (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))

#define	OSCCTRL_DFLLMUL_FSTEP_Pos 16
	(OSCCTRL_DFLLMUL) Fine Maximum Step

#define	OSCCTRL_DFLLMUL_FSTEP_Msk (_U_(0xFF) << OSCCTRL_DFLLMUL_FSTEP_Pos)

#define	OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))

#define	OSCCTRL_DFLLMUL_CSTEP_Pos 26
	(OSCCTRL_DFLLMUL) Coarse Maximum Step

#define	OSCCTRL_DFLLMUL_CSTEP_Msk (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos)

#define	OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))

#define	OSCCTRL_DFLLMUL_MASK _U_(0xFCFFFFFF)
	(OSCCTRL_DFLLMUL) MASK Register

#define	OSCCTRL_DFLLSYNC_OFFSET 0x2C
	(OSCCTRL_DFLLSYNC offset) DFLL48M Synchronization

#define	OSCCTRL_DFLLSYNC_RESETVALUE _U_(0x00)
	(OSCCTRL_DFLLSYNC reset_value) DFLL48M Synchronization

#define	OSCCTRL_DFLLSYNC_ENABLE_Pos 1
	(OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy

#define	OSCCTRL_DFLLSYNC_ENABLE (_U_(0x1) << OSCCTRL_DFLLSYNC_ENABLE_Pos)

#define	OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos 2
	(OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy

#define	OSCCTRL_DFLLSYNC_DFLLCTRLB (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos)

#define	OSCCTRL_DFLLSYNC_DFLLVAL_Pos 3
	(OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy

#define	OSCCTRL_DFLLSYNC_DFLLVAL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos)

#define	OSCCTRL_DFLLSYNC_DFLLMUL_Pos 4
	(OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy

#define	OSCCTRL_DFLLSYNC_DFLLMUL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos)

#define	OSCCTRL_DFLLSYNC_MASK _U_(0x1E)
	(OSCCTRL_DFLLSYNC) MASK Register

#define	OSCCTRL_DPLLCTRLA_OFFSET 0x30
	(OSCCTRL_DPLLCTRLA offset) DPLL Control A

#define	OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80)
	(OSCCTRL_DPLLCTRLA reset_value) DPLL Control A

#define	OSCCTRL_DPLLCTRLA_ENABLE_Pos 1
	(OSCCTRL_DPLLCTRLA) DPLL Enable

#define	OSCCTRL_DPLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos)

#define	OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6
	(OSCCTRL_DPLLCTRLA) Run in Standby

#define	OSCCTRL_DPLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)

#define	OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7
	(OSCCTRL_DPLLCTRLA) On Demand Control

#define	OSCCTRL_DPLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos)

#define	OSCCTRL_DPLLCTRLA_MASK _U_(0xC2)
	(OSCCTRL_DPLLCTRLA) MASK Register

#define	OSCCTRL_DPLLRATIO_OFFSET 0x34
	(OSCCTRL_DPLLRATIO offset) DPLL Ratio Control

#define	OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00000000)
	(OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control

#define	OSCCTRL_DPLLRATIO_LDR_Pos 0
	(OSCCTRL_DPLLRATIO) Loop Divider Ratio

#define	OSCCTRL_DPLLRATIO_LDR_Msk (_U_(0x1FFF) << OSCCTRL_DPLLRATIO_LDR_Pos)

#define	OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))

#define	OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16
	(OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part

#define	OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0x1F) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)

#define	OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))

#define	OSCCTRL_DPLLRATIO_MASK _U_(0x001F1FFF)
	(OSCCTRL_DPLLRATIO) MASK Register

#define	OSCCTRL_DPLLCTRLB_OFFSET 0x38
	(OSCCTRL_DPLLCTRLB offset) DPLL Control B

#define	OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x00000020)
	(OSCCTRL_DPLLCTRLB reset_value) DPLL Control B

#define	OSCCTRL_DPLLCTRLB_FILTER_Pos 0
	(OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection

#define	OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0xF) << OSCCTRL_DPLLCTRLB_FILTER_Pos)

#define	OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))

#define	OSCCTRL_DPLLCTRLB_WUF_Pos 4
	(OSCCTRL_DPLLCTRLB) Wake Up Fast

#define	OSCCTRL_DPLLCTRLB_WUF (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos)

#define	OSCCTRL_DPLLCTRLB_REFCLK_Pos 5
	(OSCCTRL_DPLLCTRLB) Reference Clock Selection

#define	OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)

#define	OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))

#define	OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val _U_(0x0)
	(OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference

#define	OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val _U_(0x1)
	(OSCCTRL_DPLLCTRLB) XOSC32K clock reference

#define	OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val _U_(0x2)
	(OSCCTRL_DPLLCTRLB) XOSC0 clock reference

#define	OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val _U_(0x3)
	(OSCCTRL_DPLLCTRLB) XOSC1 clock reference

#define	OSCCTRL_DPLLCTRLB_REFCLK_GCLK (OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)

#define	OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)

#define	OSCCTRL_DPLLCTRLB_REFCLK_XOSC0 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)

#define	OSCCTRL_DPLLCTRLB_REFCLK_XOSC1 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)

#define	OSCCTRL_DPLLCTRLB_LTIME_Pos 8
	(OSCCTRL_DPLLCTRLB) Lock Time

#define	OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos)

#define	OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))

#define	OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _U_(0x0)
	(OSCCTRL_DPLLCTRLB) No time-out. Automatic lock

#define	OSCCTRL_DPLLCTRLB_LTIME_800US_Val _U_(0x4)
	(OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us

#define	OSCCTRL_DPLLCTRLB_LTIME_900US_Val _U_(0x5)
	(OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us

#define	OSCCTRL_DPLLCTRLB_LTIME_1MS_Val _U_(0x6)
	(OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms

#define	OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val _U_(0x7)
	(OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms

#define	OSCCTRL_DPLLCTRLB_LTIME_DEFAULT (OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)

#define	OSCCTRL_DPLLCTRLB_LTIME_800US (OSCCTRL_DPLLCTRLB_LTIME_800US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)

#define	OSCCTRL_DPLLCTRLB_LTIME_900US (OSCCTRL_DPLLCTRLB_LTIME_900US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)

#define	OSCCTRL_DPLLCTRLB_LTIME_1MS (OSCCTRL_DPLLCTRLB_LTIME_1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)

#define	OSCCTRL_DPLLCTRLB_LTIME_1P1MS (OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)

#define	OSCCTRL_DPLLCTRLB_LBYPASS_Pos 11
	(OSCCTRL_DPLLCTRLB) Lock Bypass

#define	OSCCTRL_DPLLCTRLB_LBYPASS (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos)

#define	OSCCTRL_DPLLCTRLB_DCOFILTER_Pos 12
	(OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection

#define	OSCCTRL_DPLLCTRLB_DCOFILTER_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos)

#define	OSCCTRL_DPLLCTRLB_DCOFILTER(value) (OSCCTRL_DPLLCTRLB_DCOFILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos))

#define	OSCCTRL_DPLLCTRLB_DCOEN_Pos 15
	(OSCCTRL_DPLLCTRLB) DCO Filter Enable

#define	OSCCTRL_DPLLCTRLB_DCOEN (_U_(0x1) << OSCCTRL_DPLLCTRLB_DCOEN_Pos)

#define	OSCCTRL_DPLLCTRLB_DIV_Pos 16
	(OSCCTRL_DPLLCTRLB) Clock Divider

#define	OSCCTRL_DPLLCTRLB_DIV_Msk (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos)

#define	OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))

#define	OSCCTRL_DPLLCTRLB_MASK _U_(0x07FFFFFF)
	(OSCCTRL_DPLLCTRLB) MASK Register

#define	OSCCTRL_DPLLSYNCBUSY_OFFSET 0x3C
	(OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy

#define	OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00000000)
	(OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy

#define	OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1
	(OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status

#define	OSCCTRL_DPLLSYNCBUSY_ENABLE (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos)

#define	OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2
	(OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status

#define	OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos)

#define	OSCCTRL_DPLLSYNCBUSY_MASK _U_(0x00000006)
	(OSCCTRL_DPLLSYNCBUSY) MASK Register

#define	OSCCTRL_DPLLSTATUS_OFFSET 0x40
	(OSCCTRL_DPLLSTATUS offset) DPLL Status

#define	OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00000000)
	(OSCCTRL_DPLLSTATUS reset_value) DPLL Status

#define	OSCCTRL_DPLLSTATUS_LOCK_Pos 0
	(OSCCTRL_DPLLSTATUS) DPLL Lock Status

#define	OSCCTRL_DPLLSTATUS_LOCK (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos)

#define	OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1
	(OSCCTRL_DPLLSTATUS) DPLL Clock Ready

#define	OSCCTRL_DPLLSTATUS_CLKRDY (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos)

#define	OSCCTRL_DPLLSTATUS_MASK _U_(0x00000003)
	(OSCCTRL_DPLLSTATUS) MASK Register

Detailed Description

Component description for OSCCTRL.

\asf_license_start

Definition in file oscctrl.h.

Data Structures

Macros

Detailed Description