Component description for OSC32KCTRL. More...

Data Structures
union	OSC32KCTRL_INTENCLR_Type

union	OSC32KCTRL_INTENSET_Type

union	OSC32KCTRL_INTFLAG_Type

union	OSC32KCTRL_STATUS_Type

union	OSC32KCTRL_RTCCTRL_Type

union	OSC32KCTRL_XOSC32K_Type

union	OSC32KCTRL_CFDCTRL_Type

union	OSC32KCTRL_EVCTRL_Type

union	OSC32KCTRL_OSCULP32K_Type

struct	Osc32kctrl
	OSC32KCTRL hardware registers. More...

Macros
#define	OSC32KCTRL_U2400

#define	REV_OSC32KCTRL 0x100

#define	OSC32KCTRL_INTENCLR_OFFSET 0x00
	(OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear

#define	OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000)
	(OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear

#define	OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0
	(OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable

#define	OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)

#define	OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos 2
	(OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable

#define	OSC32KCTRL_INTENCLR_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos)

#define	OSC32KCTRL_INTENCLR_MASK _U_(0x00000005)
	(OSC32KCTRL_INTENCLR) MASK Register

#define	OSC32KCTRL_INTENSET_OFFSET 0x04
	(OSC32KCTRL_INTENSET offset) Interrupt Enable Set

#define	OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000)
	(OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set

#define	OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0
	(OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable

#define	OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)

#define	OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos 2
	(OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable

#define	OSC32KCTRL_INTENSET_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos)

#define	OSC32KCTRL_INTENSET_MASK _U_(0x00000005)
	(OSC32KCTRL_INTENSET) MASK Register

#define	OSC32KCTRL_INTFLAG_OFFSET 0x08
	(OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear

#define	OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000)
	(OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear

#define	OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0
	(OSC32KCTRL_INTFLAG) XOSC32K Ready

#define	OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)

#define	OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos 2
	(OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector

#define	OSC32KCTRL_INTFLAG_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos)

#define	OSC32KCTRL_INTFLAG_MASK _U_(0x00000005)
	(OSC32KCTRL_INTFLAG) MASK Register

#define	OSC32KCTRL_STATUS_OFFSET 0x0C
	(OSC32KCTRL_STATUS offset) Power and Clocks Status

#define	OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000)
	(OSC32KCTRL_STATUS reset_value) Power and Clocks Status

#define	OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0
	(OSC32KCTRL_STATUS) XOSC32K Ready

#define	OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)

#define	OSC32KCTRL_STATUS_XOSC32KFAIL_Pos 2
	(OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector

#define	OSC32KCTRL_STATUS_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos)

#define	OSC32KCTRL_STATUS_XOSC32KSW_Pos 3
	(OSC32KCTRL_STATUS) XOSC32K Clock switch

#define	OSC32KCTRL_STATUS_XOSC32KSW (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)

#define	OSC32KCTRL_STATUS_MASK _U_(0x0000000D)
	(OSC32KCTRL_STATUS) MASK Register

#define	OSC32KCTRL_RTCCTRL_OFFSET 0x10
	(OSC32KCTRL_RTCCTRL offset) RTC Clock Selection

#define	OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00)
	(OSC32KCTRL_RTCCTRL reset_value) RTC Clock Selection

#define	OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0
	(OSC32KCTRL_RTCCTRL) RTC Clock Selection

#define	OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)

#define	OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))

#define	OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0)
	(OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator

#define	OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1)
	(OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator

#define	OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4)
	(OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator

#define	OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5)
	(OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator

#define	OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)

#define	OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)

#define	OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)

#define	OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)

#define	OSC32KCTRL_RTCCTRL_MASK _U_(0x07)
	(OSC32KCTRL_RTCCTRL) MASK Register

#define	OSC32KCTRL_XOSC32K_OFFSET 0x14
	(OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control

#define	OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x2080)
	(OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control

#define	OSC32KCTRL_XOSC32K_ENABLE_Pos 1
	(OSC32KCTRL_XOSC32K) Oscillator Enable

#define	OSC32KCTRL_XOSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)

#define	OSC32KCTRL_XOSC32K_XTALEN_Pos 2
	(OSC32KCTRL_XOSC32K) Crystal Oscillator Enable

#define	OSC32KCTRL_XOSC32K_XTALEN (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)

#define	OSC32KCTRL_XOSC32K_EN32K_Pos 3
	(OSC32KCTRL_XOSC32K) 32kHz Output Enable

#define	OSC32KCTRL_XOSC32K_EN32K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)

#define	OSC32KCTRL_XOSC32K_EN1K_Pos 4
	(OSC32KCTRL_XOSC32K) 1kHz Output Enable

#define	OSC32KCTRL_XOSC32K_EN1K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)

#define	OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6
	(OSC32KCTRL_XOSC32K) Run in Standby

#define	OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)

#define	OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7
	(OSC32KCTRL_XOSC32K) On Demand Control

#define	OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)

#define	OSC32KCTRL_XOSC32K_STARTUP_Pos 8
	(OSC32KCTRL_XOSC32K) Oscillator Start-Up Time

#define	OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)

#define	OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))

#define	OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12
	(OSC32KCTRL_XOSC32K) Write Lock

#define	OSC32KCTRL_XOSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)

#define	OSC32KCTRL_XOSC32K_CGM_Pos 13
	(OSC32KCTRL_XOSC32K) Control Gain Mode

#define	OSC32KCTRL_XOSC32K_CGM_Msk (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos)

#define	OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos))

#define	OSC32KCTRL_XOSC32K_CGM_XT_Val _U_(0x1)
	(OSC32KCTRL_XOSC32K) Standard mode

#define	OSC32KCTRL_XOSC32K_CGM_HS_Val _U_(0x2)
	(OSC32KCTRL_XOSC32K) High Speed mode

#define	OSC32KCTRL_XOSC32K_CGM_XT (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos)

#define	OSC32KCTRL_XOSC32K_CGM_HS (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos)

#define	OSC32KCTRL_XOSC32K_MASK _U_(0x77DE)
	(OSC32KCTRL_XOSC32K) MASK Register

#define	OSC32KCTRL_CFDCTRL_OFFSET 0x16
	(OSC32KCTRL_CFDCTRL offset) Clock Failure Detector Control

#define	OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00)
	(OSC32KCTRL_CFDCTRL reset_value) Clock Failure Detector Control

#define	OSC32KCTRL_CFDCTRL_CFDEN_Pos 0
	(OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable

#define	OSC32KCTRL_CFDCTRL_CFDEN (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)

#define	OSC32KCTRL_CFDCTRL_SWBACK_Pos 1
	(OSC32KCTRL_CFDCTRL) Clock Switch Back

#define	OSC32KCTRL_CFDCTRL_SWBACK (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)

#define	OSC32KCTRL_CFDCTRL_CFDPRESC_Pos 2
	(OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler

#define	OSC32KCTRL_CFDCTRL_CFDPRESC (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)

#define	OSC32KCTRL_CFDCTRL_MASK _U_(0x07)
	(OSC32KCTRL_CFDCTRL) MASK Register

#define	OSC32KCTRL_EVCTRL_OFFSET 0x17
	(OSC32KCTRL_EVCTRL offset) Event Control

#define	OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00)
	(OSC32KCTRL_EVCTRL reset_value) Event Control

#define	OSC32KCTRL_EVCTRL_CFDEO_Pos 0
	(OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable

#define	OSC32KCTRL_EVCTRL_CFDEO (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)

#define	OSC32KCTRL_EVCTRL_MASK _U_(0x01)
	(OSC32KCTRL_EVCTRL) MASK Register

#define	OSC32KCTRL_OSCULP32K_OFFSET 0x1C
	(OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control

#define	OSC32KCTRL_OSCULP32K_RESETVALUE _U_(0x00000000)
	(OSC32KCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control

#define	OSC32KCTRL_OSCULP32K_EN32K_Pos 1
	(OSC32KCTRL_OSCULP32K) Enable Out 32k

#define	OSC32KCTRL_OSCULP32K_EN32K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos)

#define	OSC32KCTRL_OSCULP32K_EN1K_Pos 2
	(OSC32KCTRL_OSCULP32K) Enable Out 1k

#define	OSC32KCTRL_OSCULP32K_EN1K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos)

#define	OSC32KCTRL_OSCULP32K_CALIB_Pos 8
	(OSC32KCTRL_OSCULP32K) Oscillator Calibration

#define	OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)

#define	OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))

#define	OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15
	(OSC32KCTRL_OSCULP32K) Write Lock

#define	OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)

#define	OSC32KCTRL_OSCULP32K_MASK _U_(0x0000BF06)
	(OSC32KCTRL_OSCULP32K) MASK Register

Detailed Description

Component description for OSC32KCTRL.

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Definition in file osc32kctrl.h.

Data Structures

Macros

Detailed Description