Component description for MCLK. More...

Data Structures
union	MCLK_INTENCLR_Type

union	MCLK_INTENSET_Type

union	MCLK_INTFLAG_Type

union	MCLK_HSDIV_Type

union	MCLK_CPUDIV_Type

union	MCLK_AHBMASK_Type

union	MCLK_APBAMASK_Type

union	MCLK_APBBMASK_Type

union	MCLK_APBCMASK_Type

union	MCLK_APBDMASK_Type

struct	Mclk
	MCLK hardware registers. More...

Macros
#define	MCLK_U2408

#define	REV_MCLK 0x100

#define	MCLK_INTENCLR_OFFSET 0x01
	(MCLK_INTENCLR offset) Interrupt Enable Clear

#define	MCLK_INTENCLR_RESETVALUE _U_(0x00)
	(MCLK_INTENCLR reset_value) Interrupt Enable Clear

#define	MCLK_INTENCLR_CKRDY_Pos 0
	(MCLK_INTENCLR) Clock Ready Interrupt Enable

#define	MCLK_INTENCLR_CKRDY (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)

#define	MCLK_INTENCLR_MASK _U_(0x01)
	(MCLK_INTENCLR) MASK Register

#define	MCLK_INTENSET_OFFSET 0x02
	(MCLK_INTENSET offset) Interrupt Enable Set

#define	MCLK_INTENSET_RESETVALUE _U_(0x00)
	(MCLK_INTENSET reset_value) Interrupt Enable Set

#define	MCLK_INTENSET_CKRDY_Pos 0
	(MCLK_INTENSET) Clock Ready Interrupt Enable

#define	MCLK_INTENSET_CKRDY (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)

#define	MCLK_INTENSET_MASK _U_(0x01)
	(MCLK_INTENSET) MASK Register

#define	MCLK_INTFLAG_OFFSET 0x03
	(MCLK_INTFLAG offset) Interrupt Flag Status and Clear

#define	MCLK_INTFLAG_RESETVALUE _U_(0x01)
	(MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear

#define	MCLK_INTFLAG_CKRDY_Pos 0
	(MCLK_INTFLAG) Clock Ready

#define	MCLK_INTFLAG_CKRDY (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)

#define	MCLK_INTFLAG_MASK _U_(0x01)
	(MCLK_INTFLAG) MASK Register

#define	MCLK_HSDIV_OFFSET 0x04
	(MCLK_HSDIV offset) HS Clock Division

#define	MCLK_HSDIV_RESETVALUE _U_(0x01)
	(MCLK_HSDIV reset_value) HS Clock Division

#define	MCLK_HSDIV_DIV_Pos 0
	(MCLK_HSDIV) CPU Clock Division Factor

#define	MCLK_HSDIV_DIV_Msk (_U_(0xFF) << MCLK_HSDIV_DIV_Pos)

#define	MCLK_HSDIV_DIV(value) (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos))

#define	MCLK_HSDIV_DIV_DIV1_Val _U_(0x1)
	(MCLK_HSDIV) Divide by 1

#define	MCLK_HSDIV_DIV_DIV1 (MCLK_HSDIV_DIV_DIV1_Val << MCLK_HSDIV_DIV_Pos)

#define	MCLK_HSDIV_MASK _U_(0xFF)
	(MCLK_HSDIV) MASK Register

#define	MCLK_CPUDIV_OFFSET 0x05
	(MCLK_CPUDIV offset) CPU Clock Division

#define	MCLK_CPUDIV_RESETVALUE _U_(0x01)
	(MCLK_CPUDIV reset_value) CPU Clock Division

#define	MCLK_CPUDIV_DIV_Pos 0
	(MCLK_CPUDIV) Low-Power Clock Division Factor

#define	MCLK_CPUDIV_DIV_Msk (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos)

#define	MCLK_CPUDIV_DIV(value) (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos))

#define	MCLK_CPUDIV_DIV_DIV1_Val _U_(0x1)
	(MCLK_CPUDIV) Divide by 1

#define	MCLK_CPUDIV_DIV_DIV2_Val _U_(0x2)
	(MCLK_CPUDIV) Divide by 2

#define	MCLK_CPUDIV_DIV_DIV4_Val _U_(0x4)
	(MCLK_CPUDIV) Divide by 4

#define	MCLK_CPUDIV_DIV_DIV8_Val _U_(0x8)
	(MCLK_CPUDIV) Divide by 8

#define	MCLK_CPUDIV_DIV_DIV16_Val _U_(0x10)
	(MCLK_CPUDIV) Divide by 16

#define	MCLK_CPUDIV_DIV_DIV32_Val _U_(0x20)
	(MCLK_CPUDIV) Divide by 32

#define	MCLK_CPUDIV_DIV_DIV64_Val _U_(0x40)
	(MCLK_CPUDIV) Divide by 64

#define	MCLK_CPUDIV_DIV_DIV128_Val _U_(0x80)
	(MCLK_CPUDIV) Divide by 128

#define	MCLK_CPUDIV_DIV_DIV1 (MCLK_CPUDIV_DIV_DIV1_Val << MCLK_CPUDIV_DIV_Pos)

#define	MCLK_CPUDIV_DIV_DIV2 (MCLK_CPUDIV_DIV_DIV2_Val << MCLK_CPUDIV_DIV_Pos)

#define	MCLK_CPUDIV_DIV_DIV4 (MCLK_CPUDIV_DIV_DIV4_Val << MCLK_CPUDIV_DIV_Pos)

#define	MCLK_CPUDIV_DIV_DIV8 (MCLK_CPUDIV_DIV_DIV8_Val << MCLK_CPUDIV_DIV_Pos)

#define	MCLK_CPUDIV_DIV_DIV16 (MCLK_CPUDIV_DIV_DIV16_Val << MCLK_CPUDIV_DIV_Pos)

#define	MCLK_CPUDIV_DIV_DIV32 (MCLK_CPUDIV_DIV_DIV32_Val << MCLK_CPUDIV_DIV_Pos)

#define	MCLK_CPUDIV_DIV_DIV64 (MCLK_CPUDIV_DIV_DIV64_Val << MCLK_CPUDIV_DIV_Pos)

#define	MCLK_CPUDIV_DIV_DIV128 (MCLK_CPUDIV_DIV_DIV128_Val << MCLK_CPUDIV_DIV_Pos)

#define	MCLK_CPUDIV_MASK _U_(0xFF)
	(MCLK_CPUDIV) MASK Register

#define	MCLK_AHBMASK_OFFSET 0x10
	(MCLK_AHBMASK offset) AHB Mask

#define	MCLK_AHBMASK_RESETVALUE _U_(0x00FFFFFF)
	(MCLK_AHBMASK reset_value) AHB Mask

#define	MCLK_AHBMASK_HPB0_Pos 0
	(MCLK_AHBMASK) HPB0 AHB Clock Mask

#define	MCLK_AHBMASK_HPB0 (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)

#define	MCLK_AHBMASK_HPB1_Pos 1
	(MCLK_AHBMASK) HPB1 AHB Clock Mask

#define	MCLK_AHBMASK_HPB1 (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)

#define	MCLK_AHBMASK_HPB2_Pos 2
	(MCLK_AHBMASK) HPB2 AHB Clock Mask

#define	MCLK_AHBMASK_HPB2 (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)

#define	MCLK_AHBMASK_HPB3_Pos 3
	(MCLK_AHBMASK) HPB3 AHB Clock Mask

#define	MCLK_AHBMASK_HPB3 (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos)

#define	MCLK_AHBMASK_DSU_Pos 4
	(MCLK_AHBMASK) DSU AHB Clock Mask

#define	MCLK_AHBMASK_DSU (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)

#define	MCLK_AHBMASK_HMATRIX_Pos 5
	(MCLK_AHBMASK) HMATRIX AHB Clock Mask

#define	MCLK_AHBMASK_HMATRIX (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos)

#define	MCLK_AHBMASK_NVMCTRL_Pos 6
	(MCLK_AHBMASK) NVMCTRL AHB Clock Mask

#define	MCLK_AHBMASK_NVMCTRL (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)

#define	MCLK_AHBMASK_HSRAM_Pos 7
	(MCLK_AHBMASK) HSRAM AHB Clock Mask

#define	MCLK_AHBMASK_HSRAM (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos)

#define	MCLK_AHBMASK_CMCC_Pos 8
	(MCLK_AHBMASK) CMCC AHB Clock Mask

#define	MCLK_AHBMASK_CMCC (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos)

#define	MCLK_AHBMASK_DMAC_Pos 9
	(MCLK_AHBMASK) DMAC AHB Clock Mask

#define	MCLK_AHBMASK_DMAC (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)

#define	MCLK_AHBMASK_USB_Pos 10
	(MCLK_AHBMASK) USB AHB Clock Mask

#define	MCLK_AHBMASK_USB (_U_(0x1) << MCLK_AHBMASK_USB_Pos)

#define	MCLK_AHBMASK_BKUPRAM_Pos 11
	(MCLK_AHBMASK) BKUPRAM AHB Clock Mask

#define	MCLK_AHBMASK_BKUPRAM (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos)

#define	MCLK_AHBMASK_PAC_Pos 12
	(MCLK_AHBMASK) PAC AHB Clock Mask

#define	MCLK_AHBMASK_PAC (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)

#define	MCLK_AHBMASK_QSPI_Pos 13
	(MCLK_AHBMASK) QSPI AHB Clock Mask

#define	MCLK_AHBMASK_QSPI (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos)

#define	MCLK_AHBMASK_GMAC_Pos 14
	(MCLK_AHBMASK) GMAC AHB Clock Mask

#define	MCLK_AHBMASK_GMAC (_U_(0x1) << MCLK_AHBMASK_GMAC_Pos)

#define	MCLK_AHBMASK_SDHC0_Pos 15
	(MCLK_AHBMASK) SDHC0 AHB Clock Mask

#define	MCLK_AHBMASK_SDHC0 (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos)

#define	MCLK_AHBMASK_SDHC1_Pos 16
	(MCLK_AHBMASK) SDHC1 AHB Clock Mask

#define	MCLK_AHBMASK_SDHC1 (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos)

#define	MCLK_AHBMASK_CAN0_Pos 17
	(MCLK_AHBMASK) CAN0 AHB Clock Mask

#define	MCLK_AHBMASK_CAN0 (_U_(0x1) << MCLK_AHBMASK_CAN0_Pos)

#define	MCLK_AHBMASK_CAN1_Pos 18
	(MCLK_AHBMASK) CAN1 AHB Clock Mask

#define	MCLK_AHBMASK_CAN1 (_U_(0x1) << MCLK_AHBMASK_CAN1_Pos)

#define	MCLK_AHBMASK_ICM_Pos 19
	(MCLK_AHBMASK) ICM AHB Clock Mask

#define	MCLK_AHBMASK_ICM (_U_(0x1) << MCLK_AHBMASK_ICM_Pos)

#define	MCLK_AHBMASK_PUKCC_Pos 20
	(MCLK_AHBMASK) PUKCC AHB Clock Mask

#define	MCLK_AHBMASK_PUKCC (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos)

#define	MCLK_AHBMASK_QSPI_2X_Pos 21
	(MCLK_AHBMASK) QSPI_2X AHB Clock Mask

#define	MCLK_AHBMASK_QSPI_2X (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos)

#define	MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos 22
	(MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask

#define	MCLK_AHBMASK_NVMCTRL_SMEEPROM (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos)

#define	MCLK_AHBMASK_NVMCTRL_CACHE_Pos 23
	(MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask

#define	MCLK_AHBMASK_NVMCTRL_CACHE (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos)

#define	MCLK_AHBMASK_MASK _U_(0x00FFFFFF)
	(MCLK_AHBMASK) MASK Register

#define	MCLK_APBAMASK_OFFSET 0x14
	(MCLK_APBAMASK offset) APBA Mask

#define	MCLK_APBAMASK_RESETVALUE _U_(0x000007FF)
	(MCLK_APBAMASK reset_value) APBA Mask

#define	MCLK_APBAMASK_PAC_Pos 0
	(MCLK_APBAMASK) PAC APB Clock Enable

#define	MCLK_APBAMASK_PAC (_U_(0x1) << MCLK_APBAMASK_PAC_Pos)

#define	MCLK_APBAMASK_PM_Pos 1
	(MCLK_APBAMASK) PM APB Clock Enable

#define	MCLK_APBAMASK_PM (_U_(0x1) << MCLK_APBAMASK_PM_Pos)

#define	MCLK_APBAMASK_MCLK_Pos 2
	(MCLK_APBAMASK) MCLK APB Clock Enable

#define	MCLK_APBAMASK_MCLK (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)

#define	MCLK_APBAMASK_RSTC_Pos 3
	(MCLK_APBAMASK) RSTC APB Clock Enable

#define	MCLK_APBAMASK_RSTC (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)

#define	MCLK_APBAMASK_OSCCTRL_Pos 4
	(MCLK_APBAMASK) OSCCTRL APB Clock Enable

#define	MCLK_APBAMASK_OSCCTRL (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)

#define	MCLK_APBAMASK_OSC32KCTRL_Pos 5
	(MCLK_APBAMASK) OSC32KCTRL APB Clock Enable

#define	MCLK_APBAMASK_OSC32KCTRL (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)

#define	MCLK_APBAMASK_SUPC_Pos 6
	(MCLK_APBAMASK) SUPC APB Clock Enable

#define	MCLK_APBAMASK_SUPC (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)

#define	MCLK_APBAMASK_GCLK_Pos 7
	(MCLK_APBAMASK) GCLK APB Clock Enable

#define	MCLK_APBAMASK_GCLK (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)

#define	MCLK_APBAMASK_WDT_Pos 8
	(MCLK_APBAMASK) WDT APB Clock Enable

#define	MCLK_APBAMASK_WDT (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)

#define	MCLK_APBAMASK_RTC_Pos 9
	(MCLK_APBAMASK) RTC APB Clock Enable

#define	MCLK_APBAMASK_RTC (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)

#define	MCLK_APBAMASK_EIC_Pos 10
	(MCLK_APBAMASK) EIC APB Clock Enable

#define	MCLK_APBAMASK_EIC (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)

#define	MCLK_APBAMASK_FREQM_Pos 11
	(MCLK_APBAMASK) FREQM APB Clock Enable

#define	MCLK_APBAMASK_FREQM (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos)

#define	MCLK_APBAMASK_SERCOM0_Pos 12
	(MCLK_APBAMASK) SERCOM0 APB Clock Enable

#define	MCLK_APBAMASK_SERCOM0 (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos)

#define	MCLK_APBAMASK_SERCOM1_Pos 13
	(MCLK_APBAMASK) SERCOM1 APB Clock Enable

#define	MCLK_APBAMASK_SERCOM1 (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos)

#define	MCLK_APBAMASK_TC0_Pos 14
	(MCLK_APBAMASK) TC0 APB Clock Enable

#define	MCLK_APBAMASK_TC0 (_U_(0x1) << MCLK_APBAMASK_TC0_Pos)

#define	MCLK_APBAMASK_TC1_Pos 15
	(MCLK_APBAMASK) TC1 APB Clock Enable

#define	MCLK_APBAMASK_TC1 (_U_(0x1) << MCLK_APBAMASK_TC1_Pos)

#define	MCLK_APBAMASK_MASK _U_(0x0000FFFF)
	(MCLK_APBAMASK) MASK Register

#define	MCLK_APBBMASK_OFFSET 0x18
	(MCLK_APBBMASK offset) APBB Mask

#define	MCLK_APBBMASK_RESETVALUE _U_(0x00018056)
	(MCLK_APBBMASK reset_value) APBB Mask

#define	MCLK_APBBMASK_USB_Pos 0
	(MCLK_APBBMASK) USB APB Clock Enable

#define	MCLK_APBBMASK_USB (_U_(0x1) << MCLK_APBBMASK_USB_Pos)

#define	MCLK_APBBMASK_DSU_Pos 1
	(MCLK_APBBMASK) DSU APB Clock Enable

#define	MCLK_APBBMASK_DSU (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)

#define	MCLK_APBBMASK_NVMCTRL_Pos 2
	(MCLK_APBBMASK) NVMCTRL APB Clock Enable

#define	MCLK_APBBMASK_NVMCTRL (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)

#define	MCLK_APBBMASK_PORT_Pos 4
	(MCLK_APBBMASK) PORT APB Clock Enable

#define	MCLK_APBBMASK_PORT (_U_(0x1) << MCLK_APBBMASK_PORT_Pos)

#define	MCLK_APBBMASK_HMATRIX_Pos 6
	(MCLK_APBBMASK) HMATRIX APB Clock Enable

#define	MCLK_APBBMASK_HMATRIX (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos)

#define	MCLK_APBBMASK_EVSYS_Pos 7
	(MCLK_APBBMASK) EVSYS APB Clock Enable

#define	MCLK_APBBMASK_EVSYS (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos)

#define	MCLK_APBBMASK_SERCOM2_Pos 9
	(MCLK_APBBMASK) SERCOM2 APB Clock Enable

#define	MCLK_APBBMASK_SERCOM2 (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos)

#define	MCLK_APBBMASK_SERCOM3_Pos 10
	(MCLK_APBBMASK) SERCOM3 APB Clock Enable

#define	MCLK_APBBMASK_SERCOM3 (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos)

#define	MCLK_APBBMASK_TCC0_Pos 11
	(MCLK_APBBMASK) TCC0 APB Clock Enable

#define	MCLK_APBBMASK_TCC0 (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos)

#define	MCLK_APBBMASK_TCC1_Pos 12
	(MCLK_APBBMASK) TCC1 APB Clock Enable

#define	MCLK_APBBMASK_TCC1 (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos)

#define	MCLK_APBBMASK_TC2_Pos 13
	(MCLK_APBBMASK) TC2 APB Clock Enable

#define	MCLK_APBBMASK_TC2 (_U_(0x1) << MCLK_APBBMASK_TC2_Pos)

#define	MCLK_APBBMASK_TC3_Pos 14
	(MCLK_APBBMASK) TC3 APB Clock Enable

#define	MCLK_APBBMASK_TC3 (_U_(0x1) << MCLK_APBBMASK_TC3_Pos)

#define	MCLK_APBBMASK_RAMECC_Pos 16
	(MCLK_APBBMASK) RAMECC APB Clock Enable

#define	MCLK_APBBMASK_RAMECC (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos)

#define	MCLK_APBBMASK_MASK _U_(0x00017ED7)
	(MCLK_APBBMASK) MASK Register

#define	MCLK_APBCMASK_OFFSET 0x1C
	(MCLK_APBCMASK offset) APBC Mask

#define	MCLK_APBCMASK_RESETVALUE _U_(0x00002000)
	(MCLK_APBCMASK reset_value) APBC Mask

#define	MCLK_APBCMASK_GMAC_Pos 2
	(MCLK_APBCMASK) GMAC APB Clock Enable

#define	MCLK_APBCMASK_GMAC (_U_(0x1) << MCLK_APBCMASK_GMAC_Pos)

#define	MCLK_APBCMASK_TCC2_Pos 3
	(MCLK_APBCMASK) TCC2 APB Clock Enable

#define	MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)

#define	MCLK_APBCMASK_TCC3_Pos 4
	(MCLK_APBCMASK) TCC3 APB Clock Enable

#define	MCLK_APBCMASK_TCC3 (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos)

#define	MCLK_APBCMASK_TC4_Pos 5
	(MCLK_APBCMASK) TC4 APB Clock Enable

#define	MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)

#define	MCLK_APBCMASK_TC5_Pos 6
	(MCLK_APBCMASK) TC5 APB Clock Enable

#define	MCLK_APBCMASK_TC5 (_U_(0x1) << MCLK_APBCMASK_TC5_Pos)

#define	MCLK_APBCMASK_PDEC_Pos 7
	(MCLK_APBCMASK) PDEC APB Clock Enable

#define	MCLK_APBCMASK_PDEC (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos)

#define	MCLK_APBCMASK_AC_Pos 8
	(MCLK_APBCMASK) AC APB Clock Enable

#define	MCLK_APBCMASK_AC (_U_(0x1) << MCLK_APBCMASK_AC_Pos)

#define	MCLK_APBCMASK_AES_Pos 9
	(MCLK_APBCMASK) AES APB Clock Enable

#define	MCLK_APBCMASK_AES (_U_(0x1) << MCLK_APBCMASK_AES_Pos)

#define	MCLK_APBCMASK_TRNG_Pos 10
	(MCLK_APBCMASK) TRNG APB Clock Enable

#define	MCLK_APBCMASK_TRNG (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos)

#define	MCLK_APBCMASK_ICM_Pos 11
	(MCLK_APBCMASK) ICM APB Clock Enable

#define	MCLK_APBCMASK_ICM (_U_(0x1) << MCLK_APBCMASK_ICM_Pos)

#define	MCLK_APBCMASK_QSPI_Pos 13
	(MCLK_APBCMASK) QSPI APB Clock Enable

#define	MCLK_APBCMASK_QSPI (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos)

#define	MCLK_APBCMASK_CCL_Pos 14
	(MCLK_APBCMASK) CCL APB Clock Enable

#define	MCLK_APBCMASK_CCL (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)

#define	MCLK_APBCMASK_MASK _U_(0x00006FFC)
	(MCLK_APBCMASK) MASK Register

#define	MCLK_APBDMASK_OFFSET 0x20
	(MCLK_APBDMASK offset) APBD Mask

#define	MCLK_APBDMASK_RESETVALUE _U_(0x00000000)
	(MCLK_APBDMASK reset_value) APBD Mask

#define	MCLK_APBDMASK_SERCOM4_Pos 0
	(MCLK_APBDMASK) SERCOM4 APB Clock Enable

#define	MCLK_APBDMASK_SERCOM4 (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos)

#define	MCLK_APBDMASK_SERCOM5_Pos 1
	(MCLK_APBDMASK) SERCOM5 APB Clock Enable

#define	MCLK_APBDMASK_SERCOM5 (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos)

#define	MCLK_APBDMASK_SERCOM6_Pos 2
	(MCLK_APBDMASK) SERCOM6 APB Clock Enable

#define	MCLK_APBDMASK_SERCOM6 (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos)

#define	MCLK_APBDMASK_SERCOM7_Pos 3
	(MCLK_APBDMASK) SERCOM7 APB Clock Enable

#define	MCLK_APBDMASK_SERCOM7 (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos)

#define	MCLK_APBDMASK_TCC4_Pos 4
	(MCLK_APBDMASK) TCC4 APB Clock Enable

#define	MCLK_APBDMASK_TCC4 (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos)

#define	MCLK_APBDMASK_TC6_Pos 5
	(MCLK_APBDMASK) TC6 APB Clock Enable

#define	MCLK_APBDMASK_TC6 (_U_(0x1) << MCLK_APBDMASK_TC6_Pos)

#define	MCLK_APBDMASK_TC7_Pos 6
	(MCLK_APBDMASK) TC7 APB Clock Enable

#define	MCLK_APBDMASK_TC7 (_U_(0x1) << MCLK_APBDMASK_TC7_Pos)

#define	MCLK_APBDMASK_ADC0_Pos 7
	(MCLK_APBDMASK) ADC0 APB Clock Enable

#define	MCLK_APBDMASK_ADC0 (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos)

#define	MCLK_APBDMASK_ADC1_Pos 8
	(MCLK_APBDMASK) ADC1 APB Clock Enable

#define	MCLK_APBDMASK_ADC1 (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos)

#define	MCLK_APBDMASK_DAC_Pos 9
	(MCLK_APBDMASK) DAC APB Clock Enable

#define	MCLK_APBDMASK_DAC (_U_(0x1) << MCLK_APBDMASK_DAC_Pos)

#define	MCLK_APBDMASK_I2S_Pos 10
	(MCLK_APBDMASK) I2S APB Clock Enable

#define	MCLK_APBDMASK_I2S (_U_(0x1) << MCLK_APBDMASK_I2S_Pos)

#define	MCLK_APBDMASK_PCC_Pos 11
	(MCLK_APBDMASK) PCC APB Clock Enable

#define	MCLK_APBDMASK_PCC (_U_(0x1) << MCLK_APBDMASK_PCC_Pos)

#define	MCLK_APBDMASK_MASK _U_(0x00000FFF)
	(MCLK_APBDMASK) MASK Register

Detailed Description

Component description for MCLK.

\asf_license_start

Definition in file mclk.h.

Data Structures

Macros

Detailed Description