Component description for ICM. More...

Data Structures
union	ICM_CFG_Type

union	ICM_CTRL_Type

union	ICM_SR_Type

union	ICM_IER_Type

union	ICM_IDR_Type

union	ICM_IMR_Type

union	ICM_ISR_Type

union	ICM_UASR_Type

union	ICM_DSCR_Type

union	ICM_HASH_Type

union	ICM_UIHVAL_Type

union	ICM_RADDR_Type

union	ICM_RCFG_Type

union	ICM_RCTRL_Type

union	ICM_RNEXT_Type

struct	Icm
	ICM APB hardware registers. More...

struct	IcmDescriptor
	ICM Descriptor SRAM registers. More...

Macros
#define	ICM_U2010

#define	REV_ICM 0x120

#define	ICM_CFG_OFFSET 0x00
	(ICM_CFG offset) Configuration

#define	ICM_CFG_RESETVALUE _U_(0x00000000)
	(ICM_CFG reset_value) Configuration

#define	ICM_CFG_WBDIS_Pos 0
	(ICM_CFG) Write Back Disable

#define	ICM_CFG_WBDIS (_U_(0x1) << ICM_CFG_WBDIS_Pos)

#define	ICM_CFG_EOMDIS_Pos 1
	(ICM_CFG) End of Monitoring Disable

#define	ICM_CFG_EOMDIS (_U_(0x1) << ICM_CFG_EOMDIS_Pos)

#define	ICM_CFG_SLBDIS_Pos 2
	(ICM_CFG) Secondary List Branching Disable

#define	ICM_CFG_SLBDIS (_U_(0x1) << ICM_CFG_SLBDIS_Pos)

#define	ICM_CFG_BBC_Pos 4
	(ICM_CFG) Bus Burden Control

#define	ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos)

#define	ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))

#define	ICM_CFG_ASCD_Pos 8
	(ICM_CFG) Automatic Switch To Compare Digest

#define	ICM_CFG_ASCD (_U_(0x1) << ICM_CFG_ASCD_Pos)

#define	ICM_CFG_DUALBUFF_Pos 9
	(ICM_CFG) Dual Input Buffer

#define	ICM_CFG_DUALBUFF (_U_(0x1) << ICM_CFG_DUALBUFF_Pos)

#define	ICM_CFG_UIHASH_Pos 12
	(ICM_CFG) User Initial Hash Value

#define	ICM_CFG_UIHASH (_U_(0x1) << ICM_CFG_UIHASH_Pos)

#define	ICM_CFG_UALGO_Pos 13
	(ICM_CFG) User SHA Algorithm

#define	ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos)

#define	ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))

#define	ICM_CFG_UALGO_SHA1_Val _U_(0x0)
	(ICM_CFG) SHA1 Algorithm

#define	ICM_CFG_UALGO_SHA256_Val _U_(0x1)
	(ICM_CFG) SHA256 Algorithm

#define	ICM_CFG_UALGO_SHA224_Val _U_(0x4)
	(ICM_CFG) SHA224 Algorithm

#define	ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos)

#define	ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos)

#define	ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos)

#define	ICM_CFG_HAPROT_Pos 16
	(ICM_CFG) Region Hash Area Protection

#define	ICM_CFG_HAPROT_Msk (_U_(0x3F) << ICM_CFG_HAPROT_Pos)

#define	ICM_CFG_HAPROT(value) (ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))

#define	ICM_CFG_DAPROT_Pos 24
	(ICM_CFG) Region Descriptor Area Protection

#define	ICM_CFG_DAPROT_Msk (_U_(0x3F) << ICM_CFG_DAPROT_Pos)

#define	ICM_CFG_DAPROT(value) (ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))

#define	ICM_CFG_MASK _U_(0x3F3FF3F7)
	(ICM_CFG) MASK Register

#define	ICM_CTRL_OFFSET 0x04
	(ICM_CTRL offset) Control

#define	ICM_CTRL_ENABLE_Pos 0
	(ICM_CTRL) ICM Enable

#define	ICM_CTRL_ENABLE (_U_(0x1) << ICM_CTRL_ENABLE_Pos)

#define	ICM_CTRL_DISABLE_Pos 1
	(ICM_CTRL) ICM Disable Register

#define	ICM_CTRL_DISABLE (_U_(0x1) << ICM_CTRL_DISABLE_Pos)

#define	ICM_CTRL_SWRST_Pos 2
	(ICM_CTRL) Software Reset

#define	ICM_CTRL_SWRST (_U_(0x1) << ICM_CTRL_SWRST_Pos)

#define	ICM_CTRL_REHASH_Pos 4
	(ICM_CTRL) Recompute Internal Hash

#define	ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos)

#define	ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))

#define	ICM_CTRL_RMDIS_Pos 8
	(ICM_CTRL) Region Monitoring Disable

#define	ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos)

#define	ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))

#define	ICM_CTRL_RMEN_Pos 12
	(ICM_CTRL) Region Monitoring Enable

#define	ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos)

#define	ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))

#define	ICM_CTRL_MASK _U_(0x0000FFF7)
	(ICM_CTRL) MASK Register

#define	ICM_SR_OFFSET 0x08
	(ICM_SR offset) Status

#define	ICM_SR_RESETVALUE _U_(0x00000000)
	(ICM_SR reset_value) Status

#define	ICM_SR_ENABLE_Pos 0
	(ICM_SR) ICM Controller Enable Register

#define	ICM_SR_ENABLE (_U_(0x1) << ICM_SR_ENABLE_Pos)

#define	ICM_SR_RAWRMDIS_Pos 8
	(ICM_SR) RAW Region Monitoring Disabled Status

#define	ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos)

#define	ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))

#define	ICM_SR_RMDIS_Pos 12
	(ICM_SR) Region Monitoring Disabled Status

#define	ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos)

#define	ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))

#define	ICM_SR_MASK _U_(0x0000FF01)
	(ICM_SR) MASK Register

#define	ICM_IER_OFFSET 0x10
	(ICM_IER offset) Interrupt Enable

#define	ICM_IER_RHC_Pos 0
	(ICM_IER) Region Hash Completed Interrupt Enable

#define	ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos)

#define	ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))

#define	ICM_IER_RDM_Pos 4
	(ICM_IER) Region Digest Mismatch Interrupt Enable

#define	ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos)

#define	ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))

#define	ICM_IER_RBE_Pos 8
	(ICM_IER) Region Bus Error Interrupt Enable

#define	ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos)

#define	ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))

#define	ICM_IER_RWC_Pos 12
	(ICM_IER) Region Wrap Condition detected Interrupt Enable

#define	ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos)

#define	ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))

#define	ICM_IER_REC_Pos 16
	(ICM_IER) Region End bit Condition Detected Interrupt Enable

#define	ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos)

#define	ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))

#define	ICM_IER_RSU_Pos 20
	(ICM_IER) Region Status Updated Interrupt Disable

#define	ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos)

#define	ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))

#define	ICM_IER_URAD_Pos 24
	(ICM_IER) Undefined Register Access Detection Interrupt Enable

#define	ICM_IER_URAD (_U_(0x1) << ICM_IER_URAD_Pos)

#define	ICM_IER_MASK _U_(0x01FFFFFF)
	(ICM_IER) MASK Register

#define	ICM_IDR_OFFSET 0x14
	(ICM_IDR offset) Interrupt Disable

#define	ICM_IDR_RESETVALUE _U_(0x00000000)
	(ICM_IDR reset_value) Interrupt Disable

#define	ICM_IDR_RHC_Pos 0
	(ICM_IDR) Region Hash Completed Interrupt Disable

#define	ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos)

#define	ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))

#define	ICM_IDR_RDM_Pos 4
	(ICM_IDR) Region Digest Mismatch Interrupt Disable

#define	ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos)

#define	ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))

#define	ICM_IDR_RBE_Pos 8
	(ICM_IDR) Region Bus Error Interrupt Disable

#define	ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos)

#define	ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))

#define	ICM_IDR_RWC_Pos 12
	(ICM_IDR) Region Wrap Condition Detected Interrupt Disable

#define	ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos)

#define	ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))

#define	ICM_IDR_REC_Pos 16
	(ICM_IDR) Region End bit Condition detected Interrupt Disable

#define	ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos)

#define	ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))

#define	ICM_IDR_RSU_Pos 20
	(ICM_IDR) Region Status Updated Interrupt Disable

#define	ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos)

#define	ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))

#define	ICM_IDR_URAD_Pos 24
	(ICM_IDR) Undefined Register Access Detection Interrupt Disable

#define	ICM_IDR_URAD (_U_(0x1) << ICM_IDR_URAD_Pos)

#define	ICM_IDR_MASK _U_(0x01FFFFFF)
	(ICM_IDR) MASK Register

#define	ICM_IMR_OFFSET 0x18
	(ICM_IMR offset) Interrupt Mask

#define	ICM_IMR_RESETVALUE _U_(0x00000000)
	(ICM_IMR reset_value) Interrupt Mask

#define	ICM_IMR_RHC_Pos 0
	(ICM_IMR) Region Hash Completed Interrupt Mask

#define	ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos)

#define	ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos))

#define	ICM_IMR_RDM_Pos 4
	(ICM_IMR) Region Digest Mismatch Interrupt Mask

#define	ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos)

#define	ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos))

#define	ICM_IMR_RBE_Pos 8
	(ICM_IMR) Region Bus Error Interrupt Mask

#define	ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos)

#define	ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos))

#define	ICM_IMR_RWC_Pos 12
	(ICM_IMR) Region Wrap Condition Detected Interrupt Mask

#define	ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos)

#define	ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos))

#define	ICM_IMR_REC_Pos 16
	(ICM_IMR) Region End bit Condition Detected Interrupt Mask

#define	ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos)

#define	ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos))

#define	ICM_IMR_RSU_Pos 20
	(ICM_IMR) Region Status Updated Interrupt Mask

#define	ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos)

#define	ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos))

#define	ICM_IMR_URAD_Pos 24
	(ICM_IMR) Undefined Register Access Detection Interrupt Mask

#define	ICM_IMR_URAD (_U_(0x1) << ICM_IMR_URAD_Pos)

#define	ICM_IMR_MASK _U_(0x01FFFFFF)
	(ICM_IMR) MASK Register

#define	ICM_ISR_OFFSET 0x1C
	(ICM_ISR offset) Interrupt Status

#define	ICM_ISR_RESETVALUE _U_(0x00000000)
	(ICM_ISR reset_value) Interrupt Status

#define	ICM_ISR_RHC_Pos 0
	(ICM_ISR) Region Hash Completed

#define	ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos)

#define	ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos))

#define	ICM_ISR_RDM_Pos 4
	(ICM_ISR) Region Digest Mismatch

#define	ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos)

#define	ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos))

#define	ICM_ISR_RBE_Pos 8
	(ICM_ISR) Region Bus Error

#define	ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos)

#define	ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos))

#define	ICM_ISR_RWC_Pos 12
	(ICM_ISR) Region Wrap Condition Detected

#define	ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos)

#define	ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos))

#define	ICM_ISR_REC_Pos 16
	(ICM_ISR) Region End bit Condition Detected

#define	ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos)

#define	ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos))

#define	ICM_ISR_RSU_Pos 20
	(ICM_ISR) Region Status Updated Detected

#define	ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos)

#define	ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos))

#define	ICM_ISR_URAD_Pos 24
	(ICM_ISR) Undefined Register Access Detection Status

#define	ICM_ISR_URAD (_U_(0x1) << ICM_ISR_URAD_Pos)

#define	ICM_ISR_MASK _U_(0x01FFFFFF)
	(ICM_ISR) MASK Register

#define	ICM_UASR_OFFSET 0x20
	(ICM_UASR offset) Undefined Access Status

#define	ICM_UASR_RESETVALUE _U_(0x00000000)
	(ICM_UASR reset_value) Undefined Access Status

#define	ICM_UASR_URAT_Pos 0
	(ICM_UASR) Undefined Register Access Trace

#define	ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos)

#define	ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos))

#define	ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0)
	(ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded

#define	ICM_UASR_URAT_CFG_MODIFIED_Val _U_(0x1)
	(ICM_UASR) CFG modified during active monitoring

#define	ICM_UASR_URAT_DSCR_MODIFIED_Val _U_(0x2)
	(ICM_UASR) DSCR modified during active monitoring

#define	ICM_UASR_URAT_HASH_MODIFIED_Val _U_(0x3)
	(ICM_UASR) HASH modified during active monitoring

#define	ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4)
	(ICM_UASR) Write-only register read access

#define	ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos)

#define	ICM_UASR_URAT_CFG_MODIFIED (ICM_UASR_URAT_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos)

#define	ICM_UASR_URAT_DSCR_MODIFIED (ICM_UASR_URAT_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos)

#define	ICM_UASR_URAT_HASH_MODIFIED (ICM_UASR_URAT_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos)

#define	ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos)

#define	ICM_UASR_MASK _U_(0x00000007)
	(ICM_UASR) MASK Register

#define	ICM_DSCR_OFFSET 0x30
	(ICM_DSCR offset) Region Descriptor Area Start Address

#define	ICM_DSCR_RESETVALUE _U_(0x00000000)
	(ICM_DSCR reset_value) Region Descriptor Area Start Address

#define	ICM_DSCR_DASA_Pos 6
	(ICM_DSCR) Descriptor Area Start Address

#define	ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos)

#define	ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))

#define	ICM_DSCR_MASK _U_(0xFFFFFFC0)
	(ICM_DSCR) MASK Register

#define	ICM_HASH_OFFSET 0x34
	(ICM_HASH offset) Region Hash Area Start Address

#define	ICM_HASH_RESETVALUE _U_(0x00000000)
	(ICM_HASH reset_value) Region Hash Area Start Address

#define	ICM_HASH_HASA_Pos 7
	(ICM_HASH) Hash Area Start Address

#define	ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos)

#define	ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))

#define	ICM_HASH_MASK _U_(0xFFFFFF80)
	(ICM_HASH) MASK Register

#define	ICM_UIHVAL_OFFSET 0x38
	(ICM_UIHVAL offset) User Initial Hash Value n

#define	ICM_UIHVAL_RESETVALUE _U_(0x00000000)
	(ICM_UIHVAL reset_value) User Initial Hash Value n

#define	ICM_UIHVAL_VAL_Pos 0
	(ICM_UIHVAL) Initial Hash Value

#define	ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos)

#define	ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))

#define	ICM_UIHVAL_MASK _U_(0xFFFFFFFF)
	(ICM_UIHVAL) MASK Register

#define	ICM_RADDR_OFFSET 0x00
	(ICM_RADDR offset) Region Start Address

#define	ICM_RADDR_MASK _U_(0xFFFFFFFF)
	(ICM_RADDR) MASK Register

#define	ICM_RCFG_OFFSET 0x04
	(ICM_RCFG offset) Region Configuration

#define	ICM_RCFG_RESETVALUE _U_(0x00000000)
	(ICM_RCFG reset_value) Region Configuration

#define	ICM_RCFG_CDWBN_Pos 0
	(ICM_RCFG) Compare Digest Write Back

#define	ICM_RCFG_CDWBN (_U_(0x1) << ICM_RCFG_CDWBN_Pos)

#define	ICM_RCFG_CDWBN_WRBA_Val _U_(0x0)
	(ICM_RCFG)

#define	ICM_RCFG_CDWBN_COMP_Val _U_(0x1)
	(ICM_RCFG)

#define	ICM_RCFG_CDWBN_WRBA (ICM_RCFG_CDWBN_WRBA_Val << ICM_RCFG_CDWBN_Pos)

#define	ICM_RCFG_CDWBN_COMP (ICM_RCFG_CDWBN_COMP_Val << ICM_RCFG_CDWBN_Pos)

#define	ICM_RCFG_WRAP_Pos 1
	(ICM_RCFG) Region Wrap

#define	ICM_RCFG_WRAP (_U_(0x1) << ICM_RCFG_WRAP_Pos)

#define	ICM_RCFG_WRAP_NO_Val _U_(0x0)
	(ICM_RCFG)

#define	ICM_RCFG_WRAP_YES_Val _U_(0x1)
	(ICM_RCFG)

#define	ICM_RCFG_WRAP_NO (ICM_RCFG_WRAP_NO_Val << ICM_RCFG_WRAP_Pos)

#define	ICM_RCFG_WRAP_YES (ICM_RCFG_WRAP_YES_Val << ICM_RCFG_WRAP_Pos)

#define	ICM_RCFG_EOM_Pos 2
	(ICM_RCFG) End of Monitoring

#define	ICM_RCFG_EOM (_U_(0x1) << ICM_RCFG_EOM_Pos)

#define	ICM_RCFG_EOM_NO_Val _U_(0x0)
	(ICM_RCFG)

#define	ICM_RCFG_EOM_YES_Val _U_(0x1)
	(ICM_RCFG)

#define	ICM_RCFG_EOM_NO (ICM_RCFG_EOM_NO_Val << ICM_RCFG_EOM_Pos)

#define	ICM_RCFG_EOM_YES (ICM_RCFG_EOM_YES_Val << ICM_RCFG_EOM_Pos)

#define	ICM_RCFG_RHIEN_Pos 4
	(ICM_RCFG) Region Hash Interrupt Enable

#define	ICM_RCFG_RHIEN (_U_(0x1) << ICM_RCFG_RHIEN_Pos)

#define	ICM_RCFG_RHIEN_EN_Val _U_(0x0)
	(ICM_RCFG)

#define	ICM_RCFG_RHIEN_DIS_Val _U_(0x1)
	(ICM_RCFG)

#define	ICM_RCFG_RHIEN_EN (ICM_RCFG_RHIEN_EN_Val << ICM_RCFG_RHIEN_Pos)

#define	ICM_RCFG_RHIEN_DIS (ICM_RCFG_RHIEN_DIS_Val << ICM_RCFG_RHIEN_Pos)

#define	ICM_RCFG_DMIEN_Pos 5
	(ICM_RCFG) Region Digest Mismatch Interrupt Enable

#define	ICM_RCFG_DMIEN (_U_(0x1) << ICM_RCFG_DMIEN_Pos)

#define	ICM_RCFG_DMIEN_EN_Val _U_(0x0)
	(ICM_RCFG)

#define	ICM_RCFG_DMIEN_DIS_Val _U_(0x1)
	(ICM_RCFG)

#define	ICM_RCFG_DMIEN_EN (ICM_RCFG_DMIEN_EN_Val << ICM_RCFG_DMIEN_Pos)

#define	ICM_RCFG_DMIEN_DIS (ICM_RCFG_DMIEN_DIS_Val << ICM_RCFG_DMIEN_Pos)

#define	ICM_RCFG_BEIEN_Pos 6
	(ICM_RCFG) Region Bus Error Interrupt Enable

#define	ICM_RCFG_BEIEN (_U_(0x1) << ICM_RCFG_BEIEN_Pos)

#define	ICM_RCFG_BEIEN_EN_Val _U_(0x0)
	(ICM_RCFG)

#define	ICM_RCFG_BEIEN_DIS_Val _U_(0x1)
	(ICM_RCFG)

#define	ICM_RCFG_BEIEN_EN (ICM_RCFG_BEIEN_EN_Val << ICM_RCFG_BEIEN_Pos)

#define	ICM_RCFG_BEIEN_DIS (ICM_RCFG_BEIEN_DIS_Val << ICM_RCFG_BEIEN_Pos)

#define	ICM_RCFG_WCIEN_Pos 7
	(ICM_RCFG) Region Wrap Condition Detected Interrupt Enable

#define	ICM_RCFG_WCIEN (_U_(0x1) << ICM_RCFG_WCIEN_Pos)

#define	ICM_RCFG_WCIEN_EN_Val _U_(0x0)
	(ICM_RCFG)

#define	ICM_RCFG_WCIEN_DIS_Val _U_(0x1)
	(ICM_RCFG)

#define	ICM_RCFG_WCIEN_EN (ICM_RCFG_WCIEN_EN_Val << ICM_RCFG_WCIEN_Pos)

#define	ICM_RCFG_WCIEN_DIS (ICM_RCFG_WCIEN_DIS_Val << ICM_RCFG_WCIEN_Pos)

#define	ICM_RCFG_ECIEN_Pos 8
	(ICM_RCFG) Region End bit Condition detected Interrupt Enable

#define	ICM_RCFG_ECIEN (_U_(0x1) << ICM_RCFG_ECIEN_Pos)

#define	ICM_RCFG_ECIEN_EN_Val _U_(0x0)
	(ICM_RCFG)

#define	ICM_RCFG_ECIEN_DIS_Val _U_(0x1)
	(ICM_RCFG)

#define	ICM_RCFG_ECIEN_EN (ICM_RCFG_ECIEN_EN_Val << ICM_RCFG_ECIEN_Pos)

#define	ICM_RCFG_ECIEN_DIS (ICM_RCFG_ECIEN_DIS_Val << ICM_RCFG_ECIEN_Pos)

#define	ICM_RCFG_SUIEN_Pos 9
	(ICM_RCFG) Region Status Updated Interrupt Enable

#define	ICM_RCFG_SUIEN (_U_(0x1) << ICM_RCFG_SUIEN_Pos)

#define	ICM_RCFG_SUIEN_EN_Val _U_(0x0)
	(ICM_RCFG)

#define	ICM_RCFG_SUIEN_DIS_Val _U_(0x1)
	(ICM_RCFG)

#define	ICM_RCFG_SUIEN_EN (ICM_RCFG_SUIEN_EN_Val << ICM_RCFG_SUIEN_Pos)

#define	ICM_RCFG_SUIEN_DIS (ICM_RCFG_SUIEN_DIS_Val << ICM_RCFG_SUIEN_Pos)

#define	ICM_RCFG_PROCDLY_Pos 10
	(ICM_RCFG) SHA Processing Delay

#define	ICM_RCFG_PROCDLY (_U_(0x1) << ICM_RCFG_PROCDLY_Pos)

#define	ICM_RCFG_PROCDLY_SHORT_Val _U_(0x0)
	(ICM_RCFG)

#define	ICM_RCFG_PROCDLY_LONG_Val _U_(0x1)
	(ICM_RCFG)

#define	ICM_RCFG_PROCDLY_SHORT (ICM_RCFG_PROCDLY_SHORT_Val << ICM_RCFG_PROCDLY_Pos)

#define	ICM_RCFG_PROCDLY_LONG (ICM_RCFG_PROCDLY_LONG_Val << ICM_RCFG_PROCDLY_Pos)

#define	ICM_RCFG_ALGO_Pos 12
	(ICM_RCFG) SHA Algorithm

#define	ICM_RCFG_ALGO_Msk (_U_(0x7) << ICM_RCFG_ALGO_Pos)

#define	ICM_RCFG_ALGO(value) (ICM_RCFG_ALGO_Msk & ((value) << ICM_RCFG_ALGO_Pos))

#define	ICM_RCFG_MRPROT_Pos 24
	(ICM_RCFG) Memory Region AHB Protection

#define	ICM_RCFG_MRPROT_Msk (_U_(0x3F) << ICM_RCFG_MRPROT_Pos)

#define	ICM_RCFG_MRPROT(value) (ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos))

#define	ICM_RCFG_MASK _U_(0x3F0077F7)
	(ICM_RCFG) MASK Register

#define	ICM_RCTRL_OFFSET 0x08
	(ICM_RCTRL offset) Region Control

#define	ICM_RCTRL_TRSIZE_Pos 0
	(ICM_RCTRL) Transfer Size

#define	ICM_RCTRL_TRSIZE_Msk (_U_(0xFFFF) << ICM_RCTRL_TRSIZE_Pos)

#define	ICM_RCTRL_TRSIZE(value) (ICM_RCTRL_TRSIZE_Msk & ((value) << ICM_RCTRL_TRSIZE_Pos))

#define	ICM_RCTRL_MASK _U_(0x0000FFFF)
	(ICM_RCTRL) MASK Register

#define	ICM_RNEXT_OFFSET 0x0C
	(ICM_RNEXT offset) Region Next Address

#define	ICM_RNEXT_MASK _U_(0xFFFFFFFF)
	(ICM_RNEXT) MASK Register

#define	SECTION_ICM_DESCRIPTOR

Detailed Description

Component description for ICM.

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Definition in file icm.h.

Data Structures

Macros

Detailed Description