Component description for GCLK. More...

Data Structures
union	GCLK_CTRLA_Type

union	GCLK_SYNCBUSY_Type

union	GCLK_GENCTRL_Type

union	GCLK_PCHCTRL_Type

struct	Gclk
	GCLK hardware registers. More...

Macros
#define	GCLK_U2122

#define	REV_GCLK 0x120

#define	GCLK_CTRLA_OFFSET 0x00
	(GCLK_CTRLA offset) Control

#define	GCLK_CTRLA_RESETVALUE _U_(0x00)
	(GCLK_CTRLA reset_value) Control

#define	GCLK_CTRLA_SWRST_Pos 0
	(GCLK_CTRLA) Software Reset

#define	GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)

#define	GCLK_CTRLA_MASK _U_(0x01)
	(GCLK_CTRLA) MASK Register

#define	GCLK_SYNCBUSY_OFFSET 0x04
	(GCLK_SYNCBUSY offset) Synchronization Busy

#define	GCLK_SYNCBUSY_RESETVALUE _U_(0x00000000)
	(GCLK_SYNCBUSY reset_value) Synchronization Busy

#define	GCLK_SYNCBUSY_SWRST_Pos 0
	(GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit

#define	GCLK_SYNCBUSY_SWRST (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)

#define	GCLK_SYNCBUSY_GENCTRL0_Pos 2
	(GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bits

#define	GCLK_SYNCBUSY_GENCTRL0 (_U_(1) << GCLK_SYNCBUSY_GENCTRL0_Pos)

#define	GCLK_SYNCBUSY_GENCTRL1_Pos 3
	(GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bits

#define	GCLK_SYNCBUSY_GENCTRL1 (_U_(1) << GCLK_SYNCBUSY_GENCTRL1_Pos)

#define	GCLK_SYNCBUSY_GENCTRL2_Pos 4
	(GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bits

#define	GCLK_SYNCBUSY_GENCTRL2 (_U_(1) << GCLK_SYNCBUSY_GENCTRL2_Pos)

#define	GCLK_SYNCBUSY_GENCTRL3_Pos 5
	(GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bits

#define	GCLK_SYNCBUSY_GENCTRL3 (_U_(1) << GCLK_SYNCBUSY_GENCTRL3_Pos)

#define	GCLK_SYNCBUSY_GENCTRL4_Pos 6
	(GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bits

#define	GCLK_SYNCBUSY_GENCTRL4 (_U_(1) << GCLK_SYNCBUSY_GENCTRL4_Pos)

#define	GCLK_SYNCBUSY_GENCTRL5_Pos 7
	(GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bits

#define	GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)

#define	GCLK_SYNCBUSY_GENCTRL6_Pos 8
	(GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bits

#define	GCLK_SYNCBUSY_GENCTRL6 (_U_(1) << GCLK_SYNCBUSY_GENCTRL6_Pos)

#define	GCLK_SYNCBUSY_GENCTRL7_Pos 9
	(GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bits

#define	GCLK_SYNCBUSY_GENCTRL7 (_U_(1) << GCLK_SYNCBUSY_GENCTRL7_Pos)

#define	GCLK_SYNCBUSY_GENCTRL8_Pos 10
	(GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bits

#define	GCLK_SYNCBUSY_GENCTRL8 (_U_(1) << GCLK_SYNCBUSY_GENCTRL8_Pos)

#define	GCLK_SYNCBUSY_GENCTRL9_Pos 11
	(GCLK_SYNCBUSY) Generic Clock Generator Control 9 Synchronization Busy bits

#define	GCLK_SYNCBUSY_GENCTRL9 (_U_(1) << GCLK_SYNCBUSY_GENCTRL9_Pos)

#define	GCLK_SYNCBUSY_GENCTRL10_Pos 12
	(GCLK_SYNCBUSY) Generic Clock Generator Control 10 Synchronization Busy bits

#define	GCLK_SYNCBUSY_GENCTRL10 (_U_(1) << GCLK_SYNCBUSY_GENCTRL10_Pos)

#define	GCLK_SYNCBUSY_GENCTRL11_Pos 13
	(GCLK_SYNCBUSY) Generic Clock Generator Control 11 Synchronization Busy bits

#define	GCLK_SYNCBUSY_GENCTRL11 (_U_(1) << GCLK_SYNCBUSY_GENCTRL11_Pos)

#define	GCLK_SYNCBUSY_GENCTRL_Pos 2
	(GCLK_SYNCBUSY) Generic Clock Generator Control x Synchronization Busy bits

#define	GCLK_SYNCBUSY_GENCTRL_Msk (_U_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos)

#define	GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))

#define	GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1)
	(GCLK_SYNCBUSY) Generic clock generator 0

#define	GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2)
	(GCLK_SYNCBUSY) Generic clock generator 1

#define	GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4)
	(GCLK_SYNCBUSY) Generic clock generator 2

#define	GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8)
	(GCLK_SYNCBUSY) Generic clock generator 3

#define	GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10)
	(GCLK_SYNCBUSY) Generic clock generator 4

#define	GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20)
	(GCLK_SYNCBUSY) Generic clock generator 5

#define	GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40)
	(GCLK_SYNCBUSY) Generic clock generator 6

#define	GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80)
	(GCLK_SYNCBUSY) Generic clock generator 7

#define	GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100)
	(GCLK_SYNCBUSY) Generic clock generator 8

#define	GCLK_SYNCBUSY_GENCTRL_GCLK9_Val _U_(0x200)
	(GCLK_SYNCBUSY) Generic clock generator 9

#define	GCLK_SYNCBUSY_GENCTRL_GCLK10_Val _U_(0x400)
	(GCLK_SYNCBUSY) Generic clock generator 10

#define	GCLK_SYNCBUSY_GENCTRL_GCLK11_Val _U_(0x800)
	(GCLK_SYNCBUSY) Generic clock generator 11

#define	GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos)

#define	GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos)

#define	GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos)

#define	GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos)

#define	GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos)

#define	GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos)

#define	GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos)

#define	GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos)

#define	GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos)

#define	GCLK_SYNCBUSY_GENCTRL_GCLK9 (GCLK_SYNCBUSY_GENCTRL_GCLK9_Val << GCLK_SYNCBUSY_GENCTRL_Pos)

#define	GCLK_SYNCBUSY_GENCTRL_GCLK10 (GCLK_SYNCBUSY_GENCTRL_GCLK10_Val << GCLK_SYNCBUSY_GENCTRL_Pos)

#define	GCLK_SYNCBUSY_GENCTRL_GCLK11 (GCLK_SYNCBUSY_GENCTRL_GCLK11_Val << GCLK_SYNCBUSY_GENCTRL_Pos)

#define	GCLK_SYNCBUSY_MASK _U_(0x00003FFD)
	(GCLK_SYNCBUSY) MASK Register

#define	GCLK_GENCTRL_OFFSET 0x20
	(GCLK_GENCTRL offset) Generic Clock Generator Control

#define	GCLK_GENCTRL_RESETVALUE _U_(0x00000000)
	(GCLK_GENCTRL reset_value) Generic Clock Generator Control

#define	GCLK_GENCTRL_SRC_Pos 0
	(GCLK_GENCTRL) Source Select

#define	GCLK_GENCTRL_SRC_Msk (_U_(0xF) << GCLK_GENCTRL_SRC_Pos)

#define	GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))

#define	GCLK_GENCTRL_SRC_XOSC0_Val _U_(0x0)
	(GCLK_GENCTRL) XOSC0 oscillator output

#define	GCLK_GENCTRL_SRC_XOSC1_Val _U_(0x1)
	(GCLK_GENCTRL) XOSC1 oscillator output

#define	GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x2)
	(GCLK_GENCTRL) Generator input pad

#define	GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x3)
	(GCLK_GENCTRL) Generic clock generator 1 output

#define	GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x4)
	(GCLK_GENCTRL) OSCULP32K oscillator output

#define	GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5)
	(GCLK_GENCTRL) XOSC32K oscillator output

#define	GCLK_GENCTRL_SRC_DFLL_Val _U_(0x6)
	(GCLK_GENCTRL) DFLL output

#define	GCLK_GENCTRL_SRC_DPLL0_Val _U_(0x7)
	(GCLK_GENCTRL) DPLL0 output

#define	GCLK_GENCTRL_SRC_DPLL1_Val _U_(0x8)
	(GCLK_GENCTRL) DPLL1 output

#define	GCLK_GENCTRL_SRC_XOSC0 (GCLK_GENCTRL_SRC_XOSC0_Val << GCLK_GENCTRL_SRC_Pos)

#define	GCLK_GENCTRL_SRC_XOSC1 (GCLK_GENCTRL_SRC_XOSC1_Val << GCLK_GENCTRL_SRC_Pos)

#define	GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)

#define	GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)

#define	GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)

#define	GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)

#define	GCLK_GENCTRL_SRC_DFLL (GCLK_GENCTRL_SRC_DFLL_Val << GCLK_GENCTRL_SRC_Pos)

#define	GCLK_GENCTRL_SRC_DPLL0 (GCLK_GENCTRL_SRC_DPLL0_Val << GCLK_GENCTRL_SRC_Pos)

#define	GCLK_GENCTRL_SRC_DPLL1 (GCLK_GENCTRL_SRC_DPLL1_Val << GCLK_GENCTRL_SRC_Pos)

#define	GCLK_GENCTRL_GENEN_Pos 8
	(GCLK_GENCTRL) Generic Clock Generator Enable

#define	GCLK_GENCTRL_GENEN (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)

#define	GCLK_GENCTRL_IDC_Pos 9
	(GCLK_GENCTRL) Improve Duty Cycle

#define	GCLK_GENCTRL_IDC (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)

#define	GCLK_GENCTRL_OOV_Pos 10
	(GCLK_GENCTRL) Output Off Value

#define	GCLK_GENCTRL_OOV (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)

#define	GCLK_GENCTRL_OE_Pos 11
	(GCLK_GENCTRL) Output Enable

#define	GCLK_GENCTRL_OE (_U_(0x1) << GCLK_GENCTRL_OE_Pos)

#define	GCLK_GENCTRL_DIVSEL_Pos 12
	(GCLK_GENCTRL) Divide Selection

#define	GCLK_GENCTRL_DIVSEL (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)

#define	GCLK_GENCTRL_RUNSTDBY_Pos 13
	(GCLK_GENCTRL) Run in Standby

#define	GCLK_GENCTRL_RUNSTDBY (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)

#define	GCLK_GENCTRL_DIV_Pos 16
	(GCLK_GENCTRL) Division Factor

#define	GCLK_GENCTRL_DIV_Msk (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)

#define	GCLK_GENCTRL_DIV(value) (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))

#define	GCLK_GENCTRL_MASK _U_(0xFFFF3F0F)
	(GCLK_GENCTRL) MASK Register

#define	GCLK_PCHCTRL_OFFSET 0x80
	(GCLK_PCHCTRL offset) Peripheral Clock Control

#define	GCLK_PCHCTRL_RESETVALUE _U_(0x00000000)
	(GCLK_PCHCTRL reset_value) Peripheral Clock Control

#define	GCLK_PCHCTRL_GEN_Pos 0
	(GCLK_PCHCTRL) Generic Clock Generator

#define	GCLK_PCHCTRL_GEN_Msk (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos)

#define	GCLK_PCHCTRL_GEN(value) (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))

#define	GCLK_PCHCTRL_GEN_GCLK0_Val _U_(0x0)
	(GCLK_PCHCTRL) Generic clock generator 0

#define	GCLK_PCHCTRL_GEN_GCLK1_Val _U_(0x1)
	(GCLK_PCHCTRL) Generic clock generator 1

#define	GCLK_PCHCTRL_GEN_GCLK2_Val _U_(0x2)
	(GCLK_PCHCTRL) Generic clock generator 2

#define	GCLK_PCHCTRL_GEN_GCLK3_Val _U_(0x3)
	(GCLK_PCHCTRL) Generic clock generator 3

#define	GCLK_PCHCTRL_GEN_GCLK4_Val _U_(0x4)
	(GCLK_PCHCTRL) Generic clock generator 4

#define	GCLK_PCHCTRL_GEN_GCLK5_Val _U_(0x5)
	(GCLK_PCHCTRL) Generic clock generator 5

#define	GCLK_PCHCTRL_GEN_GCLK6_Val _U_(0x6)
	(GCLK_PCHCTRL) Generic clock generator 6

#define	GCLK_PCHCTRL_GEN_GCLK7_Val _U_(0x7)
	(GCLK_PCHCTRL) Generic clock generator 7

#define	GCLK_PCHCTRL_GEN_GCLK8_Val _U_(0x8)
	(GCLK_PCHCTRL) Generic clock generator 8

#define	GCLK_PCHCTRL_GEN_GCLK9_Val _U_(0x9)
	(GCLK_PCHCTRL) Generic clock generator 9

#define	GCLK_PCHCTRL_GEN_GCLK10_Val _U_(0xA)
	(GCLK_PCHCTRL) Generic clock generator 10

#define	GCLK_PCHCTRL_GEN_GCLK11_Val _U_(0xB)
	(GCLK_PCHCTRL) Generic clock generator 11

#define	GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos)

#define	GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos)

#define	GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos)

#define	GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos)

#define	GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos)

#define	GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos)

#define	GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos)

#define	GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos)

#define	GCLK_PCHCTRL_GEN_GCLK8 (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos)

#define	GCLK_PCHCTRL_GEN_GCLK9 (GCLK_PCHCTRL_GEN_GCLK9_Val << GCLK_PCHCTRL_GEN_Pos)

#define	GCLK_PCHCTRL_GEN_GCLK10 (GCLK_PCHCTRL_GEN_GCLK10_Val << GCLK_PCHCTRL_GEN_Pos)

#define	GCLK_PCHCTRL_GEN_GCLK11 (GCLK_PCHCTRL_GEN_GCLK11_Val << GCLK_PCHCTRL_GEN_Pos)

#define	GCLK_PCHCTRL_CHEN_Pos 6
	(GCLK_PCHCTRL) Channel Enable

#define	GCLK_PCHCTRL_CHEN (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)

#define	GCLK_PCHCTRL_WRTLOCK_Pos 7
	(GCLK_PCHCTRL) Write Lock

#define	GCLK_PCHCTRL_WRTLOCK (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)

#define	GCLK_PCHCTRL_MASK _U_(0x000000CF)
	(GCLK_PCHCTRL) MASK Register

Detailed Description

Component description for GCLK.

\asf_license_start

Definition in file gclk.h.

Data Structures

Macros

Detailed Description