Component description for DSU. More...

Data Structures
union	DSU_CTRL_Type

union	DSU_STATUSA_Type

union	DSU_STATUSB_Type

union	DSU_ADDR_Type

union	DSU_LENGTH_Type

union	DSU_DATA_Type

union	DSU_DCC_Type

union	DSU_DID_Type

union	DSU_CFG_Type

union	DSU_ENTRY0_Type

union	DSU_ENTRY1_Type

union	DSU_END_Type

union	DSU_MEMTYPE_Type

union	DSU_PID4_Type

union	DSU_PID5_Type

union	DSU_PID6_Type

union	DSU_PID7_Type

union	DSU_PID0_Type

union	DSU_PID1_Type

union	DSU_PID2_Type

union	DSU_PID3_Type

union	DSU_CID0_Type

union	DSU_CID1_Type

union	DSU_CID2_Type

union	DSU_CID3_Type

struct	Dsu
	DSU hardware registers. More...

Macros
#define	DSU_U2410

#define	REV_DSU 0x100

#define	DSU_CTRL_OFFSET 0x0000
	(DSU_CTRL offset) Control

#define	DSU_CTRL_RESETVALUE _U_(0x00)
	(DSU_CTRL reset_value) Control

#define	DSU_CTRL_SWRST_Pos 0
	(DSU_CTRL) Software Reset

#define	DSU_CTRL_SWRST (_U_(0x1) << DSU_CTRL_SWRST_Pos)

#define	DSU_CTRL_CRC_Pos 2
	(DSU_CTRL) 32-bit Cyclic Redundancy Code

#define	DSU_CTRL_CRC (_U_(0x1) << DSU_CTRL_CRC_Pos)

#define	DSU_CTRL_MBIST_Pos 3
	(DSU_CTRL) Memory built-in self-test

#define	DSU_CTRL_MBIST (_U_(0x1) << DSU_CTRL_MBIST_Pos)

#define	DSU_CTRL_CE_Pos 4
	(DSU_CTRL) Chip-Erase

#define	DSU_CTRL_CE (_U_(0x1) << DSU_CTRL_CE_Pos)

#define	DSU_CTRL_ARR_Pos 6
	(DSU_CTRL) Auxiliary Row Read

#define	DSU_CTRL_ARR (_U_(0x1) << DSU_CTRL_ARR_Pos)

#define	DSU_CTRL_SMSA_Pos 7
	(DSU_CTRL) Start Memory Stream Access

#define	DSU_CTRL_SMSA (_U_(0x1) << DSU_CTRL_SMSA_Pos)

#define	DSU_CTRL_MASK _U_(0xDD)
	(DSU_CTRL) MASK Register

#define	DSU_STATUSA_OFFSET 0x0001
	(DSU_STATUSA offset) Status A

#define	DSU_STATUSA_RESETVALUE _U_(0x00)
	(DSU_STATUSA reset_value) Status A

#define	DSU_STATUSA_DONE_Pos 0
	(DSU_STATUSA) Done

#define	DSU_STATUSA_DONE (_U_(0x1) << DSU_STATUSA_DONE_Pos)

#define	DSU_STATUSA_CRSTEXT_Pos 1
	(DSU_STATUSA) CPU Reset Phase Extension

#define	DSU_STATUSA_CRSTEXT (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos)

#define	DSU_STATUSA_BERR_Pos 2
	(DSU_STATUSA) Bus Error

#define	DSU_STATUSA_BERR (_U_(0x1) << DSU_STATUSA_BERR_Pos)

#define	DSU_STATUSA_FAIL_Pos 3
	(DSU_STATUSA) Failure

#define	DSU_STATUSA_FAIL (_U_(0x1) << DSU_STATUSA_FAIL_Pos)

#define	DSU_STATUSA_PERR_Pos 4
	(DSU_STATUSA) Protection Error

#define	DSU_STATUSA_PERR (_U_(0x1) << DSU_STATUSA_PERR_Pos)

#define	DSU_STATUSA_MASK _U_(0x1F)
	(DSU_STATUSA) MASK Register

#define	DSU_STATUSB_OFFSET 0x0002
	(DSU_STATUSB offset) Status B

#define	DSU_STATUSB_RESETVALUE _U_(0x00)
	(DSU_STATUSB reset_value) Status B

#define	DSU_STATUSB_PROT_Pos 0
	(DSU_STATUSB) Protected

#define	DSU_STATUSB_PROT (_U_(0x1) << DSU_STATUSB_PROT_Pos)

#define	DSU_STATUSB_DBGPRES_Pos 1
	(DSU_STATUSB) Debugger Present

#define	DSU_STATUSB_DBGPRES (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos)

#define	DSU_STATUSB_DCCD0_Pos 2
	(DSU_STATUSB) Debug Communication Channel 0 Dirty

#define	DSU_STATUSB_DCCD0 (_U_(1) << DSU_STATUSB_DCCD0_Pos)

#define	DSU_STATUSB_DCCD1_Pos 3
	(DSU_STATUSB) Debug Communication Channel 1 Dirty

#define	DSU_STATUSB_DCCD1 (_U_(1) << DSU_STATUSB_DCCD1_Pos)

#define	DSU_STATUSB_DCCD_Pos 2
	(DSU_STATUSB) Debug Communication Channel x Dirty

#define	DSU_STATUSB_DCCD_Msk (_U_(0x3) << DSU_STATUSB_DCCD_Pos)

#define	DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))

#define	DSU_STATUSB_HPE_Pos 4
	(DSU_STATUSB) Hot-Plugging Enable

#define	DSU_STATUSB_HPE (_U_(0x1) << DSU_STATUSB_HPE_Pos)

#define	DSU_STATUSB_CELCK_Pos 5
	(DSU_STATUSB) Chip Erase Locked

#define	DSU_STATUSB_CELCK (_U_(0x1) << DSU_STATUSB_CELCK_Pos)

#define	DSU_STATUSB_MASK _U_(0x3F)
	(DSU_STATUSB) MASK Register

#define	DSU_ADDR_OFFSET 0x0004
	(DSU_ADDR offset) Address

#define	DSU_ADDR_RESETVALUE _U_(0x00000000)
	(DSU_ADDR reset_value) Address

#define	DSU_ADDR_AMOD_Pos 0
	(DSU_ADDR) Access Mode

#define	DSU_ADDR_AMOD_Msk (_U_(0x3) << DSU_ADDR_AMOD_Pos)

#define	DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos))

#define	DSU_ADDR_ADDR_Pos 2
	(DSU_ADDR) Address

#define	DSU_ADDR_ADDR_Msk (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos)

#define	DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))

#define	DSU_ADDR_MASK _U_(0xFFFFFFFF)
	(DSU_ADDR) MASK Register

#define	DSU_LENGTH_OFFSET 0x0008
	(DSU_LENGTH offset) Length

#define	DSU_LENGTH_RESETVALUE _U_(0x00000000)
	(DSU_LENGTH reset_value) Length

#define	DSU_LENGTH_LENGTH_Pos 2
	(DSU_LENGTH) Length

#define	DSU_LENGTH_LENGTH_Msk (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos)

#define	DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))

#define	DSU_LENGTH_MASK _U_(0xFFFFFFFC)
	(DSU_LENGTH) MASK Register

#define	DSU_DATA_OFFSET 0x000C
	(DSU_DATA offset) Data

#define	DSU_DATA_RESETVALUE _U_(0x00000000)
	(DSU_DATA reset_value) Data

#define	DSU_DATA_DATA_Pos 0
	(DSU_DATA) Data

#define	DSU_DATA_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos)

#define	DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))

#define	DSU_DATA_MASK _U_(0xFFFFFFFF)
	(DSU_DATA) MASK Register

#define	DSU_DCC_OFFSET 0x0010
	(DSU_DCC offset) Debug Communication Channel n

#define	DSU_DCC_RESETVALUE _U_(0x00000000)
	(DSU_DCC reset_value) Debug Communication Channel n

#define	DSU_DCC_DATA_Pos 0
	(DSU_DCC) Data

#define	DSU_DCC_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos)

#define	DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))

#define	DSU_DCC_MASK _U_(0xFFFFFFFF)
	(DSU_DCC) MASK Register

#define	DSU_DID_OFFSET 0x0018
	(DSU_DID offset) Device Identification

#define	DSU_DID_DEVSEL_Pos 0
	(DSU_DID) Device Select

#define	DSU_DID_DEVSEL_Msk (_U_(0xFF) << DSU_DID_DEVSEL_Pos)

#define	DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))

#define	DSU_DID_REVISION_Pos 8
	(DSU_DID) Revision Number

#define	DSU_DID_REVISION_Msk (_U_(0xF) << DSU_DID_REVISION_Pos)

#define	DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))

#define	DSU_DID_DIE_Pos 12
	(DSU_DID) Die Number

#define	DSU_DID_DIE_Msk (_U_(0xF) << DSU_DID_DIE_Pos)

#define	DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))

#define	DSU_DID_SERIES_Pos 16
	(DSU_DID) Series

#define	DSU_DID_SERIES_Msk (_U_(0x3F) << DSU_DID_SERIES_Pos)

#define	DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))

#define	DSU_DID_SERIES_0_Val _U_(0x0)
	(DSU_DID) Cortex-M0+ processor, basic feature set

#define	DSU_DID_SERIES_1_Val _U_(0x1)
	(DSU_DID) Cortex-M0+ processor, USB

#define	DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos)

#define	DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos)

#define	DSU_DID_FAMILY_Pos 23
	(DSU_DID) Family

#define	DSU_DID_FAMILY_Msk (_U_(0x1F) << DSU_DID_FAMILY_Pos)

#define	DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))

#define	DSU_DID_FAMILY_0_Val _U_(0x0)
	(DSU_DID) General purpose microcontroller

#define	DSU_DID_FAMILY_1_Val _U_(0x1)
	(DSU_DID) PicoPower

#define	DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos)

#define	DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos)

#define	DSU_DID_PROCESSOR_Pos 28
	(DSU_DID) Processor

#define	DSU_DID_PROCESSOR_Msk (_U_(0xF) << DSU_DID_PROCESSOR_Pos)

#define	DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))

#define	DSU_DID_PROCESSOR_CM0P_Val _U_(0x1)
	(DSU_DID) Cortex-M0+

#define	DSU_DID_PROCESSOR_CM23_Val _U_(0x2)
	(DSU_DID) Cortex-M23

#define	DSU_DID_PROCESSOR_CM3_Val _U_(0x3)
	(DSU_DID) Cortex-M3

#define	DSU_DID_PROCESSOR_CM4_Val _U_(0x5)
	(DSU_DID) Cortex-M4

#define	DSU_DID_PROCESSOR_CM4F_Val _U_(0x6)
	(DSU_DID) Cortex-M4 with FPU

#define	DSU_DID_PROCESSOR_CM33_Val _U_(0x7)
	(DSU_DID) Cortex-M33

#define	DSU_DID_PROCESSOR_CM0P (DSU_DID_PROCESSOR_CM0P_Val << DSU_DID_PROCESSOR_Pos)

#define	DSU_DID_PROCESSOR_CM23 (DSU_DID_PROCESSOR_CM23_Val << DSU_DID_PROCESSOR_Pos)

#define	DSU_DID_PROCESSOR_CM3 (DSU_DID_PROCESSOR_CM3_Val << DSU_DID_PROCESSOR_Pos)

#define	DSU_DID_PROCESSOR_CM4 (DSU_DID_PROCESSOR_CM4_Val << DSU_DID_PROCESSOR_Pos)

#define	DSU_DID_PROCESSOR_CM4F (DSU_DID_PROCESSOR_CM4F_Val << DSU_DID_PROCESSOR_Pos)

#define	DSU_DID_PROCESSOR_CM33 (DSU_DID_PROCESSOR_CM33_Val << DSU_DID_PROCESSOR_Pos)

#define	DSU_DID_MASK _U_(0xFFBFFFFF)
	(DSU_DID) MASK Register

#define	DSU_CFG_OFFSET 0x001C
	(DSU_CFG offset) Configuration

#define	DSU_CFG_RESETVALUE _U_(0x00000002)
	(DSU_CFG reset_value) Configuration

#define	DSU_CFG_LQOS_Pos 0
	(DSU_CFG) Latency Quality Of Service

#define	DSU_CFG_LQOS_Msk (_U_(0x3) << DSU_CFG_LQOS_Pos)

#define	DSU_CFG_LQOS(value) (DSU_CFG_LQOS_Msk & ((value) << DSU_CFG_LQOS_Pos))

#define	DSU_CFG_DCCDMALEVEL_Pos 2
	(DSU_CFG) DMA Trigger Level

#define	DSU_CFG_DCCDMALEVEL_Msk (_U_(0x3) << DSU_CFG_DCCDMALEVEL_Pos)

#define	DSU_CFG_DCCDMALEVEL(value) (DSU_CFG_DCCDMALEVEL_Msk & ((value) << DSU_CFG_DCCDMALEVEL_Pos))

#define	DSU_CFG_DCCDMALEVEL_EMPTY_Val _U_(0x0)
	(DSU_CFG) Trigger rises when DCC is empty

#define	DSU_CFG_DCCDMALEVEL_FULL_Val _U_(0x1)
	(DSU_CFG) Trigger rises when DCC is full

#define	DSU_CFG_DCCDMALEVEL_EMPTY (DSU_CFG_DCCDMALEVEL_EMPTY_Val << DSU_CFG_DCCDMALEVEL_Pos)

#define	DSU_CFG_DCCDMALEVEL_FULL (DSU_CFG_DCCDMALEVEL_FULL_Val << DSU_CFG_DCCDMALEVEL_Pos)

#define	DSU_CFG_ETBRAMEN_Pos 4
	(DSU_CFG) Trace Control

#define	DSU_CFG_ETBRAMEN (_U_(0x1) << DSU_CFG_ETBRAMEN_Pos)

#define	DSU_CFG_MASK _U_(0x0000001F)
	(DSU_CFG) MASK Register

#define	DSU_ENTRY0_OFFSET 0x1000
	(DSU_ENTRY0 offset) CoreSight ROM Table Entry 0

#define	DSU_ENTRY0_RESETVALUE _U_(0x9F0FC002)
	(DSU_ENTRY0 reset_value) CoreSight ROM Table Entry 0

#define	DSU_ENTRY0_EPRES_Pos 0
	(DSU_ENTRY0) Entry Present

#define	DSU_ENTRY0_EPRES (_U_(0x1) << DSU_ENTRY0_EPRES_Pos)

#define	DSU_ENTRY0_FMT_Pos 1
	(DSU_ENTRY0) Format

#define	DSU_ENTRY0_FMT (_U_(0x1) << DSU_ENTRY0_FMT_Pos)

#define	DSU_ENTRY0_ADDOFF_Pos 12
	(DSU_ENTRY0) Address Offset

#define	DSU_ENTRY0_ADDOFF_Msk (_U_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos)

#define	DSU_ENTRY0_ADDOFF(value) (DSU_ENTRY0_ADDOFF_Msk & ((value) << DSU_ENTRY0_ADDOFF_Pos))

#define	DSU_ENTRY0_MASK _U_(0xFFFFF003)
	(DSU_ENTRY0) MASK Register

#define	DSU_ENTRY1_OFFSET 0x1004
	(DSU_ENTRY1 offset) CoreSight ROM Table Entry 1

#define	DSU_ENTRY1_RESETVALUE _U_(0x00000000)
	(DSU_ENTRY1 reset_value) CoreSight ROM Table Entry 1

#define	DSU_ENTRY1_MASK _U_(0xFFFFFFFF)
	(DSU_ENTRY1) MASK Register

#define	DSU_END_OFFSET 0x1008
	(DSU_END offset) CoreSight ROM Table End

#define	DSU_END_RESETVALUE _U_(0x00000000)
	(DSU_END reset_value) CoreSight ROM Table End

#define	DSU_END_END_Pos 0
	(DSU_END) End Marker

#define	DSU_END_END_Msk (_U_(0xFFFFFFFF) << DSU_END_END_Pos)

#define	DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))

#define	DSU_END_MASK _U_(0xFFFFFFFF)
	(DSU_END) MASK Register

#define	DSU_MEMTYPE_OFFSET 0x1FCC
	(DSU_MEMTYPE offset) CoreSight ROM Table Memory Type

#define	DSU_MEMTYPE_RESETVALUE _U_(0x00000000)
	(DSU_MEMTYPE reset_value) CoreSight ROM Table Memory Type

#define	DSU_MEMTYPE_SMEMP_Pos 0
	(DSU_MEMTYPE) System Memory Present

#define	DSU_MEMTYPE_SMEMP (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos)

#define	DSU_MEMTYPE_MASK _U_(0x00000001)
	(DSU_MEMTYPE) MASK Register

#define	DSU_PID4_OFFSET 0x1FD0
	(DSU_PID4 offset) Peripheral Identification 4

#define	DSU_PID4_RESETVALUE _U_(0x00000000)
	(DSU_PID4 reset_value) Peripheral Identification 4

#define	DSU_PID4_JEPCC_Pos 0
	(DSU_PID4) JEP-106 Continuation Code

#define	DSU_PID4_JEPCC_Msk (_U_(0xF) << DSU_PID4_JEPCC_Pos)

#define	DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))

#define	DSU_PID4_FKBC_Pos 4
	(DSU_PID4) 4KB count

#define	DSU_PID4_FKBC_Msk (_U_(0xF) << DSU_PID4_FKBC_Pos)

#define	DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))

#define	DSU_PID4_MASK _U_(0x000000FF)
	(DSU_PID4) MASK Register

#define	DSU_PID5_OFFSET 0x1FD4
	(DSU_PID5 offset) Peripheral Identification 5

#define	DSU_PID5_RESETVALUE _U_(0x00000000)
	(DSU_PID5 reset_value) Peripheral Identification 5

#define	DSU_PID5_MASK _U_(0x00000000)
	(DSU_PID5) MASK Register

#define	DSU_PID6_OFFSET 0x1FD8
	(DSU_PID6 offset) Peripheral Identification 6

#define	DSU_PID6_RESETVALUE _U_(0x00000000)
	(DSU_PID6 reset_value) Peripheral Identification 6

#define	DSU_PID6_MASK _U_(0x00000000)
	(DSU_PID6) MASK Register

#define	DSU_PID7_OFFSET 0x1FDC
	(DSU_PID7 offset) Peripheral Identification 7

#define	DSU_PID7_RESETVALUE _U_(0x00000000)
	(DSU_PID7 reset_value) Peripheral Identification 7

#define	DSU_PID7_MASK _U_(0x00000000)
	(DSU_PID7) MASK Register

#define	DSU_PID0_OFFSET 0x1FE0
	(DSU_PID0 offset) Peripheral Identification 0

#define	DSU_PID0_RESETVALUE _U_(0x000000D0)
	(DSU_PID0 reset_value) Peripheral Identification 0

#define	DSU_PID0_PARTNBL_Pos 0
	(DSU_PID0) Part Number Low

#define	DSU_PID0_PARTNBL_Msk (_U_(0xFF) << DSU_PID0_PARTNBL_Pos)

#define	DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))

#define	DSU_PID0_MASK _U_(0x000000FF)
	(DSU_PID0) MASK Register

#define	DSU_PID1_OFFSET 0x1FE4
	(DSU_PID1 offset) Peripheral Identification 1

#define	DSU_PID1_RESETVALUE _U_(0x000000FC)
	(DSU_PID1 reset_value) Peripheral Identification 1

#define	DSU_PID1_PARTNBH_Pos 0
	(DSU_PID1) Part Number High

#define	DSU_PID1_PARTNBH_Msk (_U_(0xF) << DSU_PID1_PARTNBH_Pos)

#define	DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))

#define	DSU_PID1_JEPIDCL_Pos 4
	(DSU_PID1) Low part of the JEP-106 Identity Code

#define	DSU_PID1_JEPIDCL_Msk (_U_(0xF) << DSU_PID1_JEPIDCL_Pos)

#define	DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))

#define	DSU_PID1_MASK _U_(0x000000FF)
	(DSU_PID1) MASK Register

#define	DSU_PID2_OFFSET 0x1FE8
	(DSU_PID2 offset) Peripheral Identification 2

#define	DSU_PID2_RESETVALUE _U_(0x00000009)
	(DSU_PID2 reset_value) Peripheral Identification 2

#define	DSU_PID2_JEPIDCH_Pos 0
	(DSU_PID2) JEP-106 Identity Code High

#define	DSU_PID2_JEPIDCH_Msk (_U_(0x7) << DSU_PID2_JEPIDCH_Pos)

#define	DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))

#define	DSU_PID2_JEPU_Pos 3
	(DSU_PID2) JEP-106 Identity Code is used

#define	DSU_PID2_JEPU (_U_(0x1) << DSU_PID2_JEPU_Pos)

#define	DSU_PID2_REVISION_Pos 4
	(DSU_PID2) Revision Number

#define	DSU_PID2_REVISION_Msk (_U_(0xF) << DSU_PID2_REVISION_Pos)

#define	DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))

#define	DSU_PID2_MASK _U_(0x000000FF)
	(DSU_PID2) MASK Register

#define	DSU_PID3_OFFSET 0x1FEC
	(DSU_PID3 offset) Peripheral Identification 3

#define	DSU_PID3_RESETVALUE _U_(0x00000000)
	(DSU_PID3 reset_value) Peripheral Identification 3

#define	DSU_PID3_CUSMOD_Pos 0
	(DSU_PID3) ARM CUSMOD

#define	DSU_PID3_CUSMOD_Msk (_U_(0xF) << DSU_PID3_CUSMOD_Pos)

#define	DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))

#define	DSU_PID3_REVAND_Pos 4
	(DSU_PID3) Revision Number

#define	DSU_PID3_REVAND_Msk (_U_(0xF) << DSU_PID3_REVAND_Pos)

#define	DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))

#define	DSU_PID3_MASK _U_(0x000000FF)
	(DSU_PID3) MASK Register

#define	DSU_CID0_OFFSET 0x1FF0
	(DSU_CID0 offset) Component Identification 0

#define	DSU_CID0_RESETVALUE _U_(0x0000000D)
	(DSU_CID0 reset_value) Component Identification 0

#define	DSU_CID0_PREAMBLEB0_Pos 0
	(DSU_CID0) Preamble Byte 0

#define	DSU_CID0_PREAMBLEB0_Msk (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos)

#define	DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))

#define	DSU_CID0_MASK _U_(0x000000FF)
	(DSU_CID0) MASK Register

#define	DSU_CID1_OFFSET 0x1FF4
	(DSU_CID1 offset) Component Identification 1

#define	DSU_CID1_RESETVALUE _U_(0x00000010)
	(DSU_CID1 reset_value) Component Identification 1

#define	DSU_CID1_PREAMBLE_Pos 0
	(DSU_CID1) Preamble

#define	DSU_CID1_PREAMBLE_Msk (_U_(0xF) << DSU_CID1_PREAMBLE_Pos)

#define	DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))

#define	DSU_CID1_CCLASS_Pos 4
	(DSU_CID1) Component Class

#define	DSU_CID1_CCLASS_Msk (_U_(0xF) << DSU_CID1_CCLASS_Pos)

#define	DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))

#define	DSU_CID1_MASK _U_(0x000000FF)
	(DSU_CID1) MASK Register

#define	DSU_CID2_OFFSET 0x1FF8
	(DSU_CID2 offset) Component Identification 2

#define	DSU_CID2_RESETVALUE _U_(0x00000005)
	(DSU_CID2 reset_value) Component Identification 2

#define	DSU_CID2_PREAMBLEB2_Pos 0
	(DSU_CID2) Preamble Byte 2

#define	DSU_CID2_PREAMBLEB2_Msk (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos)

#define	DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))

#define	DSU_CID2_MASK _U_(0x000000FF)
	(DSU_CID2) MASK Register

#define	DSU_CID3_OFFSET 0x1FFC
	(DSU_CID3 offset) Component Identification 3

#define	DSU_CID3_RESETVALUE _U_(0x000000B1)
	(DSU_CID3 reset_value) Component Identification 3

#define	DSU_CID3_PREAMBLEB3_Pos 0
	(DSU_CID3) Preamble Byte 3

#define	DSU_CID3_PREAMBLEB3_Msk (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos)

#define	DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))

#define	DSU_CID3_MASK _U_(0x000000FF)
	(DSU_CID3) MASK Register

Detailed Description

Component description for DSU.

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Definition in file dsu.h.

Data Structures

Macros

Detailed Description