Instance description for CAN0. More...

Macros
#define	REG_CAN0_CREL ((RoReg )0x42000000UL)
	(CAN0) Core Release

#define	REG_CAN0_ENDN ((RoReg )0x42000004UL)
	(CAN0) Endian

#define	REG_CAN0_MRCFG ((RwReg )0x42000008UL)
	(CAN0) Message RAM Configuration

#define	REG_CAN0_DBTP ((RwReg )0x4200000CUL)
	(CAN0) Fast Bit Timing and Prescaler

#define	REG_CAN0_TEST ((RwReg )0x42000010UL)
	(CAN0) Test

#define	REG_CAN0_RWD ((RwReg )0x42000014UL)
	(CAN0) RAM Watchdog

#define	REG_CAN0_CCCR ((RwReg )0x42000018UL)
	(CAN0) CC Control

#define	REG_CAN0_NBTP ((RwReg )0x4200001CUL)
	(CAN0) Nominal Bit Timing and Prescaler

#define	REG_CAN0_TSCC ((RwReg )0x42000020UL)
	(CAN0) Timestamp Counter Configuration

#define	REG_CAN0_TSCV ((RoReg )0x42000024UL)
	(CAN0) Timestamp Counter Value

#define	REG_CAN0_TOCC ((RwReg )0x42000028UL)
	(CAN0) Timeout Counter Configuration

#define	REG_CAN0_TOCV ((RwReg )0x4200002CUL)
	(CAN0) Timeout Counter Value

#define	REG_CAN0_ECR ((RoReg )0x42000040UL)
	(CAN0) Error Counter

#define	REG_CAN0_PSR ((RoReg )0x42000044UL)
	(CAN0) Protocol Status

#define	REG_CAN0_TDCR ((RwReg )0x42000048UL)
	(CAN0) Extended ID Filter Configuration

#define	REG_CAN0_IR ((RwReg )0x42000050UL)
	(CAN0) Interrupt

#define	REG_CAN0_IE ((RwReg )0x42000054UL)
	(CAN0) Interrupt Enable

#define	REG_CAN0_ILS ((RwReg )0x42000058UL)
	(CAN0) Interrupt Line Select

#define	REG_CAN0_ILE ((RwReg )0x4200005CUL)
	(CAN0) Interrupt Line Enable

#define	REG_CAN0_GFC ((RwReg )0x42000080UL)
	(CAN0) Global Filter Configuration

#define	REG_CAN0_SIDFC ((RwReg )0x42000084UL)
	(CAN0) Standard ID Filter Configuration

#define	REG_CAN0_XIDFC ((RwReg )0x42000088UL)
	(CAN0) Extended ID Filter Configuration

#define	REG_CAN0_XIDAM ((RwReg )0x42000090UL)
	(CAN0) Extended ID AND Mask

#define	REG_CAN0_HPMS ((RoReg )0x42000094UL)
	(CAN0) High Priority Message Status

#define	REG_CAN0_NDAT1 ((RwReg )0x42000098UL)
	(CAN0) New Data 1

#define	REG_CAN0_NDAT2 ((RwReg )0x4200009CUL)
	(CAN0) New Data 2

#define	REG_CAN0_RXF0C ((RwReg )0x420000A0UL)
	(CAN0) Rx FIFO 0 Configuration

#define	REG_CAN0_RXF0S ((RoReg )0x420000A4UL)
	(CAN0) Rx FIFO 0 Status

#define	REG_CAN0_RXF0A ((RwReg )0x420000A8UL)
	(CAN0) Rx FIFO 0 Acknowledge

#define	REG_CAN0_RXBC ((RwReg )0x420000ACUL)
	(CAN0) Rx Buffer Configuration

#define	REG_CAN0_RXF1C ((RwReg )0x420000B0UL)
	(CAN0) Rx FIFO 1 Configuration

#define	REG_CAN0_RXF1S ((RoReg )0x420000B4UL)
	(CAN0) Rx FIFO 1 Status

#define	REG_CAN0_RXF1A ((RwReg )0x420000B8UL)
	(CAN0) Rx FIFO 1 Acknowledge

#define	REG_CAN0_RXESC ((RwReg )0x420000BCUL)
	(CAN0) Rx Buffer / FIFO Element Size Configuration

#define	REG_CAN0_TXBC ((RwReg )0x420000C0UL)
	(CAN0) Tx Buffer Configuration

#define	REG_CAN0_TXFQS ((RoReg )0x420000C4UL)
	(CAN0) Tx FIFO / Queue Status

#define	REG_CAN0_TXESC ((RwReg )0x420000C8UL)
	(CAN0) Tx Buffer Element Size Configuration

#define	REG_CAN0_TXBRP ((RoReg )0x420000CCUL)
	(CAN0) Tx Buffer Request Pending

#define	REG_CAN0_TXBAR ((RwReg )0x420000D0UL)
	(CAN0) Tx Buffer Add Request

#define	REG_CAN0_TXBCR ((RwReg )0x420000D4UL)
	(CAN0) Tx Buffer Cancellation Request

#define	REG_CAN0_TXBTO ((RoReg )0x420000D8UL)
	(CAN0) Tx Buffer Transmission Occurred

#define	REG_CAN0_TXBCF ((RoReg )0x420000DCUL)
	(CAN0) Tx Buffer Cancellation Finished

#define	REG_CAN0_TXBTIE ((RwReg )0x420000E0UL)
	(CAN0) Tx Buffer Transmission Interrupt Enable

#define	REG_CAN0_TXBCIE ((RwReg )0x420000E4UL)
	(CAN0) Tx Buffer Cancellation Finished Interrupt Enable

#define	REG_CAN0_TXEFC ((RwReg )0x420000F0UL)
	(CAN0) Tx Event FIFO Configuration

#define	REG_CAN0_TXEFS ((RoReg )0x420000F4UL)
	(CAN0) Tx Event FIFO Status

#define	REG_CAN0_TXEFA ((RwReg )0x420000F8UL)
	(CAN0) Tx Event FIFO Acknowledge

#define	CAN0_CLK_AHB_ID 17

#define	CAN0_DMAC_ID_DEBUG 20

#define	CAN0_GCLK_ID 27

#define	CAN0_MSG_RAM_ADDR 0x20000000

#define	CAN0_QOS_RESET_VAL 1

Detailed Description

Instance description for CAN0.

\asf_license_start

Definition in file can0.h.

Macros

Detailed Description