adc.h

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#ifndef _SAME54_ADC_COMPONENT_
#define _SAME54_ADC_COMPONENT_
 
/* ========================================================================== */
/* ========================================================================== */
 
#define ADC_U2500
#define REV_ADC                     0x100
 
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t SWRST:1;          
    uint16_t ENABLE:1;         
    uint16_t :1;               
    uint16_t DUALSEL:2;        
    uint16_t SLAVEEN:1;        
    uint16_t RUNSTDBY:1;       
    uint16_t ONDEMAND:1;       
    uint16_t PRESCALER:3;      
    uint16_t :4;               
    uint16_t R2R:1;            
  } bit;                       
  uint16_t reg;                
} ADC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_CTRLA_OFFSET            0x00         
#define ADC_CTRLA_RESETVALUE        _U_(0x0000)  
#define ADC_CTRLA_SWRST_Pos         0            
#define ADC_CTRLA_SWRST             (_U_(0x1) << ADC_CTRLA_SWRST_Pos)
#define ADC_CTRLA_ENABLE_Pos        1            
#define ADC_CTRLA_ENABLE            (_U_(0x1) << ADC_CTRLA_ENABLE_Pos)
#define ADC_CTRLA_DUALSEL_Pos       3            
#define ADC_CTRLA_DUALSEL_Msk       (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos)
#define ADC_CTRLA_DUALSEL(value)    (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos))
#define   ADC_CTRLA_DUALSEL_BOTH_Val      _U_(0x0)   
#define   ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1)   
#define ADC_CTRLA_DUALSEL_BOTH      (ADC_CTRLA_DUALSEL_BOTH_Val    << ADC_CTRLA_DUALSEL_Pos)
#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos)
#define ADC_CTRLA_SLAVEEN_Pos       5            
#define ADC_CTRLA_SLAVEEN           (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos)
#define ADC_CTRLA_RUNSTDBY_Pos      6            
#define ADC_CTRLA_RUNSTDBY          (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
#define ADC_CTRLA_ONDEMAND_Pos      7            
#define ADC_CTRLA_ONDEMAND          (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos)
#define ADC_CTRLA_PRESCALER_Pos     8            
#define ADC_CTRLA_PRESCALER_Msk     (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER(value)  (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos))
#define   ADC_CTRLA_PRESCALER_DIV2_Val    _U_(0x0)   
#define   ADC_CTRLA_PRESCALER_DIV4_Val    _U_(0x1)   
#define   ADC_CTRLA_PRESCALER_DIV8_Val    _U_(0x2)   
#define   ADC_CTRLA_PRESCALER_DIV16_Val   _U_(0x3)   
#define   ADC_CTRLA_PRESCALER_DIV32_Val   _U_(0x4)   
#define   ADC_CTRLA_PRESCALER_DIV64_Val   _U_(0x5)   
#define   ADC_CTRLA_PRESCALER_DIV128_Val  _U_(0x6)   
#define   ADC_CTRLA_PRESCALER_DIV256_Val  _U_(0x7)   
#define ADC_CTRLA_PRESCALER_DIV2    (ADC_CTRLA_PRESCALER_DIV2_Val  << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV4    (ADC_CTRLA_PRESCALER_DIV4_Val  << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV8    (ADC_CTRLA_PRESCALER_DIV8_Val  << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV16   (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV32   (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV64   (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV128  (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV256  (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_R2R_Pos           15           
#define ADC_CTRLA_R2R               (_U_(0x1) << ADC_CTRLA_R2R_Pos)
#define ADC_CTRLA_MASK              _U_(0x87FB)  
/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W  8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  FLUSHEI:1;        
    uint8_t  STARTEI:1;        
    uint8_t  FLUSHINV:1;       
    uint8_t  STARTINV:1;       
    uint8_t  RESRDYEO:1;       
    uint8_t  WINMONEO:1;       
    uint8_t  :2;               
  } bit;                       
  uint8_t reg;                 
} ADC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_EVCTRL_OFFSET           0x02         
#define ADC_EVCTRL_RESETVALUE       _U_(0x00)    
#define ADC_EVCTRL_FLUSHEI_Pos      0            
#define ADC_EVCTRL_FLUSHEI          (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos)
#define ADC_EVCTRL_STARTEI_Pos      1            
#define ADC_EVCTRL_STARTEI          (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos)
#define ADC_EVCTRL_FLUSHINV_Pos     2            
#define ADC_EVCTRL_FLUSHINV         (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos)
#define ADC_EVCTRL_STARTINV_Pos     3            
#define ADC_EVCTRL_STARTINV         (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos)
#define ADC_EVCTRL_RESRDYEO_Pos     4            
#define ADC_EVCTRL_RESRDYEO         (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
#define ADC_EVCTRL_WINMONEO_Pos     5            
#define ADC_EVCTRL_WINMONEO         (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos)
#define ADC_EVCTRL_MASK             _U_(0x3F)    
/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W  8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  DBGRUN:1;         
    uint8_t  :7;               
  } bit;                       
  uint8_t reg;                 
} ADC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_DBGCTRL_OFFSET          0x03         
#define ADC_DBGCTRL_RESETVALUE      _U_(0x00)    
#define ADC_DBGCTRL_DBGRUN_Pos      0            
#define ADC_DBGCTRL_DBGRUN          (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
#define ADC_DBGCTRL_MASK            _U_(0x01)    
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t MUXPOS:5;         
    uint16_t :2;               
    uint16_t DIFFMODE:1;       
    uint16_t MUXNEG:5;         
    uint16_t :2;               
    uint16_t DSEQSTOP:1;       
  } bit;                       
  uint16_t reg;                
} ADC_INPUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_INPUTCTRL_OFFSET        0x04         
#define ADC_INPUTCTRL_RESETVALUE    _U_(0x0000)  
#define ADC_INPUTCTRL_MUXPOS_Pos    0            
#define ADC_INPUTCTRL_MUXPOS_Msk    (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
#define   ADC_INPUTCTRL_MUXPOS_AIN0_Val   _U_(0x0)   
#define   ADC_INPUTCTRL_MUXPOS_AIN1_Val   _U_(0x1)   
#define   ADC_INPUTCTRL_MUXPOS_AIN2_Val   _U_(0x2)   
#define   ADC_INPUTCTRL_MUXPOS_AIN3_Val   _U_(0x3)   
#define   ADC_INPUTCTRL_MUXPOS_AIN4_Val   _U_(0x4)   
#define   ADC_INPUTCTRL_MUXPOS_AIN5_Val   _U_(0x5)   
#define   ADC_INPUTCTRL_MUXPOS_AIN6_Val   _U_(0x6)   
#define   ADC_INPUTCTRL_MUXPOS_AIN7_Val   _U_(0x7)   
#define   ADC_INPUTCTRL_MUXPOS_AIN8_Val   _U_(0x8)   
#define   ADC_INPUTCTRL_MUXPOS_AIN9_Val   _U_(0x9)   
#define   ADC_INPUTCTRL_MUXPOS_AIN10_Val  _U_(0xA)   
#define   ADC_INPUTCTRL_MUXPOS_AIN11_Val  _U_(0xB)   
#define   ADC_INPUTCTRL_MUXPOS_AIN12_Val  _U_(0xC)   
#define   ADC_INPUTCTRL_MUXPOS_AIN13_Val  _U_(0xD)   
#define   ADC_INPUTCTRL_MUXPOS_AIN14_Val  _U_(0xE)   
#define   ADC_INPUTCTRL_MUXPOS_AIN15_Val  _U_(0xF)   
#define   ADC_INPUTCTRL_MUXPOS_AIN16_Val  _U_(0x10)   
#define   ADC_INPUTCTRL_MUXPOS_AIN17_Val  _U_(0x11)   
#define   ADC_INPUTCTRL_MUXPOS_AIN18_Val  _U_(0x12)   
#define   ADC_INPUTCTRL_MUXPOS_AIN19_Val  _U_(0x13)   
#define   ADC_INPUTCTRL_MUXPOS_AIN20_Val  _U_(0x14)   
#define   ADC_INPUTCTRL_MUXPOS_AIN21_Val  _U_(0x15)   
#define   ADC_INPUTCTRL_MUXPOS_AIN22_Val  _U_(0x16)   
#define   ADC_INPUTCTRL_MUXPOS_AIN23_Val  _U_(0x17)   
#define   ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18)   
#define   ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19)   
#define   ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A)   
#define   ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B)   
#define   ADC_INPUTCTRL_MUXPOS_PTAT_Val   _U_(0x1C)   
#define   ADC_INPUTCTRL_MUXPOS_CTAT_Val   _U_(0x1D)   
#define   ADC_INPUTCTRL_MUXPOS_DAC_Val    _U_(0x1E)   
#define   ADC_INPUTCTRL_MUXPOS_PTC_Val    _U_(0x1F)   
#define ADC_INPUTCTRL_MUXPOS_AIN0   (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN1   (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN2   (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN3   (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN4   (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN5   (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN6   (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN7   (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN8   (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN9   (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN10  (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN11  (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN12  (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN13  (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN14  (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN15  (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN16  (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN17  (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN18  (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN19  (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN20  (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN21  (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN22  (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN23  (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PTAT   (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_CTAT   (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_DAC    (ADC_INPUTCTRL_MUXPOS_DAC_Val  << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PTC    (ADC_INPUTCTRL_MUXPOS_PTC_Val  << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_DIFFMODE_Pos  7            
#define ADC_INPUTCTRL_DIFFMODE      (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos)
#define ADC_INPUTCTRL_MUXNEG_Pos    8            
#define ADC_INPUTCTRL_MUXNEG_Msk    (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
#define   ADC_INPUTCTRL_MUXNEG_AIN0_Val   _U_(0x0)   
#define   ADC_INPUTCTRL_MUXNEG_AIN1_Val   _U_(0x1)   
#define   ADC_INPUTCTRL_MUXNEG_AIN2_Val   _U_(0x2)   
#define   ADC_INPUTCTRL_MUXNEG_AIN3_Val   _U_(0x3)   
#define   ADC_INPUTCTRL_MUXNEG_AIN4_Val   _U_(0x4)   
#define   ADC_INPUTCTRL_MUXNEG_AIN5_Val   _U_(0x5)   
#define   ADC_INPUTCTRL_MUXNEG_AIN6_Val   _U_(0x6)   
#define   ADC_INPUTCTRL_MUXNEG_AIN7_Val   _U_(0x7)   
#define   ADC_INPUTCTRL_MUXNEG_GND_Val    _U_(0x18)   
#define ADC_INPUTCTRL_MUXNEG_AIN0   (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN1   (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN2   (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN3   (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN4   (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN5   (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN6   (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN7   (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_GND    (ADC_INPUTCTRL_MUXNEG_GND_Val  << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_DSEQSTOP_Pos  15           
#define ADC_INPUTCTRL_DSEQSTOP      (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos)
#define ADC_INPUTCTRL_MASK          _U_(0x9F9F)  
/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t LEFTADJ:1;        
    uint16_t FREERUN:1;        
    uint16_t CORREN:1;         
    uint16_t RESSEL:2;         
    uint16_t :3;               
    uint16_t WINMODE:3;        
    uint16_t WINSS:1;          
    uint16_t :4;               
  } bit;                       
  uint16_t reg;                
} ADC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_CTRLB_OFFSET            0x06         
#define ADC_CTRLB_RESETVALUE        _U_(0x0000)  
#define ADC_CTRLB_LEFTADJ_Pos       0            
#define ADC_CTRLB_LEFTADJ           (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos)
#define ADC_CTRLB_FREERUN_Pos       1            
#define ADC_CTRLB_FREERUN           (_U_(0x1) << ADC_CTRLB_FREERUN_Pos)
#define ADC_CTRLB_CORREN_Pos        2            
#define ADC_CTRLB_CORREN            (_U_(0x1) << ADC_CTRLB_CORREN_Pos)
#define ADC_CTRLB_RESSEL_Pos        3            
#define ADC_CTRLB_RESSEL_Msk        (_U_(0x3) << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_RESSEL(value)     (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
#define   ADC_CTRLB_RESSEL_12BIT_Val      _U_(0x0)   
#define   ADC_CTRLB_RESSEL_16BIT_Val      _U_(0x1)   
#define   ADC_CTRLB_RESSEL_10BIT_Val      _U_(0x2)   
#define   ADC_CTRLB_RESSEL_8BIT_Val       _U_(0x3)   
#define ADC_CTRLB_RESSEL_12BIT      (ADC_CTRLB_RESSEL_12BIT_Val    << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_RESSEL_16BIT      (ADC_CTRLB_RESSEL_16BIT_Val    << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_RESSEL_10BIT      (ADC_CTRLB_RESSEL_10BIT_Val    << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_RESSEL_8BIT       (ADC_CTRLB_RESSEL_8BIT_Val     << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_WINMODE_Pos       8            
#define ADC_CTRLB_WINMODE_Msk       (_U_(0x7) << ADC_CTRLB_WINMODE_Pos)
#define ADC_CTRLB_WINMODE(value)    (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos))
#define   ADC_CTRLB_WINMODE_DISABLE_Val   _U_(0x0)   
#define   ADC_CTRLB_WINMODE_MODE1_Val     _U_(0x1)   
#define   ADC_CTRLB_WINMODE_MODE2_Val     _U_(0x2)   
#define   ADC_CTRLB_WINMODE_MODE3_Val     _U_(0x3)   
#define   ADC_CTRLB_WINMODE_MODE4_Val     _U_(0x4)   
#define ADC_CTRLB_WINMODE_DISABLE   (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos)
#define ADC_CTRLB_WINMODE_MODE1     (ADC_CTRLB_WINMODE_MODE1_Val   << ADC_CTRLB_WINMODE_Pos)
#define ADC_CTRLB_WINMODE_MODE2     (ADC_CTRLB_WINMODE_MODE2_Val   << ADC_CTRLB_WINMODE_Pos)
#define ADC_CTRLB_WINMODE_MODE3     (ADC_CTRLB_WINMODE_MODE3_Val   << ADC_CTRLB_WINMODE_Pos)
#define ADC_CTRLB_WINMODE_MODE4     (ADC_CTRLB_WINMODE_MODE4_Val   << ADC_CTRLB_WINMODE_Pos)
#define ADC_CTRLB_WINSS_Pos         11           
#define ADC_CTRLB_WINSS             (_U_(0x1) << ADC_CTRLB_WINSS_Pos)
#define ADC_CTRLB_MASK              _U_(0x0F1F)  
/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W  8) Reference Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  REFSEL:4;         
    uint8_t  :3;               
    uint8_t  REFCOMP:1;        
  } bit;                       
  uint8_t reg;                 
} ADC_REFCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_REFCTRL_OFFSET          0x08         
#define ADC_REFCTRL_RESETVALUE      _U_(0x00)    
#define ADC_REFCTRL_REFSEL_Pos      0            
#define ADC_REFCTRL_REFSEL_Msk      (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL(value)   (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
#define   ADC_REFCTRL_REFSEL_INTREF_Val   _U_(0x0)   
#define   ADC_REFCTRL_REFSEL_INTVCC0_Val  _U_(0x2)   
#define   ADC_REFCTRL_REFSEL_INTVCC1_Val  _U_(0x3)   
#define   ADC_REFCTRL_REFSEL_AREFA_Val    _U_(0x4)   
#define   ADC_REFCTRL_REFSEL_AREFB_Val    _U_(0x5)   
#define   ADC_REFCTRL_REFSEL_AREFC_Val    _U_(0x6)   
#define ADC_REFCTRL_REFSEL_INTREF   (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_INTVCC0  (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_INTVCC1  (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_AREFA    (ADC_REFCTRL_REFSEL_AREFA_Val  << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_AREFB    (ADC_REFCTRL_REFSEL_AREFB_Val  << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_AREFC    (ADC_REFCTRL_REFSEL_AREFC_Val  << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFCOMP_Pos     7            
#define ADC_REFCTRL_REFCOMP         (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos)
#define ADC_REFCTRL_MASK            _U_(0x8F)    
/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W  8) Average Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  SAMPLENUM:4;      
    uint8_t  ADJRES:3;         
    uint8_t  :1;               
  } bit;                       
  uint8_t reg;                 
} ADC_AVGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_AVGCTRL_OFFSET          0x0A         
#define ADC_AVGCTRL_RESETVALUE      _U_(0x00)    
#define ADC_AVGCTRL_SAMPLENUM_Pos   0            
#define ADC_AVGCTRL_SAMPLENUM_Msk   (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
#define   ADC_AVGCTRL_SAMPLENUM_1_Val     _U_(0x0)   
#define   ADC_AVGCTRL_SAMPLENUM_2_Val     _U_(0x1)   
#define   ADC_AVGCTRL_SAMPLENUM_4_Val     _U_(0x2)   
#define   ADC_AVGCTRL_SAMPLENUM_8_Val     _U_(0x3)   
#define   ADC_AVGCTRL_SAMPLENUM_16_Val    _U_(0x4)   
#define   ADC_AVGCTRL_SAMPLENUM_32_Val    _U_(0x5)   
#define   ADC_AVGCTRL_SAMPLENUM_64_Val    _U_(0x6)   
#define   ADC_AVGCTRL_SAMPLENUM_128_Val   _U_(0x7)   
#define   ADC_AVGCTRL_SAMPLENUM_256_Val   _U_(0x8)   
#define   ADC_AVGCTRL_SAMPLENUM_512_Val   _U_(0x9)   
#define   ADC_AVGCTRL_SAMPLENUM_1024_Val  _U_(0xA)   
#define ADC_AVGCTRL_SAMPLENUM_1     (ADC_AVGCTRL_SAMPLENUM_1_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_2     (ADC_AVGCTRL_SAMPLENUM_2_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_4     (ADC_AVGCTRL_SAMPLENUM_4_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_8     (ADC_AVGCTRL_SAMPLENUM_8_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_16    (ADC_AVGCTRL_SAMPLENUM_16_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_32    (ADC_AVGCTRL_SAMPLENUM_32_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_64    (ADC_AVGCTRL_SAMPLENUM_64_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_128   (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_256   (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_512   (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_1024  (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_ADJRES_Pos      4            
#define ADC_AVGCTRL_ADJRES_Msk      (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos)
#define ADC_AVGCTRL_ADJRES(value)   (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
#define ADC_AVGCTRL_MASK            _U_(0x7F)    
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W  8) Sample Time Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  SAMPLEN:6;        
    uint8_t  :1;               
    uint8_t  OFFCOMP:1;        
  } bit;                       
  uint8_t reg;                 
} ADC_SAMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_SAMPCTRL_OFFSET         0x0B         
#define ADC_SAMPCTRL_RESETVALUE     _U_(0x00)    
#define ADC_SAMPCTRL_SAMPLEN_Pos    0            
#define ADC_SAMPCTRL_SAMPLEN_Msk    (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
#define ADC_SAMPCTRL_OFFCOMP_Pos    7            
#define ADC_SAMPCTRL_OFFCOMP        (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos)
#define ADC_SAMPCTRL_MASK           _U_(0xBF)    
/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t WINLT:16;         
  } bit;                       
  uint16_t reg;                
} ADC_WINLT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_WINLT_OFFSET            0x0C         
#define ADC_WINLT_RESETVALUE        _U_(0x0000)  
#define ADC_WINLT_WINLT_Pos         0            
#define ADC_WINLT_WINLT_Msk         (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos)
#define ADC_WINLT_WINLT(value)      (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
#define ADC_WINLT_MASK              _U_(0xFFFF)  
/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t WINUT:16;         
  } bit;                       
  uint16_t reg;                
} ADC_WINUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_WINUT_OFFSET            0x0E         
#define ADC_WINUT_RESETVALUE        _U_(0x0000)  
#define ADC_WINUT_WINUT_Pos         0            
#define ADC_WINUT_WINUT_Msk         (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos)
#define ADC_WINUT_WINUT(value)      (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
#define ADC_WINUT_MASK              _U_(0xFFFF)  
/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t GAINCORR:12;      
    uint16_t :4;               
  } bit;                       
  uint16_t reg;                
} ADC_GAINCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_GAINCORR_OFFSET         0x10         
#define ADC_GAINCORR_RESETVALUE     _U_(0x0000)  
#define ADC_GAINCORR_GAINCORR_Pos   0            
#define ADC_GAINCORR_GAINCORR_Msk   (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
#define ADC_GAINCORR_MASK           _U_(0x0FFF)  
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t OFFSETCORR:12;    
    uint16_t :4;               
  } bit;                       
  uint16_t reg;                
} ADC_OFFSETCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_OFFSETCORR_OFFSET       0x12         
#define ADC_OFFSETCORR_RESETVALUE   _U_(0x0000)  
#define ADC_OFFSETCORR_OFFSETCORR_Pos 0            
#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
#define ADC_OFFSETCORR_MASK         _U_(0x0FFF)  
/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W  8) Software Trigger -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  FLUSH:1;          
    uint8_t  START:1;          
    uint8_t  :6;               
  } bit;                       
  uint8_t reg;                 
} ADC_SWTRIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_SWTRIG_OFFSET           0x14         
#define ADC_SWTRIG_RESETVALUE       _U_(0x00)    
#define ADC_SWTRIG_FLUSH_Pos        0            
#define ADC_SWTRIG_FLUSH            (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos)
#define ADC_SWTRIG_START_Pos        1            
#define ADC_SWTRIG_START            (_U_(0x1) << ADC_SWTRIG_START_Pos)
#define ADC_SWTRIG_MASK             _U_(0x03)    
/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W  8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  RESRDY:1;         
    uint8_t  OVERRUN:1;        
    uint8_t  WINMON:1;         
    uint8_t  :5;               
  } bit;                       
  uint8_t reg;                 
} ADC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_INTENCLR_OFFSET         0x2C         
#define ADC_INTENCLR_RESETVALUE     _U_(0x00)    
#define ADC_INTENCLR_RESRDY_Pos     0            
#define ADC_INTENCLR_RESRDY         (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos)
#define ADC_INTENCLR_OVERRUN_Pos    1            
#define ADC_INTENCLR_OVERRUN        (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos)
#define ADC_INTENCLR_WINMON_Pos     2            
#define ADC_INTENCLR_WINMON         (_U_(0x1) << ADC_INTENCLR_WINMON_Pos)
#define ADC_INTENCLR_MASK           _U_(0x07)    
/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W  8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  RESRDY:1;         
    uint8_t  OVERRUN:1;        
    uint8_t  WINMON:1;         
    uint8_t  :5;               
  } bit;                       
  uint8_t reg;                 
} ADC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_INTENSET_OFFSET         0x2D         
#define ADC_INTENSET_RESETVALUE     _U_(0x00)    
#define ADC_INTENSET_RESRDY_Pos     0            
#define ADC_INTENSET_RESRDY         (_U_(0x1) << ADC_INTENSET_RESRDY_Pos)
#define ADC_INTENSET_OVERRUN_Pos    1            
#define ADC_INTENSET_OVERRUN        (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos)
#define ADC_INTENSET_WINMON_Pos     2            
#define ADC_INTENSET_WINMON         (_U_(0x1) << ADC_INTENSET_WINMON_Pos)
#define ADC_INTENSET_MASK           _U_(0x07)    
/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W  8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
  struct {
    __I uint8_t  RESRDY:1;         
    __I uint8_t  OVERRUN:1;        
    __I uint8_t  WINMON:1;         
    __I uint8_t  :5;               
  } bit;                       
  uint8_t reg;                 
} ADC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_INTFLAG_OFFSET          0x2E         
#define ADC_INTFLAG_RESETVALUE      _U_(0x00)    
#define ADC_INTFLAG_RESRDY_Pos      0            
#define ADC_INTFLAG_RESRDY          (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos)
#define ADC_INTFLAG_OVERRUN_Pos     1            
#define ADC_INTFLAG_OVERRUN         (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos)
#define ADC_INTFLAG_WINMON_Pos      2            
#define ADC_INTFLAG_WINMON          (_U_(0x1) << ADC_INTFLAG_WINMON_Pos)
#define ADC_INTFLAG_MASK            _U_(0x07)    
/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/   8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  ADCBUSY:1;        
    uint8_t  :1;               
    uint8_t  WCC:6;            
  } bit;                       
  uint8_t reg;                 
} ADC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_STATUS_OFFSET           0x2F         
#define ADC_STATUS_RESETVALUE       _U_(0x00)    
#define ADC_STATUS_ADCBUSY_Pos      0            
#define ADC_STATUS_ADCBUSY          (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos)
#define ADC_STATUS_WCC_Pos          2            
#define ADC_STATUS_WCC_Msk          (_U_(0x3F) << ADC_STATUS_WCC_Pos)
#define ADC_STATUS_WCC(value)       (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos))
#define ADC_STATUS_MASK             _U_(0xFD)    
/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/  32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t SWRST:1;          
    uint32_t ENABLE:1;         
    uint32_t INPUTCTRL:1;      
    uint32_t CTRLB:1;          
    uint32_t REFCTRL:1;        
    uint32_t AVGCTRL:1;        
    uint32_t SAMPCTRL:1;       
    uint32_t WINLT:1;          
    uint32_t WINUT:1;          
    uint32_t GAINCORR:1;       
    uint32_t OFFSETCORR:1;     
    uint32_t SWTRIG:1;         
    uint32_t :20;              
  } bit;                       
  uint32_t reg;                
} ADC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_SYNCBUSY_OFFSET         0x30         
#define ADC_SYNCBUSY_RESETVALUE     _U_(0x00000000) 
#define ADC_SYNCBUSY_SWRST_Pos      0            
#define ADC_SYNCBUSY_SWRST          (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos)
#define ADC_SYNCBUSY_ENABLE_Pos     1            
#define ADC_SYNCBUSY_ENABLE         (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos)
#define ADC_SYNCBUSY_INPUTCTRL_Pos  2            
#define ADC_SYNCBUSY_INPUTCTRL      (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos)
#define ADC_SYNCBUSY_CTRLB_Pos      3            
#define ADC_SYNCBUSY_CTRLB          (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos)
#define ADC_SYNCBUSY_REFCTRL_Pos    4            
#define ADC_SYNCBUSY_REFCTRL        (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos)
#define ADC_SYNCBUSY_AVGCTRL_Pos    5            
#define ADC_SYNCBUSY_AVGCTRL        (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos)
#define ADC_SYNCBUSY_SAMPCTRL_Pos   6            
#define ADC_SYNCBUSY_SAMPCTRL       (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos)
#define ADC_SYNCBUSY_WINLT_Pos      7            
#define ADC_SYNCBUSY_WINLT          (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos)
#define ADC_SYNCBUSY_WINUT_Pos      8            
#define ADC_SYNCBUSY_WINUT          (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos)
#define ADC_SYNCBUSY_GAINCORR_Pos   9            
#define ADC_SYNCBUSY_GAINCORR       (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos)
#define ADC_SYNCBUSY_OFFSETCORR_Pos 10           
#define ADC_SYNCBUSY_OFFSETCORR     (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos)
#define ADC_SYNCBUSY_SWTRIG_Pos     11           
#define ADC_SYNCBUSY_SWTRIG         (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos)
#define ADC_SYNCBUSY_MASK           _U_(0x00000FFF) 
/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t DATA:32;          
  } bit;                       
  uint32_t reg;                
} ADC_DSEQDATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_DSEQDATA_OFFSET         0x34         
#define ADC_DSEQDATA_RESETVALUE     _U_(0x00000000) 
#define ADC_DSEQDATA_DATA_Pos       0            
#define ADC_DSEQDATA_DATA_Msk       (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos)
#define ADC_DSEQDATA_DATA(value)    (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos))
#define ADC_DSEQDATA_MASK           _U_(0xFFFFFFFF) 
/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t INPUTCTRL:1;      
    uint32_t CTRLB:1;          
    uint32_t REFCTRL:1;        
    uint32_t AVGCTRL:1;        
    uint32_t SAMPCTRL:1;       
    uint32_t WINLT:1;          
    uint32_t WINUT:1;          
    uint32_t GAINCORR:1;       
    uint32_t OFFSETCORR:1;     
    uint32_t :22;              
    uint32_t AUTOSTART:1;      
  } bit;                       
  uint32_t reg;                
} ADC_DSEQCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_DSEQCTRL_OFFSET         0x38         
#define ADC_DSEQCTRL_RESETVALUE     _U_(0x00000000) 
#define ADC_DSEQCTRL_INPUTCTRL_Pos  0            
#define ADC_DSEQCTRL_INPUTCTRL      (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos)
#define ADC_DSEQCTRL_CTRLB_Pos      1            
#define ADC_DSEQCTRL_CTRLB          (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos)
#define ADC_DSEQCTRL_REFCTRL_Pos    2            
#define ADC_DSEQCTRL_REFCTRL        (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos)
#define ADC_DSEQCTRL_AVGCTRL_Pos    3            
#define ADC_DSEQCTRL_AVGCTRL        (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos)
#define ADC_DSEQCTRL_SAMPCTRL_Pos   4            
#define ADC_DSEQCTRL_SAMPCTRL       (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos)
#define ADC_DSEQCTRL_WINLT_Pos      5            
#define ADC_DSEQCTRL_WINLT          (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos)
#define ADC_DSEQCTRL_WINUT_Pos      6            
#define ADC_DSEQCTRL_WINUT          (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos)
#define ADC_DSEQCTRL_GAINCORR_Pos   7            
#define ADC_DSEQCTRL_GAINCORR       (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos)
#define ADC_DSEQCTRL_OFFSETCORR_Pos 8            
#define ADC_DSEQCTRL_OFFSETCORR     (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos)
#define ADC_DSEQCTRL_AUTOSTART_Pos  31           
#define ADC_DSEQCTRL_AUTOSTART      (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos)
#define ADC_DSEQCTRL_MASK           _U_(0x800001FF) 
/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/  32) DMA Sequencial Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t INPUTCTRL:1;      
    uint32_t CTRLB:1;          
    uint32_t REFCTRL:1;        
    uint32_t AVGCTRL:1;        
    uint32_t SAMPCTRL:1;       
    uint32_t WINLT:1;          
    uint32_t WINUT:1;          
    uint32_t GAINCORR:1;       
    uint32_t OFFSETCORR:1;     
    uint32_t :22;              
    uint32_t BUSY:1;           
  } bit;                       
  uint32_t reg;                
} ADC_DSEQSTAT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_DSEQSTAT_OFFSET         0x3C         
#define ADC_DSEQSTAT_RESETVALUE     _U_(0x00000000) 
#define ADC_DSEQSTAT_INPUTCTRL_Pos  0            
#define ADC_DSEQSTAT_INPUTCTRL      (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos)
#define ADC_DSEQSTAT_CTRLB_Pos      1            
#define ADC_DSEQSTAT_CTRLB          (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos)
#define ADC_DSEQSTAT_REFCTRL_Pos    2            
#define ADC_DSEQSTAT_REFCTRL        (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos)
#define ADC_DSEQSTAT_AVGCTRL_Pos    3            
#define ADC_DSEQSTAT_AVGCTRL        (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos)
#define ADC_DSEQSTAT_SAMPCTRL_Pos   4            
#define ADC_DSEQSTAT_SAMPCTRL       (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos)
#define ADC_DSEQSTAT_WINLT_Pos      5            
#define ADC_DSEQSTAT_WINLT          (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos)
#define ADC_DSEQSTAT_WINUT_Pos      6            
#define ADC_DSEQSTAT_WINUT          (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos)
#define ADC_DSEQSTAT_GAINCORR_Pos   7            
#define ADC_DSEQSTAT_GAINCORR       (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos)
#define ADC_DSEQSTAT_OFFSETCORR_Pos 8            
#define ADC_DSEQSTAT_OFFSETCORR     (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos)
#define ADC_DSEQSTAT_BUSY_Pos       31           
#define ADC_DSEQSTAT_BUSY           (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos)
#define ADC_DSEQSTAT_MASK           _U_(0x800001FF) 
/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/  16) Result Conversion Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t RESULT:16;        
  } bit;                       
  uint16_t reg;                
} ADC_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_RESULT_OFFSET           0x40         
#define ADC_RESULT_RESETVALUE       _U_(0x0000)  
#define ADC_RESULT_RESULT_Pos       0            
#define ADC_RESULT_RESULT_Msk       (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos)
#define ADC_RESULT_RESULT(value)    (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
#define ADC_RESULT_MASK             _U_(0xFFFF)  
/* -------- ADC_RESS : (ADC Offset: 0x44) (R/  16) Last Sample Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t RESS:16;          
  } bit;                       
  uint16_t reg;                
} ADC_RESS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_RESS_OFFSET             0x44         
#define ADC_RESS_RESETVALUE         _U_(0x0000)  
#define ADC_RESS_RESS_Pos           0            
#define ADC_RESS_RESS_Msk           (_U_(0xFFFF) << ADC_RESS_RESS_Pos)
#define ADC_RESS_RESS(value)        (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos))
#define ADC_RESS_MASK               _U_(0xFFFF)  
/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t BIASCOMP:3;       
    uint16_t :1;               
    uint16_t BIASR2R:3;        
    uint16_t :1;               
    uint16_t BIASREFBUF:3;     
    uint16_t :5;               
  } bit;                       
  uint16_t reg;                
} ADC_CALIB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#define ADC_CALIB_OFFSET            0x48         
#define ADC_CALIB_RESETVALUE        _U_(0x0000)  
#define ADC_CALIB_BIASCOMP_Pos      0            
#define ADC_CALIB_BIASCOMP_Msk      (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos)
#define ADC_CALIB_BIASCOMP(value)   (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))
#define ADC_CALIB_BIASR2R_Pos       4            
#define ADC_CALIB_BIASR2R_Msk       (_U_(0x7) << ADC_CALIB_BIASR2R_Pos)
#define ADC_CALIB_BIASR2R(value)    (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos))
#define ADC_CALIB_BIASREFBUF_Pos    8            
#define ADC_CALIB_BIASREFBUF_Msk    (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos)
#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))
#define ADC_CALIB_MASK              _U_(0x0777)  
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
  __IO ADC_CTRLA_Type            CTRLA;       
  __IO ADC_EVCTRL_Type           EVCTRL;      
  __IO ADC_DBGCTRL_Type          DBGCTRL;     
  __IO ADC_INPUTCTRL_Type        INPUTCTRL;   
  __IO ADC_CTRLB_Type            CTRLB;       
  __IO ADC_REFCTRL_Type          REFCTRL;     
       RoReg8                    Reserved1[0x1];
  __IO ADC_AVGCTRL_Type          AVGCTRL;     
  __IO ADC_SAMPCTRL_Type         SAMPCTRL;    
  __IO ADC_WINLT_Type            WINLT;       
  __IO ADC_WINUT_Type            WINUT;       
  __IO ADC_GAINCORR_Type         GAINCORR;    
  __IO ADC_OFFSETCORR_Type       OFFSETCORR;  
  __IO ADC_SWTRIG_Type           SWTRIG;      
       RoReg8                    Reserved2[0x17];
  __IO ADC_INTENCLR_Type         INTENCLR;    
  __IO ADC_INTENSET_Type         INTENSET;    
  __IO ADC_INTFLAG_Type          INTFLAG;     
  __I  ADC_STATUS_Type           STATUS;      
  __I  ADC_SYNCBUSY_Type         SYNCBUSY;    
  __O  ADC_DSEQDATA_Type         DSEQDATA;    
  __IO ADC_DSEQCTRL_Type         DSEQCTRL;    
  __I  ADC_DSEQSTAT_Type         DSEQSTAT;    
  __I  ADC_RESULT_Type           RESULT;      
       RoReg8                    Reserved3[0x2];
  __I  ADC_RESS_Type             RESS;        
       RoReg8                    Reserved4[0x2];
  __IO ADC_CALIB_Type            CALIB;       
} Adc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#endif /* _SAME54_ADC_COMPONENT_ */