adc1.h File Reference

Instance description for ADC1. More...

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Macros
#define	REG_ADC1_CTRLA   (*(RwReg16*)0x43002000UL)
	(ADC1) Control A
#define	REG_ADC1_EVCTRL   (*(RwReg8 *)0x43002002UL)
	(ADC1) Event Control
#define	REG_ADC1_DBGCTRL   (*(RwReg8 *)0x43002003UL)
	(ADC1) Debug Control
#define	REG_ADC1_INPUTCTRL   (*(RwReg16*)0x43002004UL)
	(ADC1) Input Control
#define	REG_ADC1_CTRLB   (*(RwReg16*)0x43002006UL)
	(ADC1) Control B
#define	REG_ADC1_REFCTRL   (*(RwReg8 *)0x43002008UL)
	(ADC1) Reference Control
#define	REG_ADC1_AVGCTRL   (*(RwReg8 *)0x4300200AUL)
	(ADC1) Average Control
#define	REG_ADC1_SAMPCTRL   (*(RwReg8 *)0x4300200BUL)
	(ADC1) Sample Time Control
#define	REG_ADC1_WINLT   (*(RwReg16*)0x4300200CUL)
	(ADC1) Window Monitor Lower Threshold
#define	REG_ADC1_WINUT   (*(RwReg16*)0x4300200EUL)
	(ADC1) Window Monitor Upper Threshold
#define	REG_ADC1_GAINCORR   (*(RwReg16*)0x43002010UL)
	(ADC1) Gain Correction
#define	REG_ADC1_OFFSETCORR   (*(RwReg16*)0x43002012UL)
	(ADC1) Offset Correction
#define	REG_ADC1_SWTRIG   (*(RwReg8 *)0x43002014UL)
	(ADC1) Software Trigger
#define	REG_ADC1_INTENCLR   (*(RwReg8 *)0x4300202CUL)
	(ADC1) Interrupt Enable Clear
#define	REG_ADC1_INTENSET   (*(RwReg8 *)0x4300202DUL)
	(ADC1) Interrupt Enable Set
#define	REG_ADC1_INTFLAG   (*(RwReg8 *)0x4300202EUL)
	(ADC1) Interrupt Flag Status and Clear
#define	REG_ADC1_STATUS   (*(RoReg8 *)0x4300202FUL)
	(ADC1) Status
#define	REG_ADC1_SYNCBUSY   (*(RoReg *)0x43002030UL)
	(ADC1) Synchronization Busy
#define	REG_ADC1_DSEQDATA   (*(WoReg *)0x43002034UL)
	(ADC1) DMA Sequencial Data
#define	REG_ADC1_DSEQCTRL   (*(RwReg *)0x43002038UL)
	(ADC1) DMA Sequential Control
#define	REG_ADC1_DSEQSTAT   (*(RoReg *)0x4300203CUL)
	(ADC1) DMA Sequencial Status
#define	REG_ADC1_RESULT   (*(RoReg16*)0x43002040UL)
	(ADC1) Result Conversion Value
#define	REG_ADC1_RESS   (*(RoReg16*)0x43002044UL)
	(ADC1) Last Sample Result
#define	REG_ADC1_CALIB   (*(RwReg16*)0x43002048UL)
	(ADC1) Calibration
#define	ADC1_BANDGAP   27
#define	ADC1_CTAT   29
#define	ADC1_DMAC_ID_RESRDY   70
#define	ADC1_DMAC_ID_SEQ   71
#define	ADC1_EXTCHANNEL_MSB   15
#define	ADC1_GCLK_ID   41
#define	ADC1_MASTER_SLAVE_MODE   2
#define	ADC1_OPAMP2   0
#define	ADC1_OPAMP01   0
#define	ADC1_PTAT   28
#define	ADC1_TOUCH_IMPLEMENTED   0
#define	ADC1_TOUCH_LINES_NUM   1

Detailed Description

Instance description for ADC1.

Copyright (c) 2019 Microchip Technology Inc.

\asf_license_start

Definition in file adc1.h.