SAME54P20A Test Project
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Instance description for TCC1. More...
Go to the source code of this file.
Macros | |
#define | REG_TCC1_CTRLA (*(RwReg *)0x41018000UL) |
(TCC1) Control A | |
#define | REG_TCC1_CTRLBCLR (*(RwReg8 *)0x41018004UL) |
(TCC1) Control B Clear | |
#define | REG_TCC1_CTRLBSET (*(RwReg8 *)0x41018005UL) |
(TCC1) Control B Set | |
#define | REG_TCC1_SYNCBUSY (*(RoReg *)0x41018008UL) |
(TCC1) Synchronization Busy | |
#define | REG_TCC1_FCTRLA (*(RwReg *)0x4101800CUL) |
(TCC1) Recoverable Fault A Configuration | |
#define | REG_TCC1_FCTRLB (*(RwReg *)0x41018010UL) |
(TCC1) Recoverable Fault B Configuration | |
#define | REG_TCC1_WEXCTRL (*(RwReg *)0x41018014UL) |
(TCC1) Waveform Extension Configuration | |
#define | REG_TCC1_DRVCTRL (*(RwReg *)0x41018018UL) |
(TCC1) Driver Control | |
#define | REG_TCC1_DBGCTRL (*(RwReg8 *)0x4101801EUL) |
(TCC1) Debug Control | |
#define | REG_TCC1_EVCTRL (*(RwReg *)0x41018020UL) |
(TCC1) Event Control | |
#define | REG_TCC1_INTENCLR (*(RwReg *)0x41018024UL) |
(TCC1) Interrupt Enable Clear | |
#define | REG_TCC1_INTENSET (*(RwReg *)0x41018028UL) |
(TCC1) Interrupt Enable Set | |
#define | REG_TCC1_INTFLAG (*(RwReg *)0x4101802CUL) |
(TCC1) Interrupt Flag Status and Clear | |
#define | REG_TCC1_STATUS (*(RwReg *)0x41018030UL) |
(TCC1) Status | |
#define | REG_TCC1_COUNT (*(RwReg *)0x41018034UL) |
(TCC1) Count | |
#define | REG_TCC1_PATT (*(RwReg16*)0x41018038UL) |
(TCC1) Pattern | |
#define | REG_TCC1_WAVE (*(RwReg *)0x4101803CUL) |
(TCC1) Waveform Control | |
#define | REG_TCC1_PER (*(RwReg *)0x41018040UL) |
(TCC1) Period | |
#define | REG_TCC1_CC0 (*(RwReg *)0x41018044UL) |
(TCC1) Compare and Capture 0 | |
#define | REG_TCC1_CC1 (*(RwReg *)0x41018048UL) |
(TCC1) Compare and Capture 1 | |
#define | REG_TCC1_CC2 (*(RwReg *)0x4101804CUL) |
(TCC1) Compare and Capture 2 | |
#define | REG_TCC1_CC3 (*(RwReg *)0x41018050UL) |
(TCC1) Compare and Capture 3 | |
#define | REG_TCC1_PATTBUF (*(RwReg16*)0x41018064UL) |
(TCC1) Pattern Buffer | |
#define | REG_TCC1_PERBUF (*(RwReg *)0x4101806CUL) |
(TCC1) Period Buffer | |
#define | REG_TCC1_CCBUF0 (*(RwReg *)0x41018070UL) |
(TCC1) Compare and Capture Buffer 0 | |
#define | REG_TCC1_CCBUF1 (*(RwReg *)0x41018074UL) |
(TCC1) Compare and Capture Buffer 1 | |
#define | REG_TCC1_CCBUF2 (*(RwReg *)0x41018078UL) |
(TCC1) Compare and Capture Buffer 2 | |
#define | REG_TCC1_CCBUF3 (*(RwReg *)0x4101807CUL) |
(TCC1) Compare and Capture Buffer 3 | |
#define | TCC1_CC_NUM 4 |
#define | TCC1_DITHERING 1 |
#define | TCC1_DMAC_ID_MC_0 30 |
#define | TCC1_DMAC_ID_MC_1 31 |
#define | TCC1_DMAC_ID_MC_2 32 |
#define | TCC1_DMAC_ID_MC_3 33 |
#define | TCC1_DMAC_ID_MC_LSB 30 |
#define | TCC1_DMAC_ID_MC_MSB 33 |
#define | TCC1_DMAC_ID_MC_SIZE 4 |
#define | TCC1_DMAC_ID_OVF 29 |
#define | TCC1_DTI 1 |
#define | TCC1_EXT 31 |
#define | TCC1_GCLK_ID 25 |
#define | TCC1_MASTER_SLAVE_MODE 2 |
#define | TCC1_OTMX 1 |
#define | TCC1_OW_NUM 8 |
#define | TCC1_PG 1 |
#define | TCC1_SIZE 24 |
#define | TCC1_SWAP 1 |
Instance description for TCC1.
Copyright (c) 2019 Microchip Technology Inc.
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Definition in file tcc1.h.