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<div class="header">
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Pdec Struct Reference</div> </div>
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<p>PDEC hardware registers.
<a href="structPdec.html#details">More...</a></p>
<p><code>#include <<a class="el" href="component_2pdec_8h_source.html">pdec.h</a>></code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:abbd37a7f83fe231552ea40b7a98b695e"><td class="memItemLeft" align="right" valign="top"><a id="abbd37a7f83fe231552ea40b7a98b695e"></a>
__IO <a class="el" href="unionPDEC__CTRLA__Type.html">PDEC_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#abbd37a7f83fe231552ea40b7a98b695e">CTRLA</a></td></tr>
<tr class="memdesc:abbd37a7f83fe231552ea40b7a98b695e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 32) Control A. <br /></td></tr>
<tr class="separator:abbd37a7f83fe231552ea40b7a98b695e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af7558c80275bb620e95eedc468e2937a"><td class="memItemLeft" align="right" valign="top"><a id="af7558c80275bb620e95eedc468e2937a"></a>
__IO <a class="el" href="unionPDEC__CTRLBCLR__Type.html">PDEC_CTRLBCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#af7558c80275bb620e95eedc468e2937a">CTRLBCLR</a></td></tr>
<tr class="memdesc:af7558c80275bb620e95eedc468e2937a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 8) Control B Clear. <br /></td></tr>
<tr class="separator:af7558c80275bb620e95eedc468e2937a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a79e2931566772274ab603cbfbe194a64"><td class="memItemLeft" align="right" valign="top"><a id="a79e2931566772274ab603cbfbe194a64"></a>
__IO <a class="el" href="unionPDEC__CTRLBSET__Type.html">PDEC_CTRLBSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#a79e2931566772274ab603cbfbe194a64">CTRLBSET</a></td></tr>
<tr class="memdesc:a79e2931566772274ab603cbfbe194a64"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x05 (R/W 8) Control B Set. <br /></td></tr>
<tr class="separator:a79e2931566772274ab603cbfbe194a64"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9a2d3727b9007cee9d73855cf3f97b61"><td class="memItemLeft" align="right" valign="top"><a id="a9a2d3727b9007cee9d73855cf3f97b61"></a>
__IO <a class="el" href="unionPDEC__EVCTRL__Type.html">PDEC_EVCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#a9a2d3727b9007cee9d73855cf3f97b61">EVCTRL</a></td></tr>
<tr class="memdesc:a9a2d3727b9007cee9d73855cf3f97b61"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x06 (R/W 16) Event Control. <br /></td></tr>
<tr class="separator:a9a2d3727b9007cee9d73855cf3f97b61"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3b944bd14fd26d2b3af5f69b35cbdf37"><td class="memItemLeft" align="right" valign="top"><a id="a3b944bd14fd26d2b3af5f69b35cbdf37"></a>
__IO <a class="el" href="unionPDEC__INTENCLR__Type.html">PDEC_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#a3b944bd14fd26d2b3af5f69b35cbdf37">INTENCLR</a></td></tr>
<tr class="memdesc:a3b944bd14fd26d2b3af5f69b35cbdf37"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 8) Interrupt Enable Clear. <br /></td></tr>
<tr class="separator:a3b944bd14fd26d2b3af5f69b35cbdf37"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9052561a41d34991ed1407878a52d58a"><td class="memItemLeft" align="right" valign="top"><a id="a9052561a41d34991ed1407878a52d58a"></a>
__IO <a class="el" href="unionPDEC__INTENSET__Type.html">PDEC_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#a9052561a41d34991ed1407878a52d58a">INTENSET</a></td></tr>
<tr class="memdesc:a9052561a41d34991ed1407878a52d58a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x09 (R/W 8) Interrupt Enable Set. <br /></td></tr>
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<tr class="memitem:a9b601eebe5b5bab912a13adef7e36ffb"><td class="memItemLeft" align="right" valign="top"><a id="a9b601eebe5b5bab912a13adef7e36ffb"></a>
__IO <a class="el" href="unionPDEC__INTFLAG__Type.html">PDEC_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#a9b601eebe5b5bab912a13adef7e36ffb">INTFLAG</a></td></tr>
<tr class="memdesc:a9b601eebe5b5bab912a13adef7e36ffb"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear. <br /></td></tr>
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<tr class="memitem:ac0b7be8c04f2b01a0d2677ffb94a5252"><td class="memItemLeft" align="right" valign="top"><a id="ac0b7be8c04f2b01a0d2677ffb94a5252"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x1]</td></tr>
<tr class="separator:ac0b7be8c04f2b01a0d2677ffb94a5252"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae4402c2c9ae1c89b44fe17f02e6a471f"><td class="memItemLeft" align="right" valign="top"><a id="ae4402c2c9ae1c89b44fe17f02e6a471f"></a>
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<tr class="memdesc:ae4402c2c9ae1c89b44fe17f02e6a471f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 16) Status. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x1]</td></tr>
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__IO <a class="el" href="unionPDEC__DBGCTRL__Type.html">PDEC_DBGCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#abdf566cec48944515787f62d8d059e47">DBGCTRL</a></td></tr>
<tr class="memdesc:abdf566cec48944515787f62d8d059e47"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0F (R/W 8) Debug Control. <br /></td></tr>
<tr class="separator:abdf566cec48944515787f62d8d059e47"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a15e9b6f761497f96a5d4f758de294e47"><td class="memItemLeft" align="right" valign="top"><a id="a15e9b6f761497f96a5d4f758de294e47"></a>
__I <a class="el" href="unionPDEC__SYNCBUSY__Type.html">PDEC_SYNCBUSY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#a15e9b6f761497f96a5d4f758de294e47">SYNCBUSY</a></td></tr>
<tr class="memdesc:a15e9b6f761497f96a5d4f758de294e47"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/ 32) Synchronization Status. <br /></td></tr>
<tr class="separator:a15e9b6f761497f96a5d4f758de294e47"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac518c41c0383cadf24605698d3303f19"><td class="memItemLeft" align="right" valign="top"><a id="ac518c41c0383cadf24605698d3303f19"></a>
__IO <a class="el" href="unionPDEC__PRESC__Type.html">PDEC_PRESC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#ac518c41c0383cadf24605698d3303f19">PRESC</a></td></tr>
<tr class="memdesc:ac518c41c0383cadf24605698d3303f19"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 8) Prescaler Value. <br /></td></tr>
<tr class="separator:ac518c41c0383cadf24605698d3303f19"><td class="memSeparator" colspan="2"> </td></tr>
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__IO <a class="el" href="unionPDEC__FILTER__Type.html">PDEC_FILTER_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#a3a3b3c5aec98674ae833b90964dd1877">FILTER</a></td></tr>
<tr class="memdesc:a3a3b3c5aec98674ae833b90964dd1877"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x15 (R/W 8) Filter Value. <br /></td></tr>
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<tr class="memitem:acb5617e141a14bc015cc1634d0cf0630"><td class="memItemLeft" align="right" valign="top"><a id="acb5617e141a14bc015cc1634d0cf0630"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x2]</td></tr>
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__IO <a class="el" href="unionPDEC__PRESCBUF__Type.html">PDEC_PRESCBUF_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#ac550ed3f472b474d415663f667462ccb">PRESCBUF</a></td></tr>
<tr class="memdesc:ac550ed3f472b474d415663f667462ccb"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x18 (R/W 8) Prescaler Buffer Value. <br /></td></tr>
<tr class="separator:ac550ed3f472b474d415663f667462ccb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac2e29f66b8c9c739ac70cddcbc296c1f"><td class="memItemLeft" align="right" valign="top"><a id="ac2e29f66b8c9c739ac70cddcbc296c1f"></a>
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<tr class="memdesc:ac2e29f66b8c9c739ac70cddcbc296c1f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x19 (R/W 8) Filter Buffer Value. <br /></td></tr>
<tr class="separator:ac2e29f66b8c9c739ac70cddcbc296c1f"><td class="memSeparator" colspan="2"> </td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved4</b> [0x2]</td></tr>
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__IO <a class="el" href="unionPDEC__COUNT__Type.html">PDEC_COUNT_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#a7883ce5294d10e0fa8c77b4a86421862">COUNT</a></td></tr>
<tr class="memdesc:a7883ce5294d10e0fa8c77b4a86421862"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1C (R/W 32) Counter Value. <br /></td></tr>
<tr class="separator:a7883ce5294d10e0fa8c77b4a86421862"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a74a36c168c7db41d3b5ff8fc51f67634"><td class="memItemLeft" align="right" valign="top"><a id="a74a36c168c7db41d3b5ff8fc51f67634"></a>
__IO <a class="el" href="unionPDEC__CC__Type.html">PDEC_CC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#a74a36c168c7db41d3b5ff8fc51f67634">CC</a> [2]</td></tr>
<tr class="memdesc:a74a36c168c7db41d3b5ff8fc51f67634"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x20 (R/W 32) Channel n Compare Value. <br /></td></tr>
<tr class="separator:a74a36c168c7db41d3b5ff8fc51f67634"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab245db72c38cbde9aa934b407dabdacd"><td class="memItemLeft" align="right" valign="top"><a id="ab245db72c38cbde9aa934b407dabdacd"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved5</b> [0x8]</td></tr>
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__IO <a class="el" href="unionPDEC__CCBUF__Type.html">PDEC_CCBUF_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPdec.html#a367f1abf31ffb859d96193a949a957cf">CCBUF</a> [2]</td></tr>
<tr class="memdesc:a367f1abf31ffb859d96193a949a957cf"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 (R/W 32) Channel Compare Buffer Value. <br /></td></tr>
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</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>PDEC hardware registers. </p>
<p class="definition">Definition at line <a class="el" href="component_2pdec_8h_source.html#l00698">698</a> of file <a class="el" href="component_2pdec_8h_source.html">pdec.h</a>.</p>
</div><hr/>The documentation for this struct was generated from the following file:<ul>
<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2pdec_8h_source.html">pdec.h</a></li>
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