SAME54P20A Test Project
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OSC32KCTRL hardware registers. More...
#include <osc32kctrl.h>
Data Fields | |
__IO OSC32KCTRL_INTENCLR_Type | INTENCLR |
Offset: 0x00 (R/W 32) Interrupt Enable Clear. | |
__IO OSC32KCTRL_INTENSET_Type | INTENSET |
Offset: 0x04 (R/W 32) Interrupt Enable Set. | |
__IO OSC32KCTRL_INTFLAG_Type | INTFLAG |
Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear. | |
__I OSC32KCTRL_STATUS_Type | STATUS |
Offset: 0x0C (R/ 32) Power and Clocks Status. | |
__IO OSC32KCTRL_RTCCTRL_Type | RTCCTRL |
Offset: 0x10 (R/W 8) RTC Clock Selection. | |
RoReg8 | Reserved1 [0x3] |
__IO OSC32KCTRL_XOSC32K_Type | XOSC32K |
Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control. | |
__IO OSC32KCTRL_CFDCTRL_Type | CFDCTRL |
Offset: 0x16 (R/W 8) Clock Failure Detector Control. | |
__IO OSC32KCTRL_EVCTRL_Type | EVCTRL |
Offset: 0x17 (R/W 8) Event Control. | |
RoReg8 | Reserved2 [0x4] |
__IO OSC32KCTRL_OSCULP32K_Type | OSCULP32K |
Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control. | |
OSC32KCTRL hardware registers.
Definition at line 286 of file osc32kctrl.h.