SAME54P20A Test Project
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Instance description for AES. More...
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Macros | |
#define | REG_AES_CTRLA (*(RwReg *)0x42002400UL) |
(AES) Control A | |
#define | REG_AES_CTRLB (*(RwReg8 *)0x42002404UL) |
(AES) Control B | |
#define | REG_AES_INTENCLR (*(RwReg8 *)0x42002405UL) |
(AES) Interrupt Enable Clear | |
#define | REG_AES_INTENSET (*(RwReg8 *)0x42002406UL) |
(AES) Interrupt Enable Set | |
#define | REG_AES_INTFLAG (*(RwReg8 *)0x42002407UL) |
(AES) Interrupt Flag Status | |
#define | REG_AES_DATABUFPTR (*(RwReg8 *)0x42002408UL) |
(AES) Data buffer pointer | |
#define | REG_AES_DBGCTRL (*(RwReg8 *)0x42002409UL) |
(AES) Debug control | |
#define | REG_AES_KEYWORD0 (*(WoReg *)0x4200240CUL) |
(AES) Keyword 0 | |
#define | REG_AES_KEYWORD1 (*(WoReg *)0x42002410UL) |
(AES) Keyword 1 | |
#define | REG_AES_KEYWORD2 (*(WoReg *)0x42002414UL) |
(AES) Keyword 2 | |
#define | REG_AES_KEYWORD3 (*(WoReg *)0x42002418UL) |
(AES) Keyword 3 | |
#define | REG_AES_KEYWORD4 (*(WoReg *)0x4200241CUL) |
(AES) Keyword 4 | |
#define | REG_AES_KEYWORD5 (*(WoReg *)0x42002420UL) |
(AES) Keyword 5 | |
#define | REG_AES_KEYWORD6 (*(WoReg *)0x42002424UL) |
(AES) Keyword 6 | |
#define | REG_AES_KEYWORD7 (*(WoReg *)0x42002428UL) |
(AES) Keyword 7 | |
#define | REG_AES_INDATA (*(RwReg *)0x42002438UL) |
(AES) Indata | |
#define | REG_AES_INTVECTV0 (*(WoReg *)0x4200243CUL) |
(AES) Initialisation Vector 0 | |
#define | REG_AES_INTVECTV1 (*(WoReg *)0x42002440UL) |
(AES) Initialisation Vector 1 | |
#define | REG_AES_INTVECTV2 (*(WoReg *)0x42002444UL) |
(AES) Initialisation Vector 2 | |
#define | REG_AES_INTVECTV3 (*(WoReg *)0x42002448UL) |
(AES) Initialisation Vector 3 | |
#define | REG_AES_HASHKEY0 (*(RwReg *)0x4200245CUL) |
(AES) Hash key 0 | |
#define | REG_AES_HASHKEY1 (*(RwReg *)0x42002460UL) |
(AES) Hash key 1 | |
#define | REG_AES_HASHKEY2 (*(RwReg *)0x42002464UL) |
(AES) Hash key 2 | |
#define | REG_AES_HASHKEY3 (*(RwReg *)0x42002468UL) |
(AES) Hash key 3 | |
#define | REG_AES_GHASH0 (*(RwReg *)0x4200246CUL) |
(AES) Galois Hash 0 | |
#define | REG_AES_GHASH1 (*(RwReg *)0x42002470UL) |
(AES) Galois Hash 1 | |
#define | REG_AES_GHASH2 (*(RwReg *)0x42002474UL) |
(AES) Galois Hash 2 | |
#define | REG_AES_GHASH3 (*(RwReg *)0x42002478UL) |
(AES) Galois Hash 3 | |
#define | REG_AES_CIPLEN (*(RwReg *)0x42002480UL) |
(AES) Cipher Length | |
#define | REG_AES_RANDSEED (*(RwReg *)0x42002484UL) |
(AES) Random Seed | |
#define | AES_DMAC_ID_RD 82 |
#define | AES_DMAC_ID_WR 81 |
#define | AES_FOUR_BYTE_OPERATION 1 |
#define | AES_GCM 1 |
#define | AES_KEYLEN 2 |
Instance description for AES.
Copyright (c) 2019 Microchip Technology Inc.
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Definition in file aes.h.