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30 #ifndef _SAME54_TC_COMPONENT_
31 #define _SAME54_TC_COMPONENT_
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
77 #define TC_CTRLA_OFFSET 0x00
78 #define TC_CTRLA_RESETVALUE _U_(0x00000000)
80 #define TC_CTRLA_SWRST_Pos 0
81 #define TC_CTRLA_SWRST (_U_(0x1) << TC_CTRLA_SWRST_Pos)
82 #define TC_CTRLA_ENABLE_Pos 1
83 #define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos)
84 #define TC_CTRLA_MODE_Pos 2
85 #define TC_CTRLA_MODE_Msk (_U_(0x3) << TC_CTRLA_MODE_Pos)
86 #define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
87 #define TC_CTRLA_MODE_COUNT16_Val _U_(0x0)
88 #define TC_CTRLA_MODE_COUNT8_Val _U_(0x1)
89 #define TC_CTRLA_MODE_COUNT32_Val _U_(0x2)
90 #define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
91 #define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
92 #define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
93 #define TC_CTRLA_PRESCSYNC_Pos 4
94 #define TC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos)
95 #define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
96 #define TC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0)
97 #define TC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1)
98 #define TC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2)
99 #define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
100 #define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
101 #define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
102 #define TC_CTRLA_RUNSTDBY_Pos 6
103 #define TC_CTRLA_RUNSTDBY (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos)
104 #define TC_CTRLA_ONDEMAND_Pos 7
105 #define TC_CTRLA_ONDEMAND (_U_(0x1) << TC_CTRLA_ONDEMAND_Pos)
106 #define TC_CTRLA_PRESCALER_Pos 8
107 #define TC_CTRLA_PRESCALER_Msk (_U_(0x7) << TC_CTRLA_PRESCALER_Pos)
108 #define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
109 #define TC_CTRLA_PRESCALER_DIV1_Val _U_(0x0)
110 #define TC_CTRLA_PRESCALER_DIV2_Val _U_(0x1)
111 #define TC_CTRLA_PRESCALER_DIV4_Val _U_(0x2)
112 #define TC_CTRLA_PRESCALER_DIV8_Val _U_(0x3)
113 #define TC_CTRLA_PRESCALER_DIV16_Val _U_(0x4)
114 #define TC_CTRLA_PRESCALER_DIV64_Val _U_(0x5)
115 #define TC_CTRLA_PRESCALER_DIV256_Val _U_(0x6)
116 #define TC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7)
117 #define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
118 #define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
119 #define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
120 #define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
121 #define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
122 #define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
123 #define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
124 #define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
125 #define TC_CTRLA_ALOCK_Pos 11
126 #define TC_CTRLA_ALOCK (_U_(0x1) << TC_CTRLA_ALOCK_Pos)
127 #define TC_CTRLA_CAPTEN0_Pos 16
128 #define TC_CTRLA_CAPTEN0 (_U_(1) << TC_CTRLA_CAPTEN0_Pos)
129 #define TC_CTRLA_CAPTEN1_Pos 17
130 #define TC_CTRLA_CAPTEN1 (_U_(1) << TC_CTRLA_CAPTEN1_Pos)
131 #define TC_CTRLA_CAPTEN_Pos 16
132 #define TC_CTRLA_CAPTEN_Msk (_U_(0x3) << TC_CTRLA_CAPTEN_Pos)
133 #define TC_CTRLA_CAPTEN(value) (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos))
134 #define TC_CTRLA_COPEN0_Pos 20
135 #define TC_CTRLA_COPEN0 (_U_(1) << TC_CTRLA_COPEN0_Pos)
136 #define TC_CTRLA_COPEN1_Pos 21
137 #define TC_CTRLA_COPEN1 (_U_(1) << TC_CTRLA_COPEN1_Pos)
138 #define TC_CTRLA_COPEN_Pos 20
139 #define TC_CTRLA_COPEN_Msk (_U_(0x3) << TC_CTRLA_COPEN_Pos)
140 #define TC_CTRLA_COPEN(value) (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos))
141 #define TC_CTRLA_CAPTMODE0_Pos 24
142 #define TC_CTRLA_CAPTMODE0_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE0_Pos)
143 #define TC_CTRLA_CAPTMODE0(value) (TC_CTRLA_CAPTMODE0_Msk & ((value) << TC_CTRLA_CAPTMODE0_Pos))
144 #define TC_CTRLA_CAPTMODE0_DEFAULT_Val _U_(0x0)
145 #define TC_CTRLA_CAPTMODE0_CAPTMIN_Val _U_(0x1)
146 #define TC_CTRLA_CAPTMODE0_CAPTMAX_Val _U_(0x2)
147 #define TC_CTRLA_CAPTMODE0_DEFAULT (TC_CTRLA_CAPTMODE0_DEFAULT_Val << TC_CTRLA_CAPTMODE0_Pos)
148 #define TC_CTRLA_CAPTMODE0_CAPTMIN (TC_CTRLA_CAPTMODE0_CAPTMIN_Val << TC_CTRLA_CAPTMODE0_Pos)
149 #define TC_CTRLA_CAPTMODE0_CAPTMAX (TC_CTRLA_CAPTMODE0_CAPTMAX_Val << TC_CTRLA_CAPTMODE0_Pos)
150 #define TC_CTRLA_CAPTMODE1_Pos 27
151 #define TC_CTRLA_CAPTMODE1_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE1_Pos)
152 #define TC_CTRLA_CAPTMODE1(value) (TC_CTRLA_CAPTMODE1_Msk & ((value) << TC_CTRLA_CAPTMODE1_Pos))
153 #define TC_CTRLA_CAPTMODE1_DEFAULT_Val _U_(0x0)
154 #define TC_CTRLA_CAPTMODE1_CAPTMIN_Val _U_(0x1)
155 #define TC_CTRLA_CAPTMODE1_CAPTMAX_Val _U_(0x2)
156 #define TC_CTRLA_CAPTMODE1_DEFAULT (TC_CTRLA_CAPTMODE1_DEFAULT_Val << TC_CTRLA_CAPTMODE1_Pos)
157 #define TC_CTRLA_CAPTMODE1_CAPTMIN (TC_CTRLA_CAPTMODE1_CAPTMIN_Val << TC_CTRLA_CAPTMODE1_Pos)
158 #define TC_CTRLA_CAPTMODE1_CAPTMAX (TC_CTRLA_CAPTMODE1_CAPTMAX_Val << TC_CTRLA_CAPTMODE1_Pos)
159 #define TC_CTRLA_MASK _U_(0x1B330FFF)
162 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
175 #define TC_CTRLBCLR_OFFSET 0x04
176 #define TC_CTRLBCLR_RESETVALUE _U_(0x00)
178 #define TC_CTRLBCLR_DIR_Pos 0
179 #define TC_CTRLBCLR_DIR (_U_(0x1) << TC_CTRLBCLR_DIR_Pos)
180 #define TC_CTRLBCLR_LUPD_Pos 1
181 #define TC_CTRLBCLR_LUPD (_U_(0x1) << TC_CTRLBCLR_LUPD_Pos)
182 #define TC_CTRLBCLR_ONESHOT_Pos 2
183 #define TC_CTRLBCLR_ONESHOT (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos)
184 #define TC_CTRLBCLR_CMD_Pos 5
185 #define TC_CTRLBCLR_CMD_Msk (_U_(0x7) << TC_CTRLBCLR_CMD_Pos)
186 #define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
187 #define TC_CTRLBCLR_CMD_NONE_Val _U_(0x0)
188 #define TC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1)
189 #define TC_CTRLBCLR_CMD_STOP_Val _U_(0x2)
190 #define TC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3)
191 #define TC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4)
192 #define TC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5)
193 #define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
194 #define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
195 #define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
196 #define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos)
197 #define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos)
198 #define TC_CTRLBCLR_CMD_DMAOS (TC_CTRLBCLR_CMD_DMAOS_Val << TC_CTRLBCLR_CMD_Pos)
199 #define TC_CTRLBCLR_MASK _U_(0xE7)
202 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
215 #define TC_CTRLBSET_OFFSET 0x05
216 #define TC_CTRLBSET_RESETVALUE _U_(0x00)
218 #define TC_CTRLBSET_DIR_Pos 0
219 #define TC_CTRLBSET_DIR (_U_(0x1) << TC_CTRLBSET_DIR_Pos)
220 #define TC_CTRLBSET_LUPD_Pos 1
221 #define TC_CTRLBSET_LUPD (_U_(0x1) << TC_CTRLBSET_LUPD_Pos)
222 #define TC_CTRLBSET_ONESHOT_Pos 2
223 #define TC_CTRLBSET_ONESHOT (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos)
224 #define TC_CTRLBSET_CMD_Pos 5
225 #define TC_CTRLBSET_CMD_Msk (_U_(0x7) << TC_CTRLBSET_CMD_Pos)
226 #define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
227 #define TC_CTRLBSET_CMD_NONE_Val _U_(0x0)
228 #define TC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1)
229 #define TC_CTRLBSET_CMD_STOP_Val _U_(0x2)
230 #define TC_CTRLBSET_CMD_UPDATE_Val _U_(0x3)
231 #define TC_CTRLBSET_CMD_READSYNC_Val _U_(0x4)
232 #define TC_CTRLBSET_CMD_DMAOS_Val _U_(0x5)
233 #define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
234 #define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
235 #define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
236 #define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos)
237 #define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos)
238 #define TC_CTRLBSET_CMD_DMAOS (TC_CTRLBSET_CMD_DMAOS_Val << TC_CTRLBSET_CMD_Pos)
239 #define TC_CTRLBSET_MASK _U_(0xE7)
242 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
265 #define TC_EVCTRL_OFFSET 0x06
266 #define TC_EVCTRL_RESETVALUE _U_(0x0000)
268 #define TC_EVCTRL_EVACT_Pos 0
269 #define TC_EVCTRL_EVACT_Msk (_U_(0x7) << TC_EVCTRL_EVACT_Pos)
270 #define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
271 #define TC_EVCTRL_EVACT_OFF_Val _U_(0x0)
272 #define TC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1)
273 #define TC_EVCTRL_EVACT_COUNT_Val _U_(0x2)
274 #define TC_EVCTRL_EVACT_START_Val _U_(0x3)
275 #define TC_EVCTRL_EVACT_STAMP_Val _U_(0x4)
276 #define TC_EVCTRL_EVACT_PPW_Val _U_(0x5)
277 #define TC_EVCTRL_EVACT_PWP_Val _U_(0x6)
278 #define TC_EVCTRL_EVACT_PW_Val _U_(0x7)
279 #define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
280 #define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
281 #define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
282 #define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
283 #define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos)
284 #define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
285 #define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
286 #define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos)
287 #define TC_EVCTRL_TCINV_Pos 4
288 #define TC_EVCTRL_TCINV (_U_(0x1) << TC_EVCTRL_TCINV_Pos)
289 #define TC_EVCTRL_TCEI_Pos 5
290 #define TC_EVCTRL_TCEI (_U_(0x1) << TC_EVCTRL_TCEI_Pos)
291 #define TC_EVCTRL_OVFEO_Pos 8
292 #define TC_EVCTRL_OVFEO (_U_(0x1) << TC_EVCTRL_OVFEO_Pos)
293 #define TC_EVCTRL_MCEO0_Pos 12
294 #define TC_EVCTRL_MCEO0 (_U_(1) << TC_EVCTRL_MCEO0_Pos)
295 #define TC_EVCTRL_MCEO1_Pos 13
296 #define TC_EVCTRL_MCEO1 (_U_(1) << TC_EVCTRL_MCEO1_Pos)
297 #define TC_EVCTRL_MCEO_Pos 12
298 #define TC_EVCTRL_MCEO_Msk (_U_(0x3) << TC_EVCTRL_MCEO_Pos)
299 #define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
300 #define TC_EVCTRL_MASK _U_(0x3137)
303 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
322 #define TC_INTENCLR_OFFSET 0x08
323 #define TC_INTENCLR_RESETVALUE _U_(0x00)
325 #define TC_INTENCLR_OVF_Pos 0
326 #define TC_INTENCLR_OVF (_U_(0x1) << TC_INTENCLR_OVF_Pos)
327 #define TC_INTENCLR_ERR_Pos 1
328 #define TC_INTENCLR_ERR (_U_(0x1) << TC_INTENCLR_ERR_Pos)
329 #define TC_INTENCLR_MC0_Pos 4
330 #define TC_INTENCLR_MC0 (_U_(1) << TC_INTENCLR_MC0_Pos)
331 #define TC_INTENCLR_MC1_Pos 5
332 #define TC_INTENCLR_MC1 (_U_(1) << TC_INTENCLR_MC1_Pos)
333 #define TC_INTENCLR_MC_Pos 4
334 #define TC_INTENCLR_MC_Msk (_U_(0x3) << TC_INTENCLR_MC_Pos)
335 #define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
336 #define TC_INTENCLR_MASK _U_(0x33)
339 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
358 #define TC_INTENSET_OFFSET 0x09
359 #define TC_INTENSET_RESETVALUE _U_(0x00)
361 #define TC_INTENSET_OVF_Pos 0
362 #define TC_INTENSET_OVF (_U_(0x1) << TC_INTENSET_OVF_Pos)
363 #define TC_INTENSET_ERR_Pos 1
364 #define TC_INTENSET_ERR (_U_(0x1) << TC_INTENSET_ERR_Pos)
365 #define TC_INTENSET_MC0_Pos 4
366 #define TC_INTENSET_MC0 (_U_(1) << TC_INTENSET_MC0_Pos)
367 #define TC_INTENSET_MC1_Pos 5
368 #define TC_INTENSET_MC1 (_U_(1) << TC_INTENSET_MC1_Pos)
369 #define TC_INTENSET_MC_Pos 4
370 #define TC_INTENSET_MC_Msk (_U_(0x3) << TC_INTENSET_MC_Pos)
371 #define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
372 #define TC_INTENSET_MASK _U_(0x33)
375 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
394 #define TC_INTFLAG_OFFSET 0x0A
395 #define TC_INTFLAG_RESETVALUE _U_(0x00)
397 #define TC_INTFLAG_OVF_Pos 0
398 #define TC_INTFLAG_OVF (_U_(0x1) << TC_INTFLAG_OVF_Pos)
399 #define TC_INTFLAG_ERR_Pos 1
400 #define TC_INTFLAG_ERR (_U_(0x1) << TC_INTFLAG_ERR_Pos)
401 #define TC_INTFLAG_MC0_Pos 4
402 #define TC_INTFLAG_MC0 (_U_(1) << TC_INTFLAG_MC0_Pos)
403 #define TC_INTFLAG_MC1_Pos 5
404 #define TC_INTFLAG_MC1 (_U_(1) << TC_INTFLAG_MC1_Pos)
405 #define TC_INTFLAG_MC_Pos 4
406 #define TC_INTFLAG_MC_Msk (_U_(0x3) << TC_INTFLAG_MC_Pos)
407 #define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
408 #define TC_INTFLAG_MASK _U_(0x33)
411 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
431 #define TC_STATUS_OFFSET 0x0B
432 #define TC_STATUS_RESETVALUE _U_(0x01)
434 #define TC_STATUS_STOP_Pos 0
435 #define TC_STATUS_STOP (_U_(0x1) << TC_STATUS_STOP_Pos)
436 #define TC_STATUS_SLAVE_Pos 1
437 #define TC_STATUS_SLAVE (_U_(0x1) << TC_STATUS_SLAVE_Pos)
438 #define TC_STATUS_PERBUFV_Pos 3
439 #define TC_STATUS_PERBUFV (_U_(0x1) << TC_STATUS_PERBUFV_Pos)
440 #define TC_STATUS_CCBUFV0_Pos 4
441 #define TC_STATUS_CCBUFV0 (_U_(1) << TC_STATUS_CCBUFV0_Pos)
442 #define TC_STATUS_CCBUFV1_Pos 5
443 #define TC_STATUS_CCBUFV1 (_U_(1) << TC_STATUS_CCBUFV1_Pos)
444 #define TC_STATUS_CCBUFV_Pos 4
445 #define TC_STATUS_CCBUFV_Msk (_U_(0x3) << TC_STATUS_CCBUFV_Pos)
446 #define TC_STATUS_CCBUFV(value) (TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos))
447 #define TC_STATUS_MASK _U_(0x3B)
450 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
460 #define TC_WAVE_OFFSET 0x0C
461 #define TC_WAVE_RESETVALUE _U_(0x00)
463 #define TC_WAVE_WAVEGEN_Pos 0
464 #define TC_WAVE_WAVEGEN_Msk (_U_(0x3) << TC_WAVE_WAVEGEN_Pos)
465 #define TC_WAVE_WAVEGEN(value) (TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos))
466 #define TC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0)
467 #define TC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1)
468 #define TC_WAVE_WAVEGEN_NPWM_Val _U_(0x2)
469 #define TC_WAVE_WAVEGEN_MPWM_Val _U_(0x3)
470 #define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos)
471 #define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos)
472 #define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos)
473 #define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos)
474 #define TC_WAVE_MASK _U_(0x03)
477 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
492 #define TC_DRVCTRL_OFFSET 0x0D
493 #define TC_DRVCTRL_RESETVALUE _U_(0x00)
495 #define TC_DRVCTRL_INVEN0_Pos 0
496 #define TC_DRVCTRL_INVEN0 (_U_(1) << TC_DRVCTRL_INVEN0_Pos)
497 #define TC_DRVCTRL_INVEN1_Pos 1
498 #define TC_DRVCTRL_INVEN1 (_U_(1) << TC_DRVCTRL_INVEN1_Pos)
499 #define TC_DRVCTRL_INVEN_Pos 0
500 #define TC_DRVCTRL_INVEN_Msk (_U_(0x3) << TC_DRVCTRL_INVEN_Pos)
501 #define TC_DRVCTRL_INVEN(value) (TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos))
502 #define TC_DRVCTRL_MASK _U_(0x03)
505 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
515 #define TC_DBGCTRL_OFFSET 0x0F
516 #define TC_DBGCTRL_RESETVALUE _U_(0x00)
518 #define TC_DBGCTRL_DBGRUN_Pos 0
519 #define TC_DBGCTRL_DBGRUN (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos)
520 #define TC_DBGCTRL_MASK _U_(0x01)
523 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
545 #define TC_SYNCBUSY_OFFSET 0x10
546 #define TC_SYNCBUSY_RESETVALUE _U_(0x00000000)
548 #define TC_SYNCBUSY_SWRST_Pos 0
549 #define TC_SYNCBUSY_SWRST (_U_(0x1) << TC_SYNCBUSY_SWRST_Pos)
550 #define TC_SYNCBUSY_ENABLE_Pos 1
551 #define TC_SYNCBUSY_ENABLE (_U_(0x1) << TC_SYNCBUSY_ENABLE_Pos)
552 #define TC_SYNCBUSY_CTRLB_Pos 2
553 #define TC_SYNCBUSY_CTRLB (_U_(0x1) << TC_SYNCBUSY_CTRLB_Pos)
554 #define TC_SYNCBUSY_STATUS_Pos 3
555 #define TC_SYNCBUSY_STATUS (_U_(0x1) << TC_SYNCBUSY_STATUS_Pos)
556 #define TC_SYNCBUSY_COUNT_Pos 4
557 #define TC_SYNCBUSY_COUNT (_U_(0x1) << TC_SYNCBUSY_COUNT_Pos)
558 #define TC_SYNCBUSY_PER_Pos 5
559 #define TC_SYNCBUSY_PER (_U_(0x1) << TC_SYNCBUSY_PER_Pos)
560 #define TC_SYNCBUSY_CC0_Pos 6
561 #define TC_SYNCBUSY_CC0 (_U_(1) << TC_SYNCBUSY_CC0_Pos)
562 #define TC_SYNCBUSY_CC1_Pos 7
563 #define TC_SYNCBUSY_CC1 (_U_(1) << TC_SYNCBUSY_CC1_Pos)
564 #define TC_SYNCBUSY_CC_Pos 6
565 #define TC_SYNCBUSY_CC_Msk (_U_(0x3) << TC_SYNCBUSY_CC_Pos)
566 #define TC_SYNCBUSY_CC(value) (TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos))
567 #define TC_SYNCBUSY_MASK _U_(0x000000FF)
570 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
579 #define TC_COUNT16_COUNT_OFFSET 0x14
580 #define TC_COUNT16_COUNT_RESETVALUE _U_(0x0000)
582 #define TC_COUNT16_COUNT_COUNT_Pos 0
583 #define TC_COUNT16_COUNT_COUNT_Msk (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos)
584 #define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
585 #define TC_COUNT16_COUNT_MASK _U_(0xFFFF)
588 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
597 #define TC_COUNT32_COUNT_OFFSET 0x14
598 #define TC_COUNT32_COUNT_RESETVALUE _U_(0x00000000)
600 #define TC_COUNT32_COUNT_COUNT_Pos 0
601 #define TC_COUNT32_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos)
602 #define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
603 #define TC_COUNT32_COUNT_MASK _U_(0xFFFFFFFF)
606 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
615 #define TC_COUNT8_COUNT_OFFSET 0x14
616 #define TC_COUNT8_COUNT_RESETVALUE _U_(0x00)
618 #define TC_COUNT8_COUNT_COUNT_Pos 0
619 #define TC_COUNT8_COUNT_COUNT_Msk (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos)
620 #define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
621 #define TC_COUNT8_COUNT_MASK _U_(0xFF)
624 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
633 #define TC_COUNT8_PER_OFFSET 0x1B
634 #define TC_COUNT8_PER_RESETVALUE _U_(0xFF)
636 #define TC_COUNT8_PER_PER_Pos 0
637 #define TC_COUNT8_PER_PER_Msk (_U_(0xFF) << TC_COUNT8_PER_PER_Pos)
638 #define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
639 #define TC_COUNT8_PER_MASK _U_(0xFF)
642 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
651 #define TC_COUNT16_CC_OFFSET 0x1C
652 #define TC_COUNT16_CC_RESETVALUE _U_(0x0000)
654 #define TC_COUNT16_CC_CC_Pos 0
655 #define TC_COUNT16_CC_CC_Msk (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos)
656 #define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
657 #define TC_COUNT16_CC_MASK _U_(0xFFFF)
660 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
669 #define TC_COUNT32_CC_OFFSET 0x1C
670 #define TC_COUNT32_CC_RESETVALUE _U_(0x00000000)
672 #define TC_COUNT32_CC_CC_Pos 0
673 #define TC_COUNT32_CC_CC_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos)
674 #define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
675 #define TC_COUNT32_CC_MASK _U_(0xFFFFFFFF)
678 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
687 #define TC_COUNT8_CC_OFFSET 0x1C
688 #define TC_COUNT8_CC_RESETVALUE _U_(0x00)
690 #define TC_COUNT8_CC_CC_Pos 0
691 #define TC_COUNT8_CC_CC_Msk (_U_(0xFF) << TC_COUNT8_CC_CC_Pos)
692 #define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
693 #define TC_COUNT8_CC_MASK _U_(0xFF)
696 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
705 #define TC_COUNT8_PERBUF_OFFSET 0x2F
706 #define TC_COUNT8_PERBUF_RESETVALUE _U_(0xFF)
708 #define TC_COUNT8_PERBUF_PERBUF_Pos 0
709 #define TC_COUNT8_PERBUF_PERBUF_Msk (_U_(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos)
710 #define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & ((value) << TC_COUNT8_PERBUF_PERBUF_Pos))
711 #define TC_COUNT8_PERBUF_MASK _U_(0xFF)
714 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
723 #define TC_COUNT16_CCBUF_OFFSET 0x30
724 #define TC_COUNT16_CCBUF_RESETVALUE _U_(0x0000)
726 #define TC_COUNT16_CCBUF_CCBUF_Pos 0
727 #define TC_COUNT16_CCBUF_CCBUF_Msk (_U_(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos)
728 #define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos))
729 #define TC_COUNT16_CCBUF_MASK _U_(0xFFFF)
732 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
741 #define TC_COUNT32_CCBUF_OFFSET 0x30
742 #define TC_COUNT32_CCBUF_RESETVALUE _U_(0x00000000)
744 #define TC_COUNT32_CCBUF_CCBUF_Pos 0
745 #define TC_COUNT32_CCBUF_CCBUF_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos)
746 #define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos))
747 #define TC_COUNT32_CCBUF_MASK _U_(0xFFFFFFFF)
750 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
759 #define TC_COUNT8_CCBUF_OFFSET 0x30
760 #define TC_COUNT8_CCBUF_RESETVALUE _U_(0x00)
762 #define TC_COUNT8_CCBUF_CCBUF_Pos 0
763 #define TC_COUNT8_CCBUF_CCBUF_Msk (_U_(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos)
764 #define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos))
765 #define TC_COUNT8_CCBUF_MASK _U_(0xFF)
768 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
794 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
818 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
841 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__IO TC_COUNT32_COUNT_Type COUNT
Offset: 0x14 (R/W 32) COUNT32 Count.
__IO TC_INTENCLR_Type INTENCLR
Offset: 0x08 (R/W 8) Interrupt Enable Clear.
TcCount16 COUNT16
Offset: 0x00 16-bit Counter Mode.
__IO TC_CTRLBCLR_Type CTRLBCLR
Offset: 0x04 (R/W 8) Control B Clear.
__IO TC_DRVCTRL_Type DRVCTRL
Offset: 0x0D (R/W 8) Control C.
__IO TC_CTRLBCLR_Type CTRLBCLR
Offset: 0x04 (R/W 8) Control B Clear.
__IO TC_INTENCLR_Type INTENCLR
Offset: 0x08 (R/W 8) Interrupt Enable Clear.
__IO TC_STATUS_Type STATUS
Offset: 0x0B (R/W 8) Status.
__IO TC_CTRLA_Type CTRLA
Offset: 0x00 (R/W 32) Control A.
__I TC_SYNCBUSY_Type SYNCBUSY
Offset: 0x10 (R/ 32) Synchronization Status.
__IO TC_CTRLA_Type CTRLA
Offset: 0x00 (R/W 32) Control A.
__IO TC_INTENSET_Type INTENSET
Offset: 0x09 (R/W 8) Interrupt Enable Set.
__IO TC_CTRLBSET_Type CTRLBSET
Offset: 0x05 (R/W 8) Control B Set.
__IO TC_INTFLAG_Type INTFLAG
Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear.
__IO TC_DBGCTRL_Type DBGCTRL
Offset: 0x0F (R/W 8) Debug Control.
__IO TC_STATUS_Type STATUS
Offset: 0x0B (R/W 8) Status.
TcCount8 COUNT8
Offset: 0x00 8-bit Counter Mode.
TC_COUNT8 hardware registers.
__I TC_SYNCBUSY_Type SYNCBUSY
Offset: 0x10 (R/ 32) Synchronization Status.
__IO TC_CTRLBCLR_Type CTRLBCLR
Offset: 0x04 (R/W 8) Control B Clear.
TcCount32 COUNT32
Offset: 0x00 32-bit Counter Mode.
__IO TC_INTENSET_Type INTENSET
Offset: 0x09 (R/W 8) Interrupt Enable Set.
__IO TC_EVCTRL_Type EVCTRL
Offset: 0x06 (R/W 16) Event Control.
__IO TC_DBGCTRL_Type DBGCTRL
Offset: 0x0F (R/W 8) Debug Control.
__IO TC_COUNT16_COUNT_Type COUNT
Offset: 0x14 (R/W 16) COUNT16 Count.
TC_COUNT32 hardware registers.
__IO TC_WAVE_Type WAVE
Offset: 0x0C (R/W 8) Waveform Generation Control.
TC_COUNT16 hardware registers.
__IO TC_WAVE_Type WAVE
Offset: 0x0C (R/W 8) Waveform Generation Control.
__IO TC_STATUS_Type STATUS
Offset: 0x0B (R/W 8) Status.
__IO TC_INTENSET_Type INTENSET
Offset: 0x09 (R/W 8) Interrupt Enable Set.
__IO TC_COUNT8_PER_Type PER
Offset: 0x1B (R/W 8) COUNT8 Period.
__IO TC_CTRLBSET_Type CTRLBSET
Offset: 0x05 (R/W 8) Control B Set.
__IO TC_COUNT8_PERBUF_Type PERBUF
Offset: 0x2F (R/W 8) COUNT8 Period Buffer.
__IO TC_WAVE_Type WAVE
Offset: 0x0C (R/W 8) Waveform Generation Control.
__IO TC_DRVCTRL_Type DRVCTRL
Offset: 0x0D (R/W 8) Control C.
__IO TC_CTRLA_Type CTRLA
Offset: 0x00 (R/W 32) Control A.
__IO TC_EVCTRL_Type EVCTRL
Offset: 0x06 (R/W 16) Event Control.
__I TC_SYNCBUSY_Type SYNCBUSY
Offset: 0x10 (R/ 32) Synchronization Status.
__IO TC_DRVCTRL_Type DRVCTRL
Offset: 0x0D (R/W 8) Control C.
volatile const uint8_t RoReg8
__IO TC_COUNT8_COUNT_Type COUNT
Offset: 0x14 (R/W 8) COUNT8 Count.
__IO TC_DBGCTRL_Type DBGCTRL
Offset: 0x0F (R/W 8) Debug Control.
__IO TC_CTRLBSET_Type CTRLBSET
Offset: 0x05 (R/W 8) Control B Set.
__IO TC_INTENCLR_Type INTENCLR
Offset: 0x08 (R/W 8) Interrupt Enable Clear.
__IO TC_INTFLAG_Type INTFLAG
Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear.
__IO TC_EVCTRL_Type EVCTRL
Offset: 0x06 (R/W 16) Event Control.
__IO TC_INTFLAG_Type INTFLAG
Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear.