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SAME54P20A Test Project
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MCLK hardware registers. More...
#include <mclk.h>
Data Fields | |
| RoReg8 | Reserved1 [0x1] |
| __IO MCLK_INTENCLR_Type | INTENCLR |
| Offset: 0x01 (R/W 8) Interrupt Enable Clear. | |
| __IO MCLK_INTENSET_Type | INTENSET |
| Offset: 0x02 (R/W 8) Interrupt Enable Set. | |
| __IO MCLK_INTFLAG_Type | INTFLAG |
| Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear. | |
| __I MCLK_HSDIV_Type | HSDIV |
| Offset: 0x04 (R/ 8) HS Clock Division. | |
| __IO MCLK_CPUDIV_Type | CPUDIV |
| Offset: 0x05 (R/W 8) CPU Clock Division. | |
| RoReg8 | Reserved2 [0xA] |
| __IO MCLK_AHBMASK_Type | AHBMASK |
| Offset: 0x10 (R/W 32) AHB Mask. | |
| __IO MCLK_APBAMASK_Type | APBAMASK |
| Offset: 0x14 (R/W 32) APBA Mask. | |
| __IO MCLK_APBBMASK_Type | APBBMASK |
| Offset: 0x18 (R/W 32) APBB Mask. | |
| __IO MCLK_APBCMASK_Type | APBCMASK |
| Offset: 0x1C (R/W 32) APBC Mask. | |
| __IO MCLK_APBDMASK_Type | APBDMASK |
| Offset: 0x20 (R/W 32) APBD Mask. | |
1.8.20