ICM APB hardware registers. More...

#include <icm.h>

Data Fields
__IO ICM_CFG_Type	CFG
	Offset: 0x00 (R/W 32) Configuration.

__O ICM_CTRL_Type	CTRL
	Offset: 0x04 ( /W 32) Control.

__I ICM_SR_Type	SR
	Offset: 0x08 (R/ 32) Status.

RoReg8	Reserved1 [0x4]

__O ICM_IER_Type	IER
	Offset: 0x10 ( /W 32) Interrupt Enable.

__O ICM_IDR_Type	IDR
	Offset: 0x14 ( /W 32) Interrupt Disable.

__I ICM_IMR_Type	IMR
	Offset: 0x18 (R/ 32) Interrupt Mask.

__I ICM_ISR_Type	ISR
	Offset: 0x1C (R/ 32) Interrupt Status.

__I ICM_UASR_Type	UASR
	Offset: 0x20 (R/ 32) Undefined Access Status.

RoReg8	Reserved2 [0xC]

__IO ICM_DSCR_Type	DSCR
	Offset: 0x30 (R/W 32) Region Descriptor Area Start Address.

__IO ICM_HASH_Type	HASH
	Offset: 0x34 (R/W 32) Region Hash Area Start Address.

__O ICM_UIHVAL_Type	UIHVAL [8]
	Offset: 0x38 ( /W 32) User Initial Hash Value n.

Detailed Description

ICM APB hardware registers.

Definition at line 551 of file icm.h.

The documentation for this struct was generated from the following file:

/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/icm.h

Data Fields