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SAME54P20A Test Project
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GCLK hardware registers. More...
#include <gclk.h>
Data Fields | |
| __IO GCLK_CTRLA_Type | CTRLA |
| Offset: 0x00 (R/W 8) Control. | |
| RoReg8 | Reserved1 [0x3] |
| __I GCLK_SYNCBUSY_Type | SYNCBUSY |
| Offset: 0x04 (R/ 32) Synchronization Busy. | |
| RoReg8 | Reserved2 [0x18] |
| __IO GCLK_GENCTRL_Type | GENCTRL [12] |
| Offset: 0x20 (R/W 32) Generic Clock Generator Control. | |
| RoReg8 | Reserved3 [0x30] |
| __IO GCLK_PCHCTRL_Type | PCHCTRL [48] |
| Offset: 0x80 (R/W 32) Peripheral Clock Control. | |