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SAME54P20A Test Project
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CMCC APB hardware registers. More...
#include <cmcc.h>
Data Fields | |
| __I CMCC_TYPE_Type | TYPE |
| Offset: 0x00 (R/ 32) Cache Type Register. | |
| __IO CMCC_CFG_Type | CFG |
| Offset: 0x04 (R/W 32) Cache Configuration Register. | |
| __O CMCC_CTRL_Type | CTRL |
| Offset: 0x08 ( /W 32) Cache Control Register. | |
| __I CMCC_SR_Type | SR |
| Offset: 0x0C (R/ 32) Cache Status Register. | |
| __IO CMCC_LCKWAY_Type | LCKWAY |
| Offset: 0x10 (R/W 32) Cache Lock per Way Register. | |
| RoReg8 | Reserved1 [0xC] |
| __O CMCC_MAINT0_Type | MAINT0 |
| Offset: 0x20 ( /W 32) Cache Maintenance Register 0. | |
| __O CMCC_MAINT1_Type | MAINT1 |
| Offset: 0x24 ( /W 32) Cache Maintenance Register 1. | |
| __IO CMCC_MCFG_Type | MCFG |
| Offset: 0x28 (R/W 32) Cache Monitor Configuration Register. | |
| __IO CMCC_MEN_Type | MEN |
| Offset: 0x2C (R/W 32) Cache Monitor Enable Register. | |
| __O CMCC_MCTRL_Type | MCTRL |
| Offset: 0x30 ( /W 32) Cache Monitor Control Register. | |
| __I CMCC_MSR_Type | MSR |
| Offset: 0x34 (R/ 32) Cache Monitor Status Register. | |
1.8.20