sdhc0.h File Reference

Instance description for SDHC0. More...

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Macros
#define	REG_SDHC0_SSAR   (*(RwReg *)0x45000000UL)
	(SDHC0) SDMA System Address / Argument 2
#define	REG_SDHC0_BSR   (*(RwReg16*)0x45000004UL)
	(SDHC0) Block Size
#define	REG_SDHC0_BCR   (*(RwReg16*)0x45000006UL)
	(SDHC0) Block Count
#define	REG_SDHC0_ARG1R   (*(RwReg *)0x45000008UL)
	(SDHC0) Argument 1
#define	REG_SDHC0_TMR   (*(RwReg16*)0x4500000CUL)
	(SDHC0) Transfer Mode
#define	REG_SDHC0_CR   (*(RwReg16*)0x4500000EUL)
	(SDHC0) Command
#define	REG_SDHC0_RR0   (*(RoReg *)0x45000010UL)
	(SDHC0) Response 0
#define	REG_SDHC0_RR1   (*(RoReg *)0x45000014UL)
	(SDHC0) Response 1
#define	REG_SDHC0_RR2   (*(RoReg *)0x45000018UL)
	(SDHC0) Response 2
#define	REG_SDHC0_RR3   (*(RoReg *)0x4500001CUL)
	(SDHC0) Response 3
#define	REG_SDHC0_BDPR   (*(RwReg *)0x45000020UL)
	(SDHC0) Buffer Data Port
#define	REG_SDHC0_PSR   (*(RoReg *)0x45000024UL)
	(SDHC0) Present State
#define	REG_SDHC0_HC1R   (*(RwReg8 *)0x45000028UL)
	(SDHC0) Host Control 1
#define	REG_SDHC0_PCR   (*(RwReg8 *)0x45000029UL)
	(SDHC0) Power Control
#define	REG_SDHC0_BGCR   (*(RwReg8 *)0x4500002AUL)
	(SDHC0) Block Gap Control
#define	REG_SDHC0_WCR   (*(RwReg8 *)0x4500002BUL)
	(SDHC0) Wakeup Control
#define	REG_SDHC0_CCR   (*(RwReg16*)0x4500002CUL)
	(SDHC0) Clock Control
#define	REG_SDHC0_TCR   (*(RwReg8 *)0x4500002EUL)
	(SDHC0) Timeout Control
#define	REG_SDHC0_SRR   (*(RwReg8 *)0x4500002FUL)
	(SDHC0) Software Reset
#define	REG_SDHC0_NISTR   (*(RwReg16*)0x45000030UL)
	(SDHC0) Normal Interrupt Status
#define	REG_SDHC0_EISTR   (*(RwReg16*)0x45000032UL)
	(SDHC0) Error Interrupt Status
#define	REG_SDHC0_NISTER   (*(RwReg16*)0x45000034UL)
	(SDHC0) Normal Interrupt Status Enable
#define	REG_SDHC0_EISTER   (*(RwReg16*)0x45000036UL)
	(SDHC0) Error Interrupt Status Enable
#define	REG_SDHC0_NISIER   (*(RwReg16*)0x45000038UL)
	(SDHC0) Normal Interrupt Signal Enable
#define	REG_SDHC0_EISIER   (*(RwReg16*)0x4500003AUL)
	(SDHC0) Error Interrupt Signal Enable
#define	REG_SDHC0_ACESR   (*(RoReg16*)0x4500003CUL)
	(SDHC0) Auto CMD Error Status
#define	REG_SDHC0_HC2R   (*(RwReg16*)0x4500003EUL)
	(SDHC0) Host Control 2
#define	REG_SDHC0_CA0R   (*(RoReg *)0x45000040UL)
	(SDHC0) Capabilities 0
#define	REG_SDHC0_CA1R   (*(RoReg *)0x45000044UL)
	(SDHC0) Capabilities 1
#define	REG_SDHC0_MCCAR   (*(RoReg *)0x45000048UL)
	(SDHC0) Maximum Current Capabilities
#define	REG_SDHC0_FERACES   (*(WoReg16*)0x45000050UL)
	(SDHC0) Force Event for Auto CMD Error Status
#define	REG_SDHC0_FEREIS   (*(WoReg16*)0x45000052UL)
	(SDHC0) Force Event for Error Interrupt Status
#define	REG_SDHC0_AESR   (*(RoReg8 *)0x45000054UL)
	(SDHC0) ADMA Error Status
#define	REG_SDHC0_ASAR0   (*(RwReg *)0x45000058UL)
	(SDHC0) ADMA System Address 0
#define	REG_SDHC0_PVR0   (*(RwReg16*)0x45000060UL)
	(SDHC0) Preset Value 0
#define	REG_SDHC0_PVR1   (*(RwReg16*)0x45000062UL)
	(SDHC0) Preset Value 1
#define	REG_SDHC0_PVR2   (*(RwReg16*)0x45000064UL)
	(SDHC0) Preset Value 2
#define	REG_SDHC0_PVR3   (*(RwReg16*)0x45000066UL)
	(SDHC0) Preset Value 3
#define	REG_SDHC0_PVR4   (*(RwReg16*)0x45000068UL)
	(SDHC0) Preset Value 4
#define	REG_SDHC0_PVR5   (*(RwReg16*)0x4500006AUL)
	(SDHC0) Preset Value 5
#define	REG_SDHC0_PVR6   (*(RwReg16*)0x4500006CUL)
	(SDHC0) Preset Value 6
#define	REG_SDHC0_PVR7   (*(RwReg16*)0x4500006EUL)
	(SDHC0) Preset Value 7
#define	REG_SDHC0_SISR   (*(RoReg16*)0x450000FCUL)
	(SDHC0) Slot Interrupt Status
#define	REG_SDHC0_HCVR   (*(RoReg16*)0x450000FEUL)
	(SDHC0) Host Controller Version
#define	REG_SDHC0_MC1R   (*(RwReg8 *)0x45000204UL)
	(SDHC0) MMC Control 1
#define	REG_SDHC0_MC2R   (*(WoReg8 *)0x45000205UL)
	(SDHC0) MMC Control 2
#define	REG_SDHC0_ACR   (*(RwReg *)0x45000208UL)
	(SDHC0) AHB Control
#define	REG_SDHC0_CC2R   (*(RwReg *)0x4500020CUL)
	(SDHC0) Clock Control 2
#define	REG_SDHC0_CACR   (*(RwReg *)0x45000230UL)
	(SDHC0) Capabilities Control
#define	REG_SDHC0_DBGR   (*(RwReg8 *)0x45000234UL)
	(SDHC0) Debug
#define	SDHC0_CARD_DATA_SIZE   4
#define	SDHC0_CLK_AHB_ID   15
#define	SDHC0_GCLK_ID   45
#define	SDHC0_GCLK_ID_SLOW   3
#define	SDHC0_NB_OF_DEVICES   1
#define	SDHC0_NB_REG_PVR   8
#define	SDHC0_NB_REG_RR   4

Detailed Description

Instance description for SDHC0.

Copyright (c) 2019 Microchip Technology Inc.

\asf_license_start

Definition in file sdhc0.h.