Instance description for DMAC. More...

Macros
#define	REG_DMAC_CTRL ((RwReg16)0x4100A000UL)
	(DMAC) Control

#define	REG_DMAC_CRCCTRL ((RwReg16)0x4100A002UL)
	(DMAC) CRC Control

#define	REG_DMAC_CRCDATAIN ((RwReg )0x4100A004UL)
	(DMAC) CRC Data Input

#define	REG_DMAC_CRCCHKSUM ((RwReg )0x4100A008UL)
	(DMAC) CRC Checksum

#define	REG_DMAC_CRCSTATUS ((RwReg8 )0x4100A00CUL)
	(DMAC) CRC Status

#define	REG_DMAC_DBGCTRL ((RwReg8 )0x4100A00DUL)
	(DMAC) Debug Control

#define	REG_DMAC_SWTRIGCTRL ((RwReg )0x4100A010UL)
	(DMAC) Software Trigger Control

#define	REG_DMAC_PRICTRL0 ((RwReg )0x4100A014UL)
	(DMAC) Priority Control 0

#define	REG_DMAC_INTPEND ((RwReg16)0x4100A020UL)
	(DMAC) Interrupt Pending

#define	REG_DMAC_INTSTATUS ((RoReg )0x4100A024UL)
	(DMAC) Interrupt Status

#define	REG_DMAC_BUSYCH ((RoReg )0x4100A028UL)
	(DMAC) Busy Channels

#define	REG_DMAC_PENDCH ((RoReg )0x4100A02CUL)
	(DMAC) Pending Channels

#define	REG_DMAC_ACTIVE ((RoReg )0x4100A030UL)
	(DMAC) Active Channel and Levels

#define	REG_DMAC_BASEADDR ((RwReg )0x4100A034UL)
	(DMAC) Descriptor Memory Section Base Address

#define	REG_DMAC_WRBADDR ((RwReg )0x4100A038UL)
	(DMAC) Write-Back Memory Section Base Address

#define	REG_DMAC_CHCTRLA0 ((RwReg )0x4100A040UL)
	(DMAC) Channel 0 Control A

#define	REG_DMAC_CHCTRLB0 ((RwReg8 )0x4100A044UL)
	(DMAC) Channel 0 Control B

#define	REG_DMAC_CHPRILVL0 ((RwReg8 )0x4100A045UL)
	(DMAC) Channel 0 Priority Level

#define	REG_DMAC_CHEVCTRL0 ((RwReg8 )0x4100A046UL)
	(DMAC) Channel 0 Event Control

#define	REG_DMAC_CHINTENCLR0 ((RwReg8 )0x4100A04CUL)
	(DMAC) Channel 0 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET0 ((RwReg8 )0x4100A04DUL)
	(DMAC) Channel 0 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG0 ((RwReg8 )0x4100A04EUL)
	(DMAC) Channel 0 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS0 ((RwReg8 )0x4100A04FUL)
	(DMAC) Channel 0 Status

#define	REG_DMAC_CHCTRLA1 ((RwReg )0x4100A050UL)
	(DMAC) Channel 1 Control A

#define	REG_DMAC_CHCTRLB1 ((RwReg8 )0x4100A054UL)
	(DMAC) Channel 1 Control B

#define	REG_DMAC_CHPRILVL1 ((RwReg8 )0x4100A055UL)
	(DMAC) Channel 1 Priority Level

#define	REG_DMAC_CHEVCTRL1 ((RwReg8 )0x4100A056UL)
	(DMAC) Channel 1 Event Control

#define	REG_DMAC_CHINTENCLR1 ((RwReg8 )0x4100A05CUL)
	(DMAC) Channel 1 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET1 ((RwReg8 )0x4100A05DUL)
	(DMAC) Channel 1 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG1 ((RwReg8 )0x4100A05EUL)
	(DMAC) Channel 1 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS1 ((RwReg8 )0x4100A05FUL)
	(DMAC) Channel 1 Status

#define	REG_DMAC_CHCTRLA2 ((RwReg )0x4100A060UL)
	(DMAC) Channel 2 Control A

#define	REG_DMAC_CHCTRLB2 ((RwReg8 )0x4100A064UL)
	(DMAC) Channel 2 Control B

#define	REG_DMAC_CHPRILVL2 ((RwReg8 )0x4100A065UL)
	(DMAC) Channel 2 Priority Level

#define	REG_DMAC_CHEVCTRL2 ((RwReg8 )0x4100A066UL)
	(DMAC) Channel 2 Event Control

#define	REG_DMAC_CHINTENCLR2 ((RwReg8 )0x4100A06CUL)
	(DMAC) Channel 2 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET2 ((RwReg8 )0x4100A06DUL)
	(DMAC) Channel 2 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG2 ((RwReg8 )0x4100A06EUL)
	(DMAC) Channel 2 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS2 ((RwReg8 )0x4100A06FUL)
	(DMAC) Channel 2 Status

#define	REG_DMAC_CHCTRLA3 ((RwReg )0x4100A070UL)
	(DMAC) Channel 3 Control A

#define	REG_DMAC_CHCTRLB3 ((RwReg8 )0x4100A074UL)
	(DMAC) Channel 3 Control B

#define	REG_DMAC_CHPRILVL3 ((RwReg8 )0x4100A075UL)
	(DMAC) Channel 3 Priority Level

#define	REG_DMAC_CHEVCTRL3 ((RwReg8 )0x4100A076UL)
	(DMAC) Channel 3 Event Control

#define	REG_DMAC_CHINTENCLR3 ((RwReg8 )0x4100A07CUL)
	(DMAC) Channel 3 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET3 ((RwReg8 )0x4100A07DUL)
	(DMAC) Channel 3 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG3 ((RwReg8 )0x4100A07EUL)
	(DMAC) Channel 3 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS3 ((RwReg8 )0x4100A07FUL)
	(DMAC) Channel 3 Status

#define	REG_DMAC_CHCTRLA4 ((RwReg )0x4100A080UL)
	(DMAC) Channel 4 Control A

#define	REG_DMAC_CHCTRLB4 ((RwReg8 )0x4100A084UL)
	(DMAC) Channel 4 Control B

#define	REG_DMAC_CHPRILVL4 ((RwReg8 )0x4100A085UL)
	(DMAC) Channel 4 Priority Level

#define	REG_DMAC_CHEVCTRL4 ((RwReg8 )0x4100A086UL)
	(DMAC) Channel 4 Event Control

#define	REG_DMAC_CHINTENCLR4 ((RwReg8 )0x4100A08CUL)
	(DMAC) Channel 4 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET4 ((RwReg8 )0x4100A08DUL)
	(DMAC) Channel 4 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG4 ((RwReg8 )0x4100A08EUL)
	(DMAC) Channel 4 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS4 ((RwReg8 )0x4100A08FUL)
	(DMAC) Channel 4 Status

#define	REG_DMAC_CHCTRLA5 ((RwReg )0x4100A090UL)
	(DMAC) Channel 5 Control A

#define	REG_DMAC_CHCTRLB5 ((RwReg8 )0x4100A094UL)
	(DMAC) Channel 5 Control B

#define	REG_DMAC_CHPRILVL5 ((RwReg8 )0x4100A095UL)
	(DMAC) Channel 5 Priority Level

#define	REG_DMAC_CHEVCTRL5 ((RwReg8 )0x4100A096UL)
	(DMAC) Channel 5 Event Control

#define	REG_DMAC_CHINTENCLR5 ((RwReg8 )0x4100A09CUL)
	(DMAC) Channel 5 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET5 ((RwReg8 )0x4100A09DUL)
	(DMAC) Channel 5 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG5 ((RwReg8 )0x4100A09EUL)
	(DMAC) Channel 5 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS5 ((RwReg8 )0x4100A09FUL)
	(DMAC) Channel 5 Status

#define	REG_DMAC_CHCTRLA6 ((RwReg )0x4100A0A0UL)
	(DMAC) Channel 6 Control A

#define	REG_DMAC_CHCTRLB6 ((RwReg8 )0x4100A0A4UL)
	(DMAC) Channel 6 Control B

#define	REG_DMAC_CHPRILVL6 ((RwReg8 )0x4100A0A5UL)
	(DMAC) Channel 6 Priority Level

#define	REG_DMAC_CHEVCTRL6 ((RwReg8 )0x4100A0A6UL)
	(DMAC) Channel 6 Event Control

#define	REG_DMAC_CHINTENCLR6 ((RwReg8 )0x4100A0ACUL)
	(DMAC) Channel 6 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET6 ((RwReg8 )0x4100A0ADUL)
	(DMAC) Channel 6 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG6 ((RwReg8 )0x4100A0AEUL)
	(DMAC) Channel 6 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS6 ((RwReg8 )0x4100A0AFUL)
	(DMAC) Channel 6 Status

#define	REG_DMAC_CHCTRLA7 ((RwReg )0x4100A0B0UL)
	(DMAC) Channel 7 Control A

#define	REG_DMAC_CHCTRLB7 ((RwReg8 )0x4100A0B4UL)
	(DMAC) Channel 7 Control B

#define	REG_DMAC_CHPRILVL7 ((RwReg8 )0x4100A0B5UL)
	(DMAC) Channel 7 Priority Level

#define	REG_DMAC_CHEVCTRL7 ((RwReg8 )0x4100A0B6UL)
	(DMAC) Channel 7 Event Control

#define	REG_DMAC_CHINTENCLR7 ((RwReg8 )0x4100A0BCUL)
	(DMAC) Channel 7 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET7 ((RwReg8 )0x4100A0BDUL)
	(DMAC) Channel 7 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG7 ((RwReg8 )0x4100A0BEUL)
	(DMAC) Channel 7 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS7 ((RwReg8 )0x4100A0BFUL)
	(DMAC) Channel 7 Status

#define	REG_DMAC_CHCTRLA8 ((RwReg )0x4100A0C0UL)
	(DMAC) Channel 8 Control A

#define	REG_DMAC_CHCTRLB8 ((RwReg8 )0x4100A0C4UL)
	(DMAC) Channel 8 Control B

#define	REG_DMAC_CHPRILVL8 ((RwReg8 )0x4100A0C5UL)
	(DMAC) Channel 8 Priority Level

#define	REG_DMAC_CHEVCTRL8 ((RwReg8 )0x4100A0C6UL)
	(DMAC) Channel 8 Event Control

#define	REG_DMAC_CHINTENCLR8 ((RwReg8 )0x4100A0CCUL)
	(DMAC) Channel 8 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET8 ((RwReg8 )0x4100A0CDUL)
	(DMAC) Channel 8 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG8 ((RwReg8 )0x4100A0CEUL)
	(DMAC) Channel 8 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS8 ((RwReg8 )0x4100A0CFUL)
	(DMAC) Channel 8 Status

#define	REG_DMAC_CHCTRLA9 ((RwReg )0x4100A0D0UL)
	(DMAC) Channel 9 Control A

#define	REG_DMAC_CHCTRLB9 ((RwReg8 )0x4100A0D4UL)
	(DMAC) Channel 9 Control B

#define	REG_DMAC_CHPRILVL9 ((RwReg8 )0x4100A0D5UL)
	(DMAC) Channel 9 Priority Level

#define	REG_DMAC_CHEVCTRL9 ((RwReg8 )0x4100A0D6UL)
	(DMAC) Channel 9 Event Control

#define	REG_DMAC_CHINTENCLR9 ((RwReg8 )0x4100A0DCUL)
	(DMAC) Channel 9 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET9 ((RwReg8 )0x4100A0DDUL)
	(DMAC) Channel 9 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG9 ((RwReg8 )0x4100A0DEUL)
	(DMAC) Channel 9 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS9 ((RwReg8 )0x4100A0DFUL)
	(DMAC) Channel 9 Status

#define	REG_DMAC_CHCTRLA10 ((RwReg )0x4100A0E0UL)
	(DMAC) Channel 10 Control A

#define	REG_DMAC_CHCTRLB10 ((RwReg8 )0x4100A0E4UL)
	(DMAC) Channel 10 Control B

#define	REG_DMAC_CHPRILVL10 ((RwReg8 )0x4100A0E5UL)
	(DMAC) Channel 10 Priority Level

#define	REG_DMAC_CHEVCTRL10 ((RwReg8 )0x4100A0E6UL)
	(DMAC) Channel 10 Event Control

#define	REG_DMAC_CHINTENCLR10 ((RwReg8 )0x4100A0ECUL)
	(DMAC) Channel 10 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET10 ((RwReg8 )0x4100A0EDUL)
	(DMAC) Channel 10 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG10 ((RwReg8 )0x4100A0EEUL)
	(DMAC) Channel 10 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS10 ((RwReg8 )0x4100A0EFUL)
	(DMAC) Channel 10 Status

#define	REG_DMAC_CHCTRLA11 ((RwReg )0x4100A0F0UL)
	(DMAC) Channel 11 Control A

#define	REG_DMAC_CHCTRLB11 ((RwReg8 )0x4100A0F4UL)
	(DMAC) Channel 11 Control B

#define	REG_DMAC_CHPRILVL11 ((RwReg8 )0x4100A0F5UL)
	(DMAC) Channel 11 Priority Level

#define	REG_DMAC_CHEVCTRL11 ((RwReg8 )0x4100A0F6UL)
	(DMAC) Channel 11 Event Control

#define	REG_DMAC_CHINTENCLR11 ((RwReg8 )0x4100A0FCUL)
	(DMAC) Channel 11 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET11 ((RwReg8 )0x4100A0FDUL)
	(DMAC) Channel 11 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG11 ((RwReg8 )0x4100A0FEUL)
	(DMAC) Channel 11 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS11 ((RwReg8 )0x4100A0FFUL)
	(DMAC) Channel 11 Status

#define	REG_DMAC_CHCTRLA12 ((RwReg )0x4100A100UL)
	(DMAC) Channel 12 Control A

#define	REG_DMAC_CHCTRLB12 ((RwReg8 )0x4100A104UL)
	(DMAC) Channel 12 Control B

#define	REG_DMAC_CHPRILVL12 ((RwReg8 )0x4100A105UL)
	(DMAC) Channel 12 Priority Level

#define	REG_DMAC_CHEVCTRL12 ((RwReg8 )0x4100A106UL)
	(DMAC) Channel 12 Event Control

#define	REG_DMAC_CHINTENCLR12 ((RwReg8 )0x4100A10CUL)
	(DMAC) Channel 12 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET12 ((RwReg8 )0x4100A10DUL)
	(DMAC) Channel 12 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG12 ((RwReg8 )0x4100A10EUL)
	(DMAC) Channel 12 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS12 ((RwReg8 )0x4100A10FUL)
	(DMAC) Channel 12 Status

#define	REG_DMAC_CHCTRLA13 ((RwReg )0x4100A110UL)
	(DMAC) Channel 13 Control A

#define	REG_DMAC_CHCTRLB13 ((RwReg8 )0x4100A114UL)
	(DMAC) Channel 13 Control B

#define	REG_DMAC_CHPRILVL13 ((RwReg8 )0x4100A115UL)
	(DMAC) Channel 13 Priority Level

#define	REG_DMAC_CHEVCTRL13 ((RwReg8 )0x4100A116UL)
	(DMAC) Channel 13 Event Control

#define	REG_DMAC_CHINTENCLR13 ((RwReg8 )0x4100A11CUL)
	(DMAC) Channel 13 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET13 ((RwReg8 )0x4100A11DUL)
	(DMAC) Channel 13 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG13 ((RwReg8 )0x4100A11EUL)
	(DMAC) Channel 13 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS13 ((RwReg8 )0x4100A11FUL)
	(DMAC) Channel 13 Status

#define	REG_DMAC_CHCTRLA14 ((RwReg )0x4100A120UL)
	(DMAC) Channel 14 Control A

#define	REG_DMAC_CHCTRLB14 ((RwReg8 )0x4100A124UL)
	(DMAC) Channel 14 Control B

#define	REG_DMAC_CHPRILVL14 ((RwReg8 )0x4100A125UL)
	(DMAC) Channel 14 Priority Level

#define	REG_DMAC_CHEVCTRL14 ((RwReg8 )0x4100A126UL)
	(DMAC) Channel 14 Event Control

#define	REG_DMAC_CHINTENCLR14 ((RwReg8 )0x4100A12CUL)
	(DMAC) Channel 14 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET14 ((RwReg8 )0x4100A12DUL)
	(DMAC) Channel 14 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG14 ((RwReg8 )0x4100A12EUL)
	(DMAC) Channel 14 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS14 ((RwReg8 )0x4100A12FUL)
	(DMAC) Channel 14 Status

#define	REG_DMAC_CHCTRLA15 ((RwReg )0x4100A130UL)
	(DMAC) Channel 15 Control A

#define	REG_DMAC_CHCTRLB15 ((RwReg8 )0x4100A134UL)
	(DMAC) Channel 15 Control B

#define	REG_DMAC_CHPRILVL15 ((RwReg8 )0x4100A135UL)
	(DMAC) Channel 15 Priority Level

#define	REG_DMAC_CHEVCTRL15 ((RwReg8 )0x4100A136UL)
	(DMAC) Channel 15 Event Control

#define	REG_DMAC_CHINTENCLR15 ((RwReg8 )0x4100A13CUL)
	(DMAC) Channel 15 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET15 ((RwReg8 )0x4100A13DUL)
	(DMAC) Channel 15 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG15 ((RwReg8 )0x4100A13EUL)
	(DMAC) Channel 15 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS15 ((RwReg8 )0x4100A13FUL)
	(DMAC) Channel 15 Status

#define	REG_DMAC_CHCTRLA16 ((RwReg )0x4100A140UL)
	(DMAC) Channel 16 Control A

#define	REG_DMAC_CHCTRLB16 ((RwReg8 )0x4100A144UL)
	(DMAC) Channel 16 Control B

#define	REG_DMAC_CHPRILVL16 ((RwReg8 )0x4100A145UL)
	(DMAC) Channel 16 Priority Level

#define	REG_DMAC_CHEVCTRL16 ((RwReg8 )0x4100A146UL)
	(DMAC) Channel 16 Event Control

#define	REG_DMAC_CHINTENCLR16 ((RwReg8 )0x4100A14CUL)
	(DMAC) Channel 16 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET16 ((RwReg8 )0x4100A14DUL)
	(DMAC) Channel 16 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG16 ((RwReg8 )0x4100A14EUL)
	(DMAC) Channel 16 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS16 ((RwReg8 )0x4100A14FUL)
	(DMAC) Channel 16 Status

#define	REG_DMAC_CHCTRLA17 ((RwReg )0x4100A150UL)
	(DMAC) Channel 17 Control A

#define	REG_DMAC_CHCTRLB17 ((RwReg8 )0x4100A154UL)
	(DMAC) Channel 17 Control B

#define	REG_DMAC_CHPRILVL17 ((RwReg8 )0x4100A155UL)
	(DMAC) Channel 17 Priority Level

#define	REG_DMAC_CHEVCTRL17 ((RwReg8 )0x4100A156UL)
	(DMAC) Channel 17 Event Control

#define	REG_DMAC_CHINTENCLR17 ((RwReg8 )0x4100A15CUL)
	(DMAC) Channel 17 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET17 ((RwReg8 )0x4100A15DUL)
	(DMAC) Channel 17 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG17 ((RwReg8 )0x4100A15EUL)
	(DMAC) Channel 17 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS17 ((RwReg8 )0x4100A15FUL)
	(DMAC) Channel 17 Status

#define	REG_DMAC_CHCTRLA18 ((RwReg )0x4100A160UL)
	(DMAC) Channel 18 Control A

#define	REG_DMAC_CHCTRLB18 ((RwReg8 )0x4100A164UL)
	(DMAC) Channel 18 Control B

#define	REG_DMAC_CHPRILVL18 ((RwReg8 )0x4100A165UL)
	(DMAC) Channel 18 Priority Level

#define	REG_DMAC_CHEVCTRL18 ((RwReg8 )0x4100A166UL)
	(DMAC) Channel 18 Event Control

#define	REG_DMAC_CHINTENCLR18 ((RwReg8 )0x4100A16CUL)
	(DMAC) Channel 18 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET18 ((RwReg8 )0x4100A16DUL)
	(DMAC) Channel 18 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG18 ((RwReg8 )0x4100A16EUL)
	(DMAC) Channel 18 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS18 ((RwReg8 )0x4100A16FUL)
	(DMAC) Channel 18 Status

#define	REG_DMAC_CHCTRLA19 ((RwReg )0x4100A170UL)
	(DMAC) Channel 19 Control A

#define	REG_DMAC_CHCTRLB19 ((RwReg8 )0x4100A174UL)
	(DMAC) Channel 19 Control B

#define	REG_DMAC_CHPRILVL19 ((RwReg8 )0x4100A175UL)
	(DMAC) Channel 19 Priority Level

#define	REG_DMAC_CHEVCTRL19 ((RwReg8 )0x4100A176UL)
	(DMAC) Channel 19 Event Control

#define	REG_DMAC_CHINTENCLR19 ((RwReg8 )0x4100A17CUL)
	(DMAC) Channel 19 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET19 ((RwReg8 )0x4100A17DUL)
	(DMAC) Channel 19 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG19 ((RwReg8 )0x4100A17EUL)
	(DMAC) Channel 19 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS19 ((RwReg8 )0x4100A17FUL)
	(DMAC) Channel 19 Status

#define	REG_DMAC_CHCTRLA20 ((RwReg )0x4100A180UL)
	(DMAC) Channel 20 Control A

#define	REG_DMAC_CHCTRLB20 ((RwReg8 )0x4100A184UL)
	(DMAC) Channel 20 Control B

#define	REG_DMAC_CHPRILVL20 ((RwReg8 )0x4100A185UL)
	(DMAC) Channel 20 Priority Level

#define	REG_DMAC_CHEVCTRL20 ((RwReg8 )0x4100A186UL)
	(DMAC) Channel 20 Event Control

#define	REG_DMAC_CHINTENCLR20 ((RwReg8 )0x4100A18CUL)
	(DMAC) Channel 20 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET20 ((RwReg8 )0x4100A18DUL)
	(DMAC) Channel 20 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG20 ((RwReg8 )0x4100A18EUL)
	(DMAC) Channel 20 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS20 ((RwReg8 )0x4100A18FUL)
	(DMAC) Channel 20 Status

#define	REG_DMAC_CHCTRLA21 ((RwReg )0x4100A190UL)
	(DMAC) Channel 21 Control A

#define	REG_DMAC_CHCTRLB21 ((RwReg8 )0x4100A194UL)
	(DMAC) Channel 21 Control B

#define	REG_DMAC_CHPRILVL21 ((RwReg8 )0x4100A195UL)
	(DMAC) Channel 21 Priority Level

#define	REG_DMAC_CHEVCTRL21 ((RwReg8 )0x4100A196UL)
	(DMAC) Channel 21 Event Control

#define	REG_DMAC_CHINTENCLR21 ((RwReg8 )0x4100A19CUL)
	(DMAC) Channel 21 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET21 ((RwReg8 )0x4100A19DUL)
	(DMAC) Channel 21 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG21 ((RwReg8 )0x4100A19EUL)
	(DMAC) Channel 21 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS21 ((RwReg8 )0x4100A19FUL)
	(DMAC) Channel 21 Status

#define	REG_DMAC_CHCTRLA22 ((RwReg )0x4100A1A0UL)
	(DMAC) Channel 22 Control A

#define	REG_DMAC_CHCTRLB22 ((RwReg8 )0x4100A1A4UL)
	(DMAC) Channel 22 Control B

#define	REG_DMAC_CHPRILVL22 ((RwReg8 )0x4100A1A5UL)
	(DMAC) Channel 22 Priority Level

#define	REG_DMAC_CHEVCTRL22 ((RwReg8 )0x4100A1A6UL)
	(DMAC) Channel 22 Event Control

#define	REG_DMAC_CHINTENCLR22 ((RwReg8 )0x4100A1ACUL)
	(DMAC) Channel 22 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET22 ((RwReg8 )0x4100A1ADUL)
	(DMAC) Channel 22 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG22 ((RwReg8 )0x4100A1AEUL)
	(DMAC) Channel 22 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS22 ((RwReg8 )0x4100A1AFUL)
	(DMAC) Channel 22 Status

#define	REG_DMAC_CHCTRLA23 ((RwReg )0x4100A1B0UL)
	(DMAC) Channel 23 Control A

#define	REG_DMAC_CHCTRLB23 ((RwReg8 )0x4100A1B4UL)
	(DMAC) Channel 23 Control B

#define	REG_DMAC_CHPRILVL23 ((RwReg8 )0x4100A1B5UL)
	(DMAC) Channel 23 Priority Level

#define	REG_DMAC_CHEVCTRL23 ((RwReg8 )0x4100A1B6UL)
	(DMAC) Channel 23 Event Control

#define	REG_DMAC_CHINTENCLR23 ((RwReg8 )0x4100A1BCUL)
	(DMAC) Channel 23 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET23 ((RwReg8 )0x4100A1BDUL)
	(DMAC) Channel 23 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG23 ((RwReg8 )0x4100A1BEUL)
	(DMAC) Channel 23 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS23 ((RwReg8 )0x4100A1BFUL)
	(DMAC) Channel 23 Status

#define	REG_DMAC_CHCTRLA24 ((RwReg )0x4100A1C0UL)
	(DMAC) Channel 24 Control A

#define	REG_DMAC_CHCTRLB24 ((RwReg8 )0x4100A1C4UL)
	(DMAC) Channel 24 Control B

#define	REG_DMAC_CHPRILVL24 ((RwReg8 )0x4100A1C5UL)
	(DMAC) Channel 24 Priority Level

#define	REG_DMAC_CHEVCTRL24 ((RwReg8 )0x4100A1C6UL)
	(DMAC) Channel 24 Event Control

#define	REG_DMAC_CHINTENCLR24 ((RwReg8 )0x4100A1CCUL)
	(DMAC) Channel 24 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET24 ((RwReg8 )0x4100A1CDUL)
	(DMAC) Channel 24 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG24 ((RwReg8 )0x4100A1CEUL)
	(DMAC) Channel 24 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS24 ((RwReg8 )0x4100A1CFUL)
	(DMAC) Channel 24 Status

#define	REG_DMAC_CHCTRLA25 ((RwReg )0x4100A1D0UL)
	(DMAC) Channel 25 Control A

#define	REG_DMAC_CHCTRLB25 ((RwReg8 )0x4100A1D4UL)
	(DMAC) Channel 25 Control B

#define	REG_DMAC_CHPRILVL25 ((RwReg8 )0x4100A1D5UL)
	(DMAC) Channel 25 Priority Level

#define	REG_DMAC_CHEVCTRL25 ((RwReg8 )0x4100A1D6UL)
	(DMAC) Channel 25 Event Control

#define	REG_DMAC_CHINTENCLR25 ((RwReg8 )0x4100A1DCUL)
	(DMAC) Channel 25 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET25 ((RwReg8 )0x4100A1DDUL)
	(DMAC) Channel 25 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG25 ((RwReg8 )0x4100A1DEUL)
	(DMAC) Channel 25 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS25 ((RwReg8 )0x4100A1DFUL)
	(DMAC) Channel 25 Status

#define	REG_DMAC_CHCTRLA26 ((RwReg )0x4100A1E0UL)
	(DMAC) Channel 26 Control A

#define	REG_DMAC_CHCTRLB26 ((RwReg8 )0x4100A1E4UL)
	(DMAC) Channel 26 Control B

#define	REG_DMAC_CHPRILVL26 ((RwReg8 )0x4100A1E5UL)
	(DMAC) Channel 26 Priority Level

#define	REG_DMAC_CHEVCTRL26 ((RwReg8 )0x4100A1E6UL)
	(DMAC) Channel 26 Event Control

#define	REG_DMAC_CHINTENCLR26 ((RwReg8 )0x4100A1ECUL)
	(DMAC) Channel 26 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET26 ((RwReg8 )0x4100A1EDUL)
	(DMAC) Channel 26 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG26 ((RwReg8 )0x4100A1EEUL)
	(DMAC) Channel 26 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS26 ((RwReg8 )0x4100A1EFUL)
	(DMAC) Channel 26 Status

#define	REG_DMAC_CHCTRLA27 ((RwReg )0x4100A1F0UL)
	(DMAC) Channel 27 Control A

#define	REG_DMAC_CHCTRLB27 ((RwReg8 )0x4100A1F4UL)
	(DMAC) Channel 27 Control B

#define	REG_DMAC_CHPRILVL27 ((RwReg8 )0x4100A1F5UL)
	(DMAC) Channel 27 Priority Level

#define	REG_DMAC_CHEVCTRL27 ((RwReg8 )0x4100A1F6UL)
	(DMAC) Channel 27 Event Control

#define	REG_DMAC_CHINTENCLR27 ((RwReg8 )0x4100A1FCUL)
	(DMAC) Channel 27 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET27 ((RwReg8 )0x4100A1FDUL)
	(DMAC) Channel 27 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG27 ((RwReg8 )0x4100A1FEUL)
	(DMAC) Channel 27 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS27 ((RwReg8 )0x4100A1FFUL)
	(DMAC) Channel 27 Status

#define	REG_DMAC_CHCTRLA28 ((RwReg )0x4100A200UL)
	(DMAC) Channel 28 Control A

#define	REG_DMAC_CHCTRLB28 ((RwReg8 )0x4100A204UL)
	(DMAC) Channel 28 Control B

#define	REG_DMAC_CHPRILVL28 ((RwReg8 )0x4100A205UL)
	(DMAC) Channel 28 Priority Level

#define	REG_DMAC_CHEVCTRL28 ((RwReg8 )0x4100A206UL)
	(DMAC) Channel 28 Event Control

#define	REG_DMAC_CHINTENCLR28 ((RwReg8 )0x4100A20CUL)
	(DMAC) Channel 28 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET28 ((RwReg8 )0x4100A20DUL)
	(DMAC) Channel 28 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG28 ((RwReg8 )0x4100A20EUL)
	(DMAC) Channel 28 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS28 ((RwReg8 )0x4100A20FUL)
	(DMAC) Channel 28 Status

#define	REG_DMAC_CHCTRLA29 ((RwReg )0x4100A210UL)
	(DMAC) Channel 29 Control A

#define	REG_DMAC_CHCTRLB29 ((RwReg8 )0x4100A214UL)
	(DMAC) Channel 29 Control B

#define	REG_DMAC_CHPRILVL29 ((RwReg8 )0x4100A215UL)
	(DMAC) Channel 29 Priority Level

#define	REG_DMAC_CHEVCTRL29 ((RwReg8 )0x4100A216UL)
	(DMAC) Channel 29 Event Control

#define	REG_DMAC_CHINTENCLR29 ((RwReg8 )0x4100A21CUL)
	(DMAC) Channel 29 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET29 ((RwReg8 )0x4100A21DUL)
	(DMAC) Channel 29 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG29 ((RwReg8 )0x4100A21EUL)
	(DMAC) Channel 29 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS29 ((RwReg8 )0x4100A21FUL)
	(DMAC) Channel 29 Status

#define	REG_DMAC_CHCTRLA30 ((RwReg )0x4100A220UL)
	(DMAC) Channel 30 Control A

#define	REG_DMAC_CHCTRLB30 ((RwReg8 )0x4100A224UL)
	(DMAC) Channel 30 Control B

#define	REG_DMAC_CHPRILVL30 ((RwReg8 )0x4100A225UL)
	(DMAC) Channel 30 Priority Level

#define	REG_DMAC_CHEVCTRL30 ((RwReg8 )0x4100A226UL)
	(DMAC) Channel 30 Event Control

#define	REG_DMAC_CHINTENCLR30 ((RwReg8 )0x4100A22CUL)
	(DMAC) Channel 30 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET30 ((RwReg8 )0x4100A22DUL)
	(DMAC) Channel 30 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG30 ((RwReg8 )0x4100A22EUL)
	(DMAC) Channel 30 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS30 ((RwReg8 )0x4100A22FUL)
	(DMAC) Channel 30 Status

#define	REG_DMAC_CHCTRLA31 ((RwReg )0x4100A230UL)
	(DMAC) Channel 31 Control A

#define	REG_DMAC_CHCTRLB31 ((RwReg8 )0x4100A234UL)
	(DMAC) Channel 31 Control B

#define	REG_DMAC_CHPRILVL31 ((RwReg8 )0x4100A235UL)
	(DMAC) Channel 31 Priority Level

#define	REG_DMAC_CHEVCTRL31 ((RwReg8 )0x4100A236UL)
	(DMAC) Channel 31 Event Control

#define	REG_DMAC_CHINTENCLR31 ((RwReg8 )0x4100A23CUL)
	(DMAC) Channel 31 Interrupt Enable Clear

#define	REG_DMAC_CHINTENSET31 ((RwReg8 )0x4100A23DUL)
	(DMAC) Channel 31 Interrupt Enable Set

#define	REG_DMAC_CHINTFLAG31 ((RwReg8 )0x4100A23EUL)
	(DMAC) Channel 31 Interrupt Flag Status and Clear

#define	REG_DMAC_CHSTATUS31 ((RwReg8 )0x4100A23FUL)
	(DMAC) Channel 31 Status

#define	DMAC_BURST 1

#define	DMAC_CH_BITS 5

#define	DMAC_CH_NUM 32

#define	DMAC_CLK_AHB_ID 9

#define	DMAC_EVIN_NUM 8

#define	DMAC_EVOUT_NUM 4

#define	DMAC_FIFO_SIZE 16

#define	DMAC_LVL_BITS 2

#define	DMAC_LVL_NUM 4

#define	DMAC_QOSCTRL_D_RESETVALUE 2

#define	DMAC_QOSCTRL_F_RESETVALUE 2

#define	DMAC_QOSCTRL_WRB_RESETVALUE 2

#define	DMAC_TRIG_BITS 7

#define	DMAC_TRIG_NUM 85

Detailed Description

Instance description for DMAC.

\asf_license_start

Definition in file dmac.h.

Macros

Detailed Description