SAME54P20A Test Project
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Instance description for CMCC. More...
Go to the source code of this file.
Macros | |
#define | REG_CMCC_TYPE (*(RoReg *)0x41006000UL) |
(CMCC) Cache Type Register | |
#define | REG_CMCC_CFG (*(RwReg *)0x41006004UL) |
(CMCC) Cache Configuration Register | |
#define | REG_CMCC_CTRL (*(WoReg *)0x41006008UL) |
(CMCC) Cache Control Register | |
#define | REG_CMCC_SR (*(RoReg *)0x4100600CUL) |
(CMCC) Cache Status Register | |
#define | REG_CMCC_LCKWAY (*(RwReg *)0x41006010UL) |
(CMCC) Cache Lock per Way Register | |
#define | REG_CMCC_MAINT0 (*(WoReg *)0x41006020UL) |
(CMCC) Cache Maintenance Register 0 | |
#define | REG_CMCC_MAINT1 (*(WoReg *)0x41006024UL) |
(CMCC) Cache Maintenance Register 1 | |
#define | REG_CMCC_MCFG (*(RwReg *)0x41006028UL) |
(CMCC) Cache Monitor Configuration Register | |
#define | REG_CMCC_MEN (*(RwReg *)0x4100602CUL) |
(CMCC) Cache Monitor Enable Register | |
#define | REG_CMCC_MCTRL (*(WoReg *)0x41006030UL) |
(CMCC) Cache Monitor Control Register | |
#define | REG_CMCC_MSR (*(RoReg *)0x41006034UL) |
(CMCC) Cache Monitor Status Register | |
Instance description for CMCC.
Copyright (c) 2019 Microchip Technology Inc.
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Definition in file cmcc.h.