Component description for EIC. More...

Data Structures
union	EIC_CTRLA_Type

union	EIC_NMICTRL_Type

union	EIC_NMIFLAG_Type

union	EIC_SYNCBUSY_Type

union	EIC_EVCTRL_Type

union	EIC_INTENCLR_Type

union	EIC_INTENSET_Type

union	EIC_INTFLAG_Type

union	EIC_ASYNCH_Type

union	EIC_CONFIG_Type

union	EIC_DEBOUNCEN_Type

union	EIC_DPRESCALER_Type

union	EIC_PINSTATE_Type

struct	Eic
	EIC hardware registers. More...

Macros
#define	EIC_U2254

#define	REV_EIC 0x300

#define	EIC_CTRLA_OFFSET 0x00
	(EIC_CTRLA offset) Control A

#define	EIC_CTRLA_RESETVALUE _U_(0x00)
	(EIC_CTRLA reset_value) Control A

#define	EIC_CTRLA_SWRST_Pos 0
	(EIC_CTRLA) Software Reset

#define	EIC_CTRLA_SWRST (_U_(0x1) << EIC_CTRLA_SWRST_Pos)

#define	EIC_CTRLA_ENABLE_Pos 1
	(EIC_CTRLA) Enable

#define	EIC_CTRLA_ENABLE (_U_(0x1) << EIC_CTRLA_ENABLE_Pos)

#define	EIC_CTRLA_CKSEL_Pos 4
	(EIC_CTRLA) Clock Selection

#define	EIC_CTRLA_CKSEL (_U_(0x1) << EIC_CTRLA_CKSEL_Pos)

#define	EIC_CTRLA_MASK _U_(0x13)
	(EIC_CTRLA) MASK Register

#define	EIC_NMICTRL_OFFSET 0x01
	(EIC_NMICTRL offset) Non-Maskable Interrupt Control

#define	EIC_NMICTRL_RESETVALUE _U_(0x00)
	(EIC_NMICTRL reset_value) Non-Maskable Interrupt Control

#define	EIC_NMICTRL_NMISENSE_Pos 0
	(EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration

#define	EIC_NMICTRL_NMISENSE_Msk (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos)

#define	EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))

#define	EIC_NMICTRL_NMISENSE_NONE_Val _U_(0x0)
	(EIC_NMICTRL) No detection

#define	EIC_NMICTRL_NMISENSE_RISE_Val _U_(0x1)
	(EIC_NMICTRL) Rising-edge detection

#define	EIC_NMICTRL_NMISENSE_FALL_Val _U_(0x2)
	(EIC_NMICTRL) Falling-edge detection

#define	EIC_NMICTRL_NMISENSE_BOTH_Val _U_(0x3)
	(EIC_NMICTRL) Both-edges detection

#define	EIC_NMICTRL_NMISENSE_HIGH_Val _U_(0x4)
	(EIC_NMICTRL) High-level detection

#define	EIC_NMICTRL_NMISENSE_LOW_Val _U_(0x5)
	(EIC_NMICTRL) Low-level detection

#define	EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)

#define	EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)

#define	EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)

#define	EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)

#define	EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)

#define	EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)

#define	EIC_NMICTRL_NMIFILTEN_Pos 3
	(EIC_NMICTRL) Non-Maskable Interrupt Filter Enable

#define	EIC_NMICTRL_NMIFILTEN (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)

#define	EIC_NMICTRL_NMIASYNCH_Pos 4
	(EIC_NMICTRL) Asynchronous Edge Detection Mode

#define	EIC_NMICTRL_NMIASYNCH (_U_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos)

#define	EIC_NMICTRL_MASK _U_(0x1F)
	(EIC_NMICTRL) MASK Register

#define	EIC_NMIFLAG_OFFSET 0x02
	(EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear

#define	EIC_NMIFLAG_RESETVALUE _U_(0x0000)
	(EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear

#define	EIC_NMIFLAG_NMI_Pos 0
	(EIC_NMIFLAG) Non-Maskable Interrupt

#define	EIC_NMIFLAG_NMI (_U_(0x1) << EIC_NMIFLAG_NMI_Pos)

#define	EIC_NMIFLAG_MASK _U_(0x0001)
	(EIC_NMIFLAG) MASK Register

#define	EIC_SYNCBUSY_OFFSET 0x04
	(EIC_SYNCBUSY offset) Synchronization Busy

#define	EIC_SYNCBUSY_RESETVALUE _U_(0x00000000)
	(EIC_SYNCBUSY reset_value) Synchronization Busy

#define	EIC_SYNCBUSY_SWRST_Pos 0
	(EIC_SYNCBUSY) Software Reset Synchronization Busy Status

#define	EIC_SYNCBUSY_SWRST (_U_(0x1) << EIC_SYNCBUSY_SWRST_Pos)

#define	EIC_SYNCBUSY_ENABLE_Pos 1
	(EIC_SYNCBUSY) Enable Synchronization Busy Status

#define	EIC_SYNCBUSY_ENABLE (_U_(0x1) << EIC_SYNCBUSY_ENABLE_Pos)

#define	EIC_SYNCBUSY_MASK _U_(0x00000003)
	(EIC_SYNCBUSY) MASK Register

#define	EIC_EVCTRL_OFFSET 0x08
	(EIC_EVCTRL offset) Event Control

#define	EIC_EVCTRL_RESETVALUE _U_(0x00000000)
	(EIC_EVCTRL reset_value) Event Control

#define	EIC_EVCTRL_EXTINTEO_Pos 0
	(EIC_EVCTRL) External Interrupt Event Output Enable

#define	EIC_EVCTRL_EXTINTEO_Msk (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)

#define	EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))

#define	EIC_EVCTRL_MASK _U_(0x0000FFFF)
	(EIC_EVCTRL) MASK Register

#define	EIC_INTENCLR_OFFSET 0x0C
	(EIC_INTENCLR offset) Interrupt Enable Clear

#define	EIC_INTENCLR_RESETVALUE _U_(0x00000000)
	(EIC_INTENCLR reset_value) Interrupt Enable Clear

#define	EIC_INTENCLR_EXTINT_Pos 0
	(EIC_INTENCLR) External Interrupt Enable

#define	EIC_INTENCLR_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)

#define	EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))

#define	EIC_INTENCLR_MASK _U_(0x0000FFFF)
	(EIC_INTENCLR) MASK Register

#define	EIC_INTENSET_OFFSET 0x10
	(EIC_INTENSET offset) Interrupt Enable Set

#define	EIC_INTENSET_RESETVALUE _U_(0x00000000)
	(EIC_INTENSET reset_value) Interrupt Enable Set

#define	EIC_INTENSET_EXTINT_Pos 0
	(EIC_INTENSET) External Interrupt Enable

#define	EIC_INTENSET_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos)

#define	EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))

#define	EIC_INTENSET_MASK _U_(0x0000FFFF)
	(EIC_INTENSET) MASK Register

#define	EIC_INTFLAG_OFFSET 0x14
	(EIC_INTFLAG offset) Interrupt Flag Status and Clear

#define	EIC_INTFLAG_RESETVALUE _U_(0x00000000)
	(EIC_INTFLAG reset_value) Interrupt Flag Status and Clear

#define	EIC_INTFLAG_EXTINT_Pos 0
	(EIC_INTFLAG) External Interrupt

#define	EIC_INTFLAG_EXTINT_Msk (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)

#define	EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))

#define	EIC_INTFLAG_MASK _U_(0x0000FFFF)
	(EIC_INTFLAG) MASK Register

#define	EIC_ASYNCH_OFFSET 0x18
	(EIC_ASYNCH offset) External Interrupt Asynchronous Mode

#define	EIC_ASYNCH_RESETVALUE _U_(0x00000000)
	(EIC_ASYNCH reset_value) External Interrupt Asynchronous Mode

#define	EIC_ASYNCH_ASYNCH_Pos 0
	(EIC_ASYNCH) Asynchronous Edge Detection Mode

#define	EIC_ASYNCH_ASYNCH_Msk (_U_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos)

#define	EIC_ASYNCH_ASYNCH(value) (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos))

#define	EIC_ASYNCH_MASK _U_(0x0000FFFF)
	(EIC_ASYNCH) MASK Register

#define	EIC_CONFIG_OFFSET 0x1C
	(EIC_CONFIG offset) External Interrupt Sense Configuration

#define	EIC_CONFIG_RESETVALUE _U_(0x00000000)
	(EIC_CONFIG reset_value) External Interrupt Sense Configuration

#define	EIC_CONFIG_SENSE0_Pos 0
	(EIC_CONFIG) Input Sense Configuration 0

#define	EIC_CONFIG_SENSE0_Msk (_U_(0x7) << EIC_CONFIG_SENSE0_Pos)

#define	EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))

#define	EIC_CONFIG_SENSE0_NONE_Val _U_(0x0)
	(EIC_CONFIG) No detection

#define	EIC_CONFIG_SENSE0_RISE_Val _U_(0x1)
	(EIC_CONFIG) Rising edge detection

#define	EIC_CONFIG_SENSE0_FALL_Val _U_(0x2)
	(EIC_CONFIG) Falling edge detection

#define	EIC_CONFIG_SENSE0_BOTH_Val _U_(0x3)
	(EIC_CONFIG) Both edges detection

#define	EIC_CONFIG_SENSE0_HIGH_Val _U_(0x4)
	(EIC_CONFIG) High level detection

#define	EIC_CONFIG_SENSE0_LOW_Val _U_(0x5)
	(EIC_CONFIG) Low level detection

#define	EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)

#define	EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)

#define	EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)

#define	EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)

#define	EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)

#define	EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)

#define	EIC_CONFIG_FILTEN0_Pos 3
	(EIC_CONFIG) Filter Enable 0

#define	EIC_CONFIG_FILTEN0 (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos)

#define	EIC_CONFIG_SENSE1_Pos 4
	(EIC_CONFIG) Input Sense Configuration 1

#define	EIC_CONFIG_SENSE1_Msk (_U_(0x7) << EIC_CONFIG_SENSE1_Pos)

#define	EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))

#define	EIC_CONFIG_SENSE1_NONE_Val _U_(0x0)
	(EIC_CONFIG) No detection

#define	EIC_CONFIG_SENSE1_RISE_Val _U_(0x1)
	(EIC_CONFIG) Rising edge detection

#define	EIC_CONFIG_SENSE1_FALL_Val _U_(0x2)
	(EIC_CONFIG) Falling edge detection

#define	EIC_CONFIG_SENSE1_BOTH_Val _U_(0x3)
	(EIC_CONFIG) Both edges detection

#define	EIC_CONFIG_SENSE1_HIGH_Val _U_(0x4)
	(EIC_CONFIG) High level detection

#define	EIC_CONFIG_SENSE1_LOW_Val _U_(0x5)
	(EIC_CONFIG) Low level detection

#define	EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)

#define	EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)

#define	EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)

#define	EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)

#define	EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)

#define	EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)

#define	EIC_CONFIG_FILTEN1_Pos 7
	(EIC_CONFIG) Filter Enable 1

#define	EIC_CONFIG_FILTEN1 (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos)

#define	EIC_CONFIG_SENSE2_Pos 8
	(EIC_CONFIG) Input Sense Configuration 2

#define	EIC_CONFIG_SENSE2_Msk (_U_(0x7) << EIC_CONFIG_SENSE2_Pos)

#define	EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))

#define	EIC_CONFIG_SENSE2_NONE_Val _U_(0x0)
	(EIC_CONFIG) No detection

#define	EIC_CONFIG_SENSE2_RISE_Val _U_(0x1)
	(EIC_CONFIG) Rising edge detection

#define	EIC_CONFIG_SENSE2_FALL_Val _U_(0x2)
	(EIC_CONFIG) Falling edge detection

#define	EIC_CONFIG_SENSE2_BOTH_Val _U_(0x3)
	(EIC_CONFIG) Both edges detection

#define	EIC_CONFIG_SENSE2_HIGH_Val _U_(0x4)
	(EIC_CONFIG) High level detection

#define	EIC_CONFIG_SENSE2_LOW_Val _U_(0x5)
	(EIC_CONFIG) Low level detection

#define	EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)

#define	EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)

#define	EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)

#define	EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)

#define	EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)

#define	EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)

#define	EIC_CONFIG_FILTEN2_Pos 11
	(EIC_CONFIG) Filter Enable 2

#define	EIC_CONFIG_FILTEN2 (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos)

#define	EIC_CONFIG_SENSE3_Pos 12
	(EIC_CONFIG) Input Sense Configuration 3

#define	EIC_CONFIG_SENSE3_Msk (_U_(0x7) << EIC_CONFIG_SENSE3_Pos)

#define	EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))

#define	EIC_CONFIG_SENSE3_NONE_Val _U_(0x0)
	(EIC_CONFIG) No detection

#define	EIC_CONFIG_SENSE3_RISE_Val _U_(0x1)
	(EIC_CONFIG) Rising edge detection

#define	EIC_CONFIG_SENSE3_FALL_Val _U_(0x2)
	(EIC_CONFIG) Falling edge detection

#define	EIC_CONFIG_SENSE3_BOTH_Val _U_(0x3)
	(EIC_CONFIG) Both edges detection

#define	EIC_CONFIG_SENSE3_HIGH_Val _U_(0x4)
	(EIC_CONFIG) High level detection

#define	EIC_CONFIG_SENSE3_LOW_Val _U_(0x5)
	(EIC_CONFIG) Low level detection

#define	EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)

#define	EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)

#define	EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)

#define	EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)

#define	EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)

#define	EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)

#define	EIC_CONFIG_FILTEN3_Pos 15
	(EIC_CONFIG) Filter Enable 3

#define	EIC_CONFIG_FILTEN3 (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos)

#define	EIC_CONFIG_SENSE4_Pos 16
	(EIC_CONFIG) Input Sense Configuration 4

#define	EIC_CONFIG_SENSE4_Msk (_U_(0x7) << EIC_CONFIG_SENSE4_Pos)

#define	EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))

#define	EIC_CONFIG_SENSE4_NONE_Val _U_(0x0)
	(EIC_CONFIG) No detection

#define	EIC_CONFIG_SENSE4_RISE_Val _U_(0x1)
	(EIC_CONFIG) Rising edge detection

#define	EIC_CONFIG_SENSE4_FALL_Val _U_(0x2)
	(EIC_CONFIG) Falling edge detection

#define	EIC_CONFIG_SENSE4_BOTH_Val _U_(0x3)
	(EIC_CONFIG) Both edges detection

#define	EIC_CONFIG_SENSE4_HIGH_Val _U_(0x4)
	(EIC_CONFIG) High level detection

#define	EIC_CONFIG_SENSE4_LOW_Val _U_(0x5)
	(EIC_CONFIG) Low level detection

#define	EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)

#define	EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)

#define	EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)

#define	EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)

#define	EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)

#define	EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)

#define	EIC_CONFIG_FILTEN4_Pos 19
	(EIC_CONFIG) Filter Enable 4

#define	EIC_CONFIG_FILTEN4 (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos)

#define	EIC_CONFIG_SENSE5_Pos 20
	(EIC_CONFIG) Input Sense Configuration 5

#define	EIC_CONFIG_SENSE5_Msk (_U_(0x7) << EIC_CONFIG_SENSE5_Pos)

#define	EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))

#define	EIC_CONFIG_SENSE5_NONE_Val _U_(0x0)
	(EIC_CONFIG) No detection

#define	EIC_CONFIG_SENSE5_RISE_Val _U_(0x1)
	(EIC_CONFIG) Rising edge detection

#define	EIC_CONFIG_SENSE5_FALL_Val _U_(0x2)
	(EIC_CONFIG) Falling edge detection

#define	EIC_CONFIG_SENSE5_BOTH_Val _U_(0x3)
	(EIC_CONFIG) Both edges detection

#define	EIC_CONFIG_SENSE5_HIGH_Val _U_(0x4)
	(EIC_CONFIG) High level detection

#define	EIC_CONFIG_SENSE5_LOW_Val _U_(0x5)
	(EIC_CONFIG) Low level detection

#define	EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)

#define	EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)

#define	EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)

#define	EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)

#define	EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)

#define	EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)

#define	EIC_CONFIG_FILTEN5_Pos 23
	(EIC_CONFIG) Filter Enable 5

#define	EIC_CONFIG_FILTEN5 (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos)

#define	EIC_CONFIG_SENSE6_Pos 24
	(EIC_CONFIG) Input Sense Configuration 6

#define	EIC_CONFIG_SENSE6_Msk (_U_(0x7) << EIC_CONFIG_SENSE6_Pos)

#define	EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))

#define	EIC_CONFIG_SENSE6_NONE_Val _U_(0x0)
	(EIC_CONFIG) No detection

#define	EIC_CONFIG_SENSE6_RISE_Val _U_(0x1)
	(EIC_CONFIG) Rising edge detection

#define	EIC_CONFIG_SENSE6_FALL_Val _U_(0x2)
	(EIC_CONFIG) Falling edge detection

#define	EIC_CONFIG_SENSE6_BOTH_Val _U_(0x3)
	(EIC_CONFIG) Both edges detection

#define	EIC_CONFIG_SENSE6_HIGH_Val _U_(0x4)
	(EIC_CONFIG) High level detection

#define	EIC_CONFIG_SENSE6_LOW_Val _U_(0x5)
	(EIC_CONFIG) Low level detection

#define	EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)

#define	EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)

#define	EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)

#define	EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)

#define	EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)

#define	EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)

#define	EIC_CONFIG_FILTEN6_Pos 27
	(EIC_CONFIG) Filter Enable 6

#define	EIC_CONFIG_FILTEN6 (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos)

#define	EIC_CONFIG_SENSE7_Pos 28
	(EIC_CONFIG) Input Sense Configuration 7

#define	EIC_CONFIG_SENSE7_Msk (_U_(0x7) << EIC_CONFIG_SENSE7_Pos)

#define	EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))

#define	EIC_CONFIG_SENSE7_NONE_Val _U_(0x0)
	(EIC_CONFIG) No detection

#define	EIC_CONFIG_SENSE7_RISE_Val _U_(0x1)
	(EIC_CONFIG) Rising edge detection

#define	EIC_CONFIG_SENSE7_FALL_Val _U_(0x2)
	(EIC_CONFIG) Falling edge detection

#define	EIC_CONFIG_SENSE7_BOTH_Val _U_(0x3)
	(EIC_CONFIG) Both edges detection

#define	EIC_CONFIG_SENSE7_HIGH_Val _U_(0x4)
	(EIC_CONFIG) High level detection

#define	EIC_CONFIG_SENSE7_LOW_Val _U_(0x5)
	(EIC_CONFIG) Low level detection

#define	EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)

#define	EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)

#define	EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)

#define	EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)

#define	EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)

#define	EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)

#define	EIC_CONFIG_FILTEN7_Pos 31
	(EIC_CONFIG) Filter Enable 7

#define	EIC_CONFIG_FILTEN7 (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos)

#define	EIC_CONFIG_MASK _U_(0xFFFFFFFF)
	(EIC_CONFIG) MASK Register

#define	EIC_DEBOUNCEN_OFFSET 0x30
	(EIC_DEBOUNCEN offset) Debouncer Enable

#define	EIC_DEBOUNCEN_RESETVALUE _U_(0x00000000)
	(EIC_DEBOUNCEN reset_value) Debouncer Enable

#define	EIC_DEBOUNCEN_DEBOUNCEN_Pos 0
	(EIC_DEBOUNCEN) Debouncer Enable

#define	EIC_DEBOUNCEN_DEBOUNCEN_Msk (_U_(0xFFFF) << EIC_DEBOUNCEN_DEBOUNCEN_Pos)

#define	EIC_DEBOUNCEN_DEBOUNCEN(value) (EIC_DEBOUNCEN_DEBOUNCEN_Msk & ((value) << EIC_DEBOUNCEN_DEBOUNCEN_Pos))

#define	EIC_DEBOUNCEN_MASK _U_(0x0000FFFF)
	(EIC_DEBOUNCEN) MASK Register

#define	EIC_DPRESCALER_OFFSET 0x34
	(EIC_DPRESCALER offset) Debouncer Prescaler

#define	EIC_DPRESCALER_RESETVALUE _U_(0x00000000)
	(EIC_DPRESCALER reset_value) Debouncer Prescaler

#define	EIC_DPRESCALER_PRESCALER0_Pos 0
	(EIC_DPRESCALER) Debouncer Prescaler

#define	EIC_DPRESCALER_PRESCALER0_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER0_Pos)

#define	EIC_DPRESCALER_PRESCALER0(value) (EIC_DPRESCALER_PRESCALER0_Msk & ((value) << EIC_DPRESCALER_PRESCALER0_Pos))

#define	EIC_DPRESCALER_STATES0_Pos 3
	(EIC_DPRESCALER) Debouncer number of states

#define	EIC_DPRESCALER_STATES0 (_U_(0x1) << EIC_DPRESCALER_STATES0_Pos)

#define	EIC_DPRESCALER_PRESCALER1_Pos 4
	(EIC_DPRESCALER) Debouncer Prescaler

#define	EIC_DPRESCALER_PRESCALER1_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER1_Pos)

#define	EIC_DPRESCALER_PRESCALER1(value) (EIC_DPRESCALER_PRESCALER1_Msk & ((value) << EIC_DPRESCALER_PRESCALER1_Pos))

#define	EIC_DPRESCALER_STATES1_Pos 7
	(EIC_DPRESCALER) Debouncer number of states

#define	EIC_DPRESCALER_STATES1 (_U_(0x1) << EIC_DPRESCALER_STATES1_Pos)

#define	EIC_DPRESCALER_TICKON_Pos 16
	(EIC_DPRESCALER) Pin Sampler frequency selection

#define	EIC_DPRESCALER_TICKON (_U_(0x1) << EIC_DPRESCALER_TICKON_Pos)

#define	EIC_DPRESCALER_MASK _U_(0x000100FF)
	(EIC_DPRESCALER) MASK Register

#define	EIC_PINSTATE_OFFSET 0x38
	(EIC_PINSTATE offset) Pin State

#define	EIC_PINSTATE_RESETVALUE _U_(0x00000000)
	(EIC_PINSTATE reset_value) Pin State

#define	EIC_PINSTATE_PINSTATE_Pos 0
	(EIC_PINSTATE) Pin State

#define	EIC_PINSTATE_PINSTATE_Msk (_U_(0xFFFF) << EIC_PINSTATE_PINSTATE_Pos)

#define	EIC_PINSTATE_PINSTATE(value) (EIC_PINSTATE_PINSTATE_Msk & ((value) << EIC_PINSTATE_PINSTATE_Pos))

#define	EIC_PINSTATE_MASK _U_(0x0000FFFF)
	(EIC_PINSTATE) MASK Register

Detailed Description

Component description for EIC.

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Definition in file eic.h.

Data Structures

Macros

Detailed Description