SAME54P20A Test Project
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Instance description for TCC0. More...
Go to the source code of this file.
Macros | |
#define | REG_TCC0_CTRLA (*(RwReg *)0x41016000UL) |
(TCC0) Control A | |
#define | REG_TCC0_CTRLBCLR (*(RwReg8 *)0x41016004UL) |
(TCC0) Control B Clear | |
#define | REG_TCC0_CTRLBSET (*(RwReg8 *)0x41016005UL) |
(TCC0) Control B Set | |
#define | REG_TCC0_SYNCBUSY (*(RoReg *)0x41016008UL) |
(TCC0) Synchronization Busy | |
#define | REG_TCC0_FCTRLA (*(RwReg *)0x4101600CUL) |
(TCC0) Recoverable Fault A Configuration | |
#define | REG_TCC0_FCTRLB (*(RwReg *)0x41016010UL) |
(TCC0) Recoverable Fault B Configuration | |
#define | REG_TCC0_WEXCTRL (*(RwReg *)0x41016014UL) |
(TCC0) Waveform Extension Configuration | |
#define | REG_TCC0_DRVCTRL (*(RwReg *)0x41016018UL) |
(TCC0) Driver Control | |
#define | REG_TCC0_DBGCTRL (*(RwReg8 *)0x4101601EUL) |
(TCC0) Debug Control | |
#define | REG_TCC0_EVCTRL (*(RwReg *)0x41016020UL) |
(TCC0) Event Control | |
#define | REG_TCC0_INTENCLR (*(RwReg *)0x41016024UL) |
(TCC0) Interrupt Enable Clear | |
#define | REG_TCC0_INTENSET (*(RwReg *)0x41016028UL) |
(TCC0) Interrupt Enable Set | |
#define | REG_TCC0_INTFLAG (*(RwReg *)0x4101602CUL) |
(TCC0) Interrupt Flag Status and Clear | |
#define | REG_TCC0_STATUS (*(RwReg *)0x41016030UL) |
(TCC0) Status | |
#define | REG_TCC0_COUNT (*(RwReg *)0x41016034UL) |
(TCC0) Count | |
#define | REG_TCC0_PATT (*(RwReg16*)0x41016038UL) |
(TCC0) Pattern | |
#define | REG_TCC0_WAVE (*(RwReg *)0x4101603CUL) |
(TCC0) Waveform Control | |
#define | REG_TCC0_PER (*(RwReg *)0x41016040UL) |
(TCC0) Period | |
#define | REG_TCC0_CC0 (*(RwReg *)0x41016044UL) |
(TCC0) Compare and Capture 0 | |
#define | REG_TCC0_CC1 (*(RwReg *)0x41016048UL) |
(TCC0) Compare and Capture 1 | |
#define | REG_TCC0_CC2 (*(RwReg *)0x4101604CUL) |
(TCC0) Compare and Capture 2 | |
#define | REG_TCC0_CC3 (*(RwReg *)0x41016050UL) |
(TCC0) Compare and Capture 3 | |
#define | REG_TCC0_CC4 (*(RwReg *)0x41016054UL) |
(TCC0) Compare and Capture 4 | |
#define | REG_TCC0_CC5 (*(RwReg *)0x41016058UL) |
(TCC0) Compare and Capture 5 | |
#define | REG_TCC0_PATTBUF (*(RwReg16*)0x41016064UL) |
(TCC0) Pattern Buffer | |
#define | REG_TCC0_PERBUF (*(RwReg *)0x4101606CUL) |
(TCC0) Period Buffer | |
#define | REG_TCC0_CCBUF0 (*(RwReg *)0x41016070UL) |
(TCC0) Compare and Capture Buffer 0 | |
#define | REG_TCC0_CCBUF1 (*(RwReg *)0x41016074UL) |
(TCC0) Compare and Capture Buffer 1 | |
#define | REG_TCC0_CCBUF2 (*(RwReg *)0x41016078UL) |
(TCC0) Compare and Capture Buffer 2 | |
#define | REG_TCC0_CCBUF3 (*(RwReg *)0x4101607CUL) |
(TCC0) Compare and Capture Buffer 3 | |
#define | REG_TCC0_CCBUF4 (*(RwReg *)0x41016080UL) |
(TCC0) Compare and Capture Buffer 4 | |
#define | REG_TCC0_CCBUF5 (*(RwReg *)0x41016084UL) |
(TCC0) Compare and Capture Buffer 5 | |
#define | TCC0_CC_NUM 6 |
#define | TCC0_DITHERING 1 |
#define | TCC0_DMAC_ID_MC_0 23 |
#define | TCC0_DMAC_ID_MC_1 24 |
#define | TCC0_DMAC_ID_MC_2 25 |
#define | TCC0_DMAC_ID_MC_3 26 |
#define | TCC0_DMAC_ID_MC_4 27 |
#define | TCC0_DMAC_ID_MC_5 28 |
#define | TCC0_DMAC_ID_MC_LSB 23 |
#define | TCC0_DMAC_ID_MC_MSB 28 |
#define | TCC0_DMAC_ID_MC_SIZE 6 |
#define | TCC0_DMAC_ID_OVF 22 |
#define | TCC0_DTI 1 |
#define | TCC0_EXT 31 |
#define | TCC0_GCLK_ID 25 |
#define | TCC0_MASTER_SLAVE_MODE 1 |
#define | TCC0_OTMX 1 |
#define | TCC0_OW_NUM 8 |
#define | TCC0_PG 1 |
#define | TCC0_SIZE 24 |
#define | TCC0_SWAP 1 |
Instance description for TCC0.
Copyright (c) 2019 Microchip Technology Inc.
\asf_license_start
Definition in file tcc0.h.