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SAME54P20A Test Project
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OSCCTRL hardware registers. More...
#include <oscctrl.h>
Data Fields | |
| __IO OSCCTRL_EVCTRL_Type | EVCTRL |
| Offset: 0x00 (R/W 8) Event Control. | |
| RoReg8 | Reserved1 [0x3] |
| __IO OSCCTRL_INTENCLR_Type | INTENCLR |
| Offset: 0x04 (R/W 32) Interrupt Enable Clear. | |
| __IO OSCCTRL_INTENSET_Type | INTENSET |
| Offset: 0x08 (R/W 32) Interrupt Enable Set. | |
| __IO OSCCTRL_INTFLAG_Type | INTFLAG |
| Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear. | |
| __I OSCCTRL_STATUS_Type | STATUS |
| Offset: 0x10 (R/ 32) Status. | |
| __IO OSCCTRL_XOSCCTRL_Type | XOSCCTRL [2] |
| Offset: 0x14 (R/W 32) External Multipurpose Crystal Oscillator Control. | |
| __IO OSCCTRL_DFLLCTRLA_Type | DFLLCTRLA |
| Offset: 0x1C (R/W 8) DFLL48M Control A. | |
| RoReg8 | Reserved2 [0x3] |
| __IO OSCCTRL_DFLLCTRLB_Type | DFLLCTRLB |
| Offset: 0x20 (R/W 8) DFLL48M Control B. | |
| RoReg8 | Reserved3 [0x3] |
| __IO OSCCTRL_DFLLVAL_Type | DFLLVAL |
| Offset: 0x24 (R/W 32) DFLL48M Value. | |
| __IO OSCCTRL_DFLLMUL_Type | DFLLMUL |
| Offset: 0x28 (R/W 32) DFLL48M Multiplier. | |
| __IO OSCCTRL_DFLLSYNC_Type | DFLLSYNC |
| Offset: 0x2C (R/W 8) DFLL48M Synchronization. | |
| RoReg8 | Reserved4 [0x3] |
| OscctrlDpll | Dpll [2] |
| Offset: 0x30 OscctrlDpll groups [DPLLS_NUM]. | |
1.8.20