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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Adc Struct Reference</div> </div>
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<p>ADC hardware registers.
<a href="structAdc.html#details">More...</a></p>
<p><code>#include <<a class="el" href="adc_8h_source.html">adc.h</a>></code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:ab3df0d5e21bc31d52cd54efb82840a84"><td class="memItemLeft" align="right" valign="top"><a id="ab3df0d5e21bc31d52cd54efb82840a84"></a>
__IO <a class="el" href="unionADC__CTRLA__Type.html">ADC_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structAdc.html#ab3df0d5e21bc31d52cd54efb82840a84">CTRLA</a></td></tr>
<tr class="memdesc:ab3df0d5e21bc31d52cd54efb82840a84"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 16) Control A. <br /></td></tr>
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<tr class="memdesc:a09f9dfbbadbc51a36cf4f8c0fcb41e35"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02 (R/W 8) Event Control. <br /></td></tr>
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<tr class="memdesc:a1ad090f498e2ce3d2b6e7b86931a0c7a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 16) Input Control. <br /></td></tr>
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<tr class="memdesc:a8c7b4543b3b320cbe078bd58fb7df93c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x06 (R/W 16) Control B. <br /></td></tr>
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<tr class="memdesc:a2ad691325acf2f381dda3f3dd66096b5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 8) Reference Control. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x1]</td></tr>
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<tr class="memdesc:a39cd0bd31779c0c1c5d3c4e058105a57"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0A (R/W 8) Average Control. <br /></td></tr>
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<tr class="memdesc:a18d68f2b4bae9ac3eefb839029c1bc84"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0B (R/W 8) Sample Time Control. <br /></td></tr>
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<tr class="memdesc:a8a6d9b6cf625bd8af5f6ad59ad484b73"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 16) Window Monitor Lower Threshold. <br /></td></tr>
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<tr class="memdesc:a486eb898066a8e9203b368556372a92d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0E (R/W 16) Window Monitor Upper Threshold. <br /></td></tr>
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<tr class="memdesc:a25c34c42fd09b099541c05b244f4acc5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/W 16) Gain Correction. <br /></td></tr>
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<tr class="memdesc:a797f96e8f37446dace23eeafbf3cf3b5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x12 (R/W 16) Offset Correction. <br /></td></tr>
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<tr class="memitem:ad3f43aead8dc3b79cb34f4afb5ccdecc"><td class="memItemLeft" align="right" valign="top"><a id="ad3f43aead8dc3b79cb34f4afb5ccdecc"></a>
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<tr class="memdesc:ad3f43aead8dc3b79cb34f4afb5ccdecc"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 8) Software Trigger. <br /></td></tr>
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<tr class="memitem:a7a8c0ccfb26b7e4312944d2c19b3e4ab"><td class="memItemLeft" align="right" valign="top"><a id="a7a8c0ccfb26b7e4312944d2c19b3e4ab"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x17]</td></tr>
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__IO <a class="el" href="unionADC__INTENCLR__Type.html">ADC_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structAdc.html#a81adb67cdacbd126e0a65f1b555f0221">INTENCLR</a></td></tr>
<tr class="memdesc:a81adb67cdacbd126e0a65f1b555f0221"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x2C (R/W 8) Interrupt Enable Clear. <br /></td></tr>
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__IO <a class="el" href="unionADC__INTENSET__Type.html">ADC_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structAdc.html#a07ae3a5472859656c92b6aaeda6849de">INTENSET</a></td></tr>
<tr class="memdesc:a07ae3a5472859656c92b6aaeda6849de"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x2D (R/W 8) Interrupt Enable Set. <br /></td></tr>
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__IO <a class="el" href="unionADC__INTFLAG__Type.html">ADC_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structAdc.html#a1b221db015a728adf157f6d130967476">INTFLAG</a></td></tr>
<tr class="memdesc:a1b221db015a728adf157f6d130967476"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear. <br /></td></tr>
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<tr class="memdesc:ac60094eae1e60edc4aa579c498c33018"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x2F (R/ 8) Status. <br /></td></tr>
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__I <a class="el" href="unionADC__SYNCBUSY__Type.html">ADC_SYNCBUSY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structAdc.html#ad098ce6ae8d280745ac9d61d46e8a71b">SYNCBUSY</a></td></tr>
<tr class="memdesc:ad098ce6ae8d280745ac9d61d46e8a71b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 (R/ 32) Synchronization Busy. <br /></td></tr>
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<tr class="memdesc:a68d33f8d08888fa6f2a403e0e99386f8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x34 ( /W 32) DMA Sequencial Data. <br /></td></tr>
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<tr class="memdesc:aaedb7034710294b81241e0493184a587"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x38 (R/W 32) DMA Sequential Control. <br /></td></tr>
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__I <a class="el" href="unionADC__DSEQSTAT__Type.html">ADC_DSEQSTAT_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structAdc.html#aa7607ca01006c2c3774f455da1f53459">DSEQSTAT</a></td></tr>
<tr class="memdesc:aa7607ca01006c2c3774f455da1f53459"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x3C (R/ 32) DMA Sequencial Status. <br /></td></tr>
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<tr class="memdesc:a04ab9cba3b770ef91a881a4b199b5da0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x40 (R/ 16) Result Conversion Value. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x2]</td></tr>
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__I <a class="el" href="unionADC__RESS__Type.html">ADC_RESS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structAdc.html#a6cd66420808d57fe1a3cdb70751793ee">RESS</a></td></tr>
<tr class="memdesc:a6cd66420808d57fe1a3cdb70751793ee"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x44 (R/ 16) Last Sample Result. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved4</b> [0x2]</td></tr>
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__IO <a class="el" href="unionADC__CALIB__Type.html">ADC_CALIB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structAdc.html#a1b5d65ffe6930f10d52dce97958a8fd8">CALIB</a></td></tr>
<tr class="memdesc:a1b5d65ffe6930f10d52dce97958a8fd8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x48 (R/W 16) Calibration. <br /></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>ADC hardware registers. </p>
<p class="definition">Definition at line <a class="el" href="adc_8h_source.html#l00837">837</a> of file <a class="el" href="adc_8h_source.html">adc.h</a>.</p>
</div><hr/>The documentation for this struct was generated from the following file:<ul>
<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="adc_8h_source.html">adc.h</a></li>
</ul>
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