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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/ramecc.h File Reference</title>
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">ramecc.h File Reference</div> </div>
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<p>Instance description for RAMECC.
<a href="#details">More...</a></p>
<p><a href="instance_2ramecc_8h_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a14ad30dff0b0d11e2ba2c09bcac54dbc"><td class="memItemLeft" align="right" valign="top"><a id="a14ad30dff0b0d11e2ba2c09bcac54dbc"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2ramecc_8h.html#a14ad30dff0b0d11e2ba2c09bcac54dbc">REG_RAMECC_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41020000UL)</td></tr>
<tr class="memdesc:a14ad30dff0b0d11e2ba2c09bcac54dbc"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC) Interrupt Enable Clear <br /></td></tr>
<tr class="separator:a14ad30dff0b0d11e2ba2c09bcac54dbc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac44d6c01140fc6c8f540fa5152a0e157"><td class="memItemLeft" align="right" valign="top"><a id="ac44d6c01140fc6c8f540fa5152a0e157"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2ramecc_8h.html#ac44d6c01140fc6c8f540fa5152a0e157">REG_RAMECC_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41020001UL)</td></tr>
<tr class="memdesc:ac44d6c01140fc6c8f540fa5152a0e157"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC) Interrupt Enable Set <br /></td></tr>
<tr class="separator:ac44d6c01140fc6c8f540fa5152a0e157"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a31bc4eebc0d8dcc47f3c05c4700d7133"><td class="memItemLeft" align="right" valign="top"><a id="a31bc4eebc0d8dcc47f3c05c4700d7133"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2ramecc_8h.html#a31bc4eebc0d8dcc47f3c05c4700d7133">REG_RAMECC_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41020002UL)</td></tr>
<tr class="memdesc:a31bc4eebc0d8dcc47f3c05c4700d7133"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC) Interrupt Flag <br /></td></tr>
<tr class="separator:a31bc4eebc0d8dcc47f3c05c4700d7133"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ace70a3dbb0b13c7888a688f60c7c3c57"><td class="memItemLeft" align="right" valign="top"><a id="ace70a3dbb0b13c7888a688f60c7c3c57"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2ramecc_8h.html#ace70a3dbb0b13c7888a688f60c7c3c57">REG_RAMECC_STATUS</a>   (*(<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> *)0x41020003UL)</td></tr>
<tr class="memdesc:ace70a3dbb0b13c7888a688f60c7c3c57"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC) Status <br /></td></tr>
<tr class="separator:ace70a3dbb0b13c7888a688f60c7c3c57"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a55cf6cb307d6b95b6bdc4c16e6b71a50"><td class="memItemLeft" align="right" valign="top"><a id="a55cf6cb307d6b95b6bdc4c16e6b71a50"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2ramecc_8h.html#a55cf6cb307d6b95b6bdc4c16e6b71a50">REG_RAMECC_ERRADDR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41020004UL)</td></tr>
<tr class="memdesc:a55cf6cb307d6b95b6bdc4c16e6b71a50"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC) Error Address <br /></td></tr>
<tr class="separator:a55cf6cb307d6b95b6bdc4c16e6b71a50"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a558bb91d9f2784c72d40ff2abecfb7fb"><td class="memItemLeft" align="right" valign="top"><a id="a558bb91d9f2784c72d40ff2abecfb7fb"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2ramecc_8h.html#a558bb91d9f2784c72d40ff2abecfb7fb">REG_RAMECC_DBGCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4102000FUL)</td></tr>
<tr class="memdesc:a558bb91d9f2784c72d40ff2abecfb7fb"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC) Debug Control <br /></td></tr>
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<tr class="memitem:a614c503453ede61182e1ee5295612d4d"><td class="memItemLeft" align="right" valign="top"><a id="a614c503453ede61182e1ee5295612d4d"></a>
#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_RAMADDR_BITS</b>   13</td></tr>
<tr class="separator:a614c503453ede61182e1ee5295612d4d"><td class="memSeparator" colspan="2"> </td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_RAMBANK_NUM</b>   4</td></tr>
<tr class="separator:a12f65a90319a3b7ea1f366ab52b973da"><td class="memSeparator" colspan="2"> </td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Instance description for RAMECC. </p>
<p>Copyright (c) 2019 Microchip Technology Inc.</p>
<p>\asf_license_start </p>
<p class="definition">Definition in file <a class="el" href="instance_2ramecc_8h_source.html">ramecc.h</a>.</p>
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