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SAME54P20A Test Project
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Component description for CAN. More...
Go to the source code of this file.
Macros | |
| #define | CAN_U2003 |
| #define | REV_CAN 0x321 |
| #define | CAN_CREL_OFFSET 0x00 |
| (CAN_CREL offset) Core Release | |
| #define | CAN_CREL_RESETVALUE _U_(0x32100000) |
| (CAN_CREL reset_value) Core Release | |
| #define | CAN_CREL_SUBSTEP_Pos 20 |
| (CAN_CREL) Sub-step of Core Release | |
| #define | CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos) |
| #define | CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos)) |
| #define | CAN_CREL_STEP_Pos 24 |
| (CAN_CREL) Step of Core Release | |
| #define | CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos) |
| #define | CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos)) |
| #define | CAN_CREL_REL_Pos 28 |
| (CAN_CREL) Core Release | |
| #define | CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos) |
| #define | CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos)) |
| #define | CAN_CREL_MASK _U_(0xFFF00000) |
| (CAN_CREL) MASK Register | |
| #define | CAN_ENDN_OFFSET 0x04 |
| (CAN_ENDN offset) Endian | |
| #define | CAN_ENDN_RESETVALUE _U_(0x87654321) |
| (CAN_ENDN reset_value) Endian | |
| #define | CAN_ENDN_ETV_Pos 0 |
| (CAN_ENDN) Endianness Test Value | |
| #define | CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) |
| #define | CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos)) |
| #define | CAN_ENDN_MASK _U_(0xFFFFFFFF) |
| (CAN_ENDN) MASK Register | |
| #define | CAN_MRCFG_OFFSET 0x08 |
| (CAN_MRCFG offset) Message RAM Configuration | |
| #define | CAN_MRCFG_RESETVALUE _U_(0x00000002) |
| (CAN_MRCFG reset_value) Message RAM Configuration | |
| #define | CAN_MRCFG_QOS_Pos 0 |
| (CAN_MRCFG) Quality of Service | |
| #define | CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos) |
| #define | CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos)) |
| #define | CAN_MRCFG_QOS_DISABLE_Val _U_(0x0) |
| (CAN_MRCFG) Background (no sensitive operation) | |
| #define | CAN_MRCFG_QOS_LOW_Val _U_(0x1) |
| (CAN_MRCFG) Sensitive Bandwidth | |
| #define | CAN_MRCFG_QOS_MEDIUM_Val _U_(0x2) |
| (CAN_MRCFG) Sensitive Latency | |
| #define | CAN_MRCFG_QOS_HIGH_Val _U_(0x3) |
| (CAN_MRCFG) Critical Latency | |
| #define | CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) |
| #define | CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) |
| #define | CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) |
| #define | CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) |
| #define | CAN_MRCFG_MASK _U_(0x00000003) |
| (CAN_MRCFG) MASK Register | |
| #define | CAN_DBTP_OFFSET 0x0C |
| (CAN_DBTP offset) Fast Bit Timing and Prescaler | |
| #define | CAN_DBTP_RESETVALUE _U_(0x00000A33) |
| (CAN_DBTP reset_value) Fast Bit Timing and Prescaler | |
| #define | CAN_DBTP_DSJW_Pos 0 |
| (CAN_DBTP) Data (Re)Synchronization Jump Width | |
| #define | CAN_DBTP_DSJW_Msk (_U_(0xF) << CAN_DBTP_DSJW_Pos) |
| #define | CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos)) |
| #define | CAN_DBTP_DTSEG2_Pos 4 |
| (CAN_DBTP) Data time segment after sample point | |
| #define | CAN_DBTP_DTSEG2_Msk (_U_(0xF) << CAN_DBTP_DTSEG2_Pos) |
| #define | CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos)) |
| #define | CAN_DBTP_DTSEG1_Pos 8 |
| (CAN_DBTP) Data time segment before sample point | |
| #define | CAN_DBTP_DTSEG1_Msk (_U_(0x1F) << CAN_DBTP_DTSEG1_Pos) |
| #define | CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos)) |
| #define | CAN_DBTP_DBRP_Pos 16 |
| (CAN_DBTP) Data Baud Rate Prescaler | |
| #define | CAN_DBTP_DBRP_Msk (_U_(0x1F) << CAN_DBTP_DBRP_Pos) |
| #define | CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos)) |
| #define | CAN_DBTP_TDC_Pos 23 |
| (CAN_DBTP) Tranceiver Delay Compensation | |
| #define | CAN_DBTP_TDC (_U_(0x1) << CAN_DBTP_TDC_Pos) |
| #define | CAN_DBTP_MASK _U_(0x009F1FFF) |
| (CAN_DBTP) MASK Register | |
| #define | CAN_TEST_OFFSET 0x10 |
| (CAN_TEST offset) Test | |
| #define | CAN_TEST_RESETVALUE _U_(0x00000000) |
| (CAN_TEST reset_value) Test | |
| #define | CAN_TEST_LBCK_Pos 4 |
| (CAN_TEST) Loop Back Mode | |
| #define | CAN_TEST_LBCK (_U_(0x1) << CAN_TEST_LBCK_Pos) |
| #define | CAN_TEST_TX_Pos 5 |
| (CAN_TEST) Control of Transmit Pin | |
| #define | CAN_TEST_TX_Msk (_U_(0x3) << CAN_TEST_TX_Pos) |
| #define | CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos)) |
| #define | CAN_TEST_TX_CORE_Val _U_(0x0) |
| (CAN_TEST) TX controlled by CAN core | |
| #define | CAN_TEST_TX_SAMPLE_Val _U_(0x1) |
| (CAN_TEST) TX monitoring sample point | |
| #define | CAN_TEST_TX_DOMINANT_Val _U_(0x2) |
| (CAN_TEST) Dominant (0) level at pin CAN_TX | |
| #define | CAN_TEST_TX_RECESSIVE_Val _U_(0x3) |
| (CAN_TEST) Recessive (1) level at pin CAN_TX | |
| #define | CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) |
| #define | CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) |
| #define | CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) |
| #define | CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) |
| #define | CAN_TEST_RX_Pos 7 |
| (CAN_TEST) Receive Pin | |
| #define | CAN_TEST_RX (_U_(0x1) << CAN_TEST_RX_Pos) |
| #define | CAN_TEST_MASK _U_(0x000000F0) |
| (CAN_TEST) MASK Register | |
| #define | CAN_RWD_OFFSET 0x14 |
| (CAN_RWD offset) RAM Watchdog | |
| #define | CAN_RWD_RESETVALUE _U_(0x00000000) |
| (CAN_RWD reset_value) RAM Watchdog | |
| #define | CAN_RWD_WDC_Pos 0 |
| (CAN_RWD) Watchdog Configuration | |
| #define | CAN_RWD_WDC_Msk (_U_(0xFF) << CAN_RWD_WDC_Pos) |
| #define | CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos)) |
| #define | CAN_RWD_WDV_Pos 8 |
| (CAN_RWD) Watchdog Value | |
| #define | CAN_RWD_WDV_Msk (_U_(0xFF) << CAN_RWD_WDV_Pos) |
| #define | CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos)) |
| #define | CAN_RWD_MASK _U_(0x0000FFFF) |
| (CAN_RWD) MASK Register | |
| #define | CAN_CCCR_OFFSET 0x18 |
| (CAN_CCCR offset) CC Control | |
| #define | CAN_CCCR_RESETVALUE _U_(0x00000001) |
| (CAN_CCCR reset_value) CC Control | |
| #define | CAN_CCCR_INIT_Pos 0 |
| (CAN_CCCR) Initialization | |
| #define | CAN_CCCR_INIT (_U_(0x1) << CAN_CCCR_INIT_Pos) |
| #define | CAN_CCCR_CCE_Pos 1 |
| (CAN_CCCR) Configuration Change Enable | |
| #define | CAN_CCCR_CCE (_U_(0x1) << CAN_CCCR_CCE_Pos) |
| #define | CAN_CCCR_ASM_Pos 2 |
| (CAN_CCCR) ASM Restricted Operation Mode | |
| #define | CAN_CCCR_ASM (_U_(0x1) << CAN_CCCR_ASM_Pos) |
| #define | CAN_CCCR_CSA_Pos 3 |
| (CAN_CCCR) Clock Stop Acknowledge | |
| #define | CAN_CCCR_CSA (_U_(0x1) << CAN_CCCR_CSA_Pos) |
| #define | CAN_CCCR_CSR_Pos 4 |
| (CAN_CCCR) Clock Stop Request | |
| #define | CAN_CCCR_CSR (_U_(0x1) << CAN_CCCR_CSR_Pos) |
| #define | CAN_CCCR_MON_Pos 5 |
| (CAN_CCCR) Bus Monitoring Mode | |
| #define | CAN_CCCR_MON (_U_(0x1) << CAN_CCCR_MON_Pos) |
| #define | CAN_CCCR_DAR_Pos 6 |
| (CAN_CCCR) Disable Automatic Retransmission | |
| #define | CAN_CCCR_DAR (_U_(0x1) << CAN_CCCR_DAR_Pos) |
| #define | CAN_CCCR_TEST_Pos 7 |
| (CAN_CCCR) Test Mode Enable | |
| #define | CAN_CCCR_TEST (_U_(0x1) << CAN_CCCR_TEST_Pos) |
| #define | CAN_CCCR_FDOE_Pos 8 |
| (CAN_CCCR) FD Operation Enable | |
| #define | CAN_CCCR_FDOE (_U_(0x1) << CAN_CCCR_FDOE_Pos) |
| #define | CAN_CCCR_BRSE_Pos 9 |
| (CAN_CCCR) Bit Rate Switch Enable | |
| #define | CAN_CCCR_BRSE (_U_(0x1) << CAN_CCCR_BRSE_Pos) |
| #define | CAN_CCCR_PXHD_Pos 12 |
| (CAN_CCCR) Protocol Exception Handling Disable | |
| #define | CAN_CCCR_PXHD (_U_(0x1) << CAN_CCCR_PXHD_Pos) |
| #define | CAN_CCCR_EFBI_Pos 13 |
| (CAN_CCCR) Edge Filtering during Bus Integration | |
| #define | CAN_CCCR_EFBI (_U_(0x1) << CAN_CCCR_EFBI_Pos) |
| #define | CAN_CCCR_TXP_Pos 14 |
| (CAN_CCCR) Transmit Pause | |
| #define | CAN_CCCR_TXP (_U_(0x1) << CAN_CCCR_TXP_Pos) |
| #define | CAN_CCCR_NISO_Pos 15 |
| (CAN_CCCR) Non ISO Operation | |
| #define | CAN_CCCR_NISO (_U_(0x1) << CAN_CCCR_NISO_Pos) |
| #define | CAN_CCCR_MASK _U_(0x0000F3FF) |
| (CAN_CCCR) MASK Register | |
| #define | CAN_NBTP_OFFSET 0x1C |
| (CAN_NBTP offset) Nominal Bit Timing and Prescaler | |
| #define | CAN_NBTP_RESETVALUE _U_(0x06000A03) |
| (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler | |
| #define | CAN_NBTP_NTSEG2_Pos 0 |
| (CAN_NBTP) Nominal Time segment after sample point | |
| #define | CAN_NBTP_NTSEG2_Msk (_U_(0x7F) << CAN_NBTP_NTSEG2_Pos) |
| #define | CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos)) |
| #define | CAN_NBTP_NTSEG1_Pos 8 |
| (CAN_NBTP) Nominal Time segment before sample point | |
| #define | CAN_NBTP_NTSEG1_Msk (_U_(0xFF) << CAN_NBTP_NTSEG1_Pos) |
| #define | CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos)) |
| #define | CAN_NBTP_NBRP_Pos 16 |
| (CAN_NBTP) Nominal Baud Rate Prescaler | |
| #define | CAN_NBTP_NBRP_Msk (_U_(0x1FF) << CAN_NBTP_NBRP_Pos) |
| #define | CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos)) |
| #define | CAN_NBTP_NSJW_Pos 25 |
| (CAN_NBTP) Nominal (Re)Synchronization Jump Width | |
| #define | CAN_NBTP_NSJW_Msk (_U_(0x7F) << CAN_NBTP_NSJW_Pos) |
| #define | CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos)) |
| #define | CAN_NBTP_MASK _U_(0xFFFFFF7F) |
| (CAN_NBTP) MASK Register | |
| #define | CAN_TSCC_OFFSET 0x20 |
| (CAN_TSCC offset) Timestamp Counter Configuration | |
| #define | CAN_TSCC_RESETVALUE _U_(0x00000000) |
| (CAN_TSCC reset_value) Timestamp Counter Configuration | |
| #define | CAN_TSCC_TSS_Pos 0 |
| (CAN_TSCC) Timestamp Select | |
| #define | CAN_TSCC_TSS_Msk (_U_(0x3) << CAN_TSCC_TSS_Pos) |
| #define | CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos)) |
| #define | CAN_TSCC_TSS_ZERO_Val _U_(0x0) |
| (CAN_TSCC) Timestamp counter value always 0x0000 | |
| #define | CAN_TSCC_TSS_INC_Val _U_(0x1) |
| (CAN_TSCC) Timestamp counter value incremented by TCP | |
| #define | CAN_TSCC_TSS_EXT_Val _U_(0x2) |
| (CAN_TSCC) External timestamp counter value used | |
| #define | CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) |
| #define | CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) |
| #define | CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) |
| #define | CAN_TSCC_TCP_Pos 16 |
| (CAN_TSCC) Timestamp Counter Prescaler | |
| #define | CAN_TSCC_TCP_Msk (_U_(0xF) << CAN_TSCC_TCP_Pos) |
| #define | CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos)) |
| #define | CAN_TSCC_MASK _U_(0x000F0003) |
| (CAN_TSCC) MASK Register | |
| #define | CAN_TSCV_OFFSET 0x24 |
| (CAN_TSCV offset) Timestamp Counter Value | |
| #define | CAN_TSCV_RESETVALUE _U_(0x00000000) |
| (CAN_TSCV reset_value) Timestamp Counter Value | |
| #define | CAN_TSCV_TSC_Pos 0 |
| (CAN_TSCV) Timestamp Counter | |
| #define | CAN_TSCV_TSC_Msk (_U_(0xFFFF) << CAN_TSCV_TSC_Pos) |
| #define | CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos)) |
| #define | CAN_TSCV_MASK _U_(0x0000FFFF) |
| (CAN_TSCV) MASK Register | |
| #define | CAN_TOCC_OFFSET 0x28 |
| (CAN_TOCC offset) Timeout Counter Configuration | |
| #define | CAN_TOCC_RESETVALUE _U_(0xFFFF0000) |
| (CAN_TOCC reset_value) Timeout Counter Configuration | |
| #define | CAN_TOCC_ETOC_Pos 0 |
| (CAN_TOCC) Enable Timeout Counter | |
| #define | CAN_TOCC_ETOC (_U_(0x1) << CAN_TOCC_ETOC_Pos) |
| #define | CAN_TOCC_TOS_Pos 1 |
| (CAN_TOCC) Timeout Select | |
| #define | CAN_TOCC_TOS_Msk (_U_(0x3) << CAN_TOCC_TOS_Pos) |
| #define | CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos)) |
| #define | CAN_TOCC_TOS_CONT_Val _U_(0x0) |
| (CAN_TOCC) Continuout operation | |
| #define | CAN_TOCC_TOS_TXEF_Val _U_(0x1) |
| (CAN_TOCC) Timeout controlled by TX Event FIFO | |
| #define | CAN_TOCC_TOS_RXF0_Val _U_(0x2) |
| (CAN_TOCC) Timeout controlled by Rx FIFO 0 | |
| #define | CAN_TOCC_TOS_RXF1_Val _U_(0x3) |
| (CAN_TOCC) Timeout controlled by Rx FIFO 1 | |
| #define | CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) |
| #define | CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) |
| #define | CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) |
| #define | CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) |
| #define | CAN_TOCC_TOP_Pos 16 |
| (CAN_TOCC) Timeout Period | |
| #define | CAN_TOCC_TOP_Msk (_U_(0xFFFF) << CAN_TOCC_TOP_Pos) |
| #define | CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos)) |
| #define | CAN_TOCC_MASK _U_(0xFFFF0007) |
| (CAN_TOCC) MASK Register | |
| #define | CAN_TOCV_OFFSET 0x2C |
| (CAN_TOCV offset) Timeout Counter Value | |
| #define | CAN_TOCV_RESETVALUE _U_(0x0000FFFF) |
| (CAN_TOCV reset_value) Timeout Counter Value | |
| #define | CAN_TOCV_TOC_Pos 0 |
| (CAN_TOCV) Timeout Counter | |
| #define | CAN_TOCV_TOC_Msk (_U_(0xFFFF) << CAN_TOCV_TOC_Pos) |
| #define | CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos)) |
| #define | CAN_TOCV_MASK _U_(0x0000FFFF) |
| (CAN_TOCV) MASK Register | |
| #define | CAN_ECR_OFFSET 0x40 |
| (CAN_ECR offset) Error Counter | |
| #define | CAN_ECR_RESETVALUE _U_(0x00000000) |
| (CAN_ECR reset_value) Error Counter | |
| #define | CAN_ECR_TEC_Pos 0 |
| (CAN_ECR) Transmit Error Counter | |
| #define | CAN_ECR_TEC_Msk (_U_(0xFF) << CAN_ECR_TEC_Pos) |
| #define | CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos)) |
| #define | CAN_ECR_REC_Pos 8 |
| (CAN_ECR) Receive Error Counter | |
| #define | CAN_ECR_REC_Msk (_U_(0x7F) << CAN_ECR_REC_Pos) |
| #define | CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos)) |
| #define | CAN_ECR_RP_Pos 15 |
| (CAN_ECR) Receive Error Passive | |
| #define | CAN_ECR_RP (_U_(0x1) << CAN_ECR_RP_Pos) |
| #define | CAN_ECR_CEL_Pos 16 |
| (CAN_ECR) CAN Error Logging | |
| #define | CAN_ECR_CEL_Msk (_U_(0xFF) << CAN_ECR_CEL_Pos) |
| #define | CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos)) |
| #define | CAN_ECR_MASK _U_(0x00FFFFFF) |
| (CAN_ECR) MASK Register | |
| #define | CAN_PSR_OFFSET 0x44 |
| (CAN_PSR offset) Protocol Status | |
| #define | CAN_PSR_RESETVALUE _U_(0x00000707) |
| (CAN_PSR reset_value) Protocol Status | |
| #define | CAN_PSR_LEC_Pos 0 |
| (CAN_PSR) Last Error Code | |
| #define | CAN_PSR_LEC_Msk (_U_(0x7) << CAN_PSR_LEC_Pos) |
| #define | CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos)) |
| #define | CAN_PSR_LEC_NONE_Val _U_(0x0) |
| (CAN_PSR) No Error | |
| #define | CAN_PSR_LEC_STUFF_Val _U_(0x1) |
| (CAN_PSR) Stuff Error | |
| #define | CAN_PSR_LEC_FORM_Val _U_(0x2) |
| (CAN_PSR) Form Error | |
| #define | CAN_PSR_LEC_ACK_Val _U_(0x3) |
| (CAN_PSR) Ack Error | |
| #define | CAN_PSR_LEC_BIT1_Val _U_(0x4) |
| (CAN_PSR) Bit1 Error | |
| #define | CAN_PSR_LEC_BIT0_Val _U_(0x5) |
| (CAN_PSR) Bit0 Error | |
| #define | CAN_PSR_LEC_CRC_Val _U_(0x6) |
| (CAN_PSR) CRC Error | |
| #define | CAN_PSR_LEC_NC_Val _U_(0x7) |
| (CAN_PSR) No Change | |
| #define | CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) |
| #define | CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) |
| #define | CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) |
| #define | CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) |
| #define | CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) |
| #define | CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) |
| #define | CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) |
| #define | CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) |
| #define | CAN_PSR_ACT_Pos 3 |
| (CAN_PSR) Activity | |
| #define | CAN_PSR_ACT_Msk (_U_(0x3) << CAN_PSR_ACT_Pos) |
| #define | CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos)) |
| #define | CAN_PSR_ACT_SYNC_Val _U_(0x0) |
| (CAN_PSR) Node is synchronizing on CAN communication | |
| #define | CAN_PSR_ACT_IDLE_Val _U_(0x1) |
| (CAN_PSR) Node is neither receiver nor transmitter | |
| #define | CAN_PSR_ACT_RX_Val _U_(0x2) |
| (CAN_PSR) Node is operating as receiver | |
| #define | CAN_PSR_ACT_TX_Val _U_(0x3) |
| (CAN_PSR) Node is operating as transmitter | |
| #define | CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) |
| #define | CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) |
| #define | CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) |
| #define | CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) |
| #define | CAN_PSR_EP_Pos 5 |
| (CAN_PSR) Error Passive | |
| #define | CAN_PSR_EP (_U_(0x1) << CAN_PSR_EP_Pos) |
| #define | CAN_PSR_EW_Pos 6 |
| (CAN_PSR) Warning Status | |
| #define | CAN_PSR_EW (_U_(0x1) << CAN_PSR_EW_Pos) |
| #define | CAN_PSR_BO_Pos 7 |
| (CAN_PSR) Bus_Off Status | |
| #define | CAN_PSR_BO (_U_(0x1) << CAN_PSR_BO_Pos) |
| #define | CAN_PSR_DLEC_Pos 8 |
| (CAN_PSR) Data Phase Last Error Code | |
| #define | CAN_PSR_DLEC_Msk (_U_(0x7) << CAN_PSR_DLEC_Pos) |
| #define | CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos)) |
| #define | CAN_PSR_DLEC_NONE_Val _U_(0x0) |
| (CAN_PSR) No Error | |
| #define | CAN_PSR_DLEC_STUFF_Val _U_(0x1) |
| (CAN_PSR) Stuff Error | |
| #define | CAN_PSR_DLEC_FORM_Val _U_(0x2) |
| (CAN_PSR) Form Error | |
| #define | CAN_PSR_DLEC_ACK_Val _U_(0x3) |
| (CAN_PSR) Ack Error | |
| #define | CAN_PSR_DLEC_BIT1_Val _U_(0x4) |
| (CAN_PSR) Bit1 Error | |
| #define | CAN_PSR_DLEC_BIT0_Val _U_(0x5) |
| (CAN_PSR) Bit0 Error | |
| #define | CAN_PSR_DLEC_CRC_Val _U_(0x6) |
| (CAN_PSR) CRC Error | |
| #define | CAN_PSR_DLEC_NC_Val _U_(0x7) |
| (CAN_PSR) No Change | |
| #define | CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) |
| #define | CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) |
| #define | CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) |
| #define | CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) |
| #define | CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) |
| #define | CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) |
| #define | CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) |
| #define | CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) |
| #define | CAN_PSR_RESI_Pos 11 |
| (CAN_PSR) ESI flag of last received CAN FD Message | |
| #define | CAN_PSR_RESI (_U_(0x1) << CAN_PSR_RESI_Pos) |
| #define | CAN_PSR_RBRS_Pos 12 |
| (CAN_PSR) BRS flag of last received CAN FD Message | |
| #define | CAN_PSR_RBRS (_U_(0x1) << CAN_PSR_RBRS_Pos) |
| #define | CAN_PSR_RFDF_Pos 13 |
| (CAN_PSR) Received a CAN FD Message | |
| #define | CAN_PSR_RFDF (_U_(0x1) << CAN_PSR_RFDF_Pos) |
| #define | CAN_PSR_PXE_Pos 14 |
| (CAN_PSR) Protocol Exception Event | |
| #define | CAN_PSR_PXE (_U_(0x1) << CAN_PSR_PXE_Pos) |
| #define | CAN_PSR_TDCV_Pos 16 |
| (CAN_PSR) Transmitter Delay Compensation Value | |
| #define | CAN_PSR_TDCV_Msk (_U_(0x7F) << CAN_PSR_TDCV_Pos) |
| #define | CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos)) |
| #define | CAN_PSR_MASK _U_(0x007F7FFF) |
| (CAN_PSR) MASK Register | |
| #define | CAN_TDCR_OFFSET 0x48 |
| (CAN_TDCR offset) Extended ID Filter Configuration | |
| #define | CAN_TDCR_RESETVALUE _U_(0x00000000) |
| (CAN_TDCR reset_value) Extended ID Filter Configuration | |
| #define | CAN_TDCR_TDCF_Pos 0 |
| (CAN_TDCR) Transmitter Delay Compensation Filter Length | |
| #define | CAN_TDCR_TDCF_Msk (_U_(0x7F) << CAN_TDCR_TDCF_Pos) |
| #define | CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos)) |
| #define | CAN_TDCR_TDCO_Pos 8 |
| (CAN_TDCR) Transmitter Delay Compensation Offset | |
| #define | CAN_TDCR_TDCO_Msk (_U_(0x7F) << CAN_TDCR_TDCO_Pos) |
| #define | CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos)) |
| #define | CAN_TDCR_MASK _U_(0x00007F7F) |
| (CAN_TDCR) MASK Register | |
| #define | CAN_IR_OFFSET 0x50 |
| (CAN_IR offset) Interrupt | |
| #define | CAN_IR_RESETVALUE _U_(0x00000000) |
| (CAN_IR reset_value) Interrupt | |
| #define | CAN_IR_RF0N_Pos 0 |
| (CAN_IR) Rx FIFO 0 New Message | |
| #define | CAN_IR_RF0N (_U_(0x1) << CAN_IR_RF0N_Pos) |
| #define | CAN_IR_RF0W_Pos 1 |
| (CAN_IR) Rx FIFO 0 Watermark Reached | |
| #define | CAN_IR_RF0W (_U_(0x1) << CAN_IR_RF0W_Pos) |
| #define | CAN_IR_RF0F_Pos 2 |
| (CAN_IR) Rx FIFO 0 Full | |
| #define | CAN_IR_RF0F (_U_(0x1) << CAN_IR_RF0F_Pos) |
| #define | CAN_IR_RF0L_Pos 3 |
| (CAN_IR) Rx FIFO 0 Message Lost | |
| #define | CAN_IR_RF0L (_U_(0x1) << CAN_IR_RF0L_Pos) |
| #define | CAN_IR_RF1N_Pos 4 |
| (CAN_IR) Rx FIFO 1 New Message | |
| #define | CAN_IR_RF1N (_U_(0x1) << CAN_IR_RF1N_Pos) |
| #define | CAN_IR_RF1W_Pos 5 |
| (CAN_IR) Rx FIFO 1 Watermark Reached | |
| #define | CAN_IR_RF1W (_U_(0x1) << CAN_IR_RF1W_Pos) |
| #define | CAN_IR_RF1F_Pos 6 |
| (CAN_IR) Rx FIFO 1 FIFO Full | |
| #define | CAN_IR_RF1F (_U_(0x1) << CAN_IR_RF1F_Pos) |
| #define | CAN_IR_RF1L_Pos 7 |
| (CAN_IR) Rx FIFO 1 Message Lost | |
| #define | CAN_IR_RF1L (_U_(0x1) << CAN_IR_RF1L_Pos) |
| #define | CAN_IR_HPM_Pos 8 |
| (CAN_IR) High Priority Message | |
| #define | CAN_IR_HPM (_U_(0x1) << CAN_IR_HPM_Pos) |
| #define | CAN_IR_TC_Pos 9 |
| (CAN_IR) Timestamp Completed | |
| #define | CAN_IR_TC (_U_(0x1) << CAN_IR_TC_Pos) |
| #define | CAN_IR_TCF_Pos 10 |
| (CAN_IR) Transmission Cancellation Finished | |
| #define | CAN_IR_TCF (_U_(0x1) << CAN_IR_TCF_Pos) |
| #define | CAN_IR_TFE_Pos 11 |
| (CAN_IR) Tx FIFO Empty | |
| #define | CAN_IR_TFE (_U_(0x1) << CAN_IR_TFE_Pos) |
| #define | CAN_IR_TEFN_Pos 12 |
| (CAN_IR) Tx Event FIFO New Entry | |
| #define | CAN_IR_TEFN (_U_(0x1) << CAN_IR_TEFN_Pos) |
| #define | CAN_IR_TEFW_Pos 13 |
| (CAN_IR) Tx Event FIFO Watermark Reached | |
| #define | CAN_IR_TEFW (_U_(0x1) << CAN_IR_TEFW_Pos) |
| #define | CAN_IR_TEFF_Pos 14 |
| (CAN_IR) Tx Event FIFO Full | |
| #define | CAN_IR_TEFF (_U_(0x1) << CAN_IR_TEFF_Pos) |
| #define | CAN_IR_TEFL_Pos 15 |
| (CAN_IR) Tx Event FIFO Element Lost | |
| #define | CAN_IR_TEFL (_U_(0x1) << CAN_IR_TEFL_Pos) |
| #define | CAN_IR_TSW_Pos 16 |
| (CAN_IR) Timestamp Wraparound | |
| #define | CAN_IR_TSW (_U_(0x1) << CAN_IR_TSW_Pos) |
| #define | CAN_IR_MRAF_Pos 17 |
| (CAN_IR) Message RAM Access Failure | |
| #define | CAN_IR_MRAF (_U_(0x1) << CAN_IR_MRAF_Pos) |
| #define | CAN_IR_TOO_Pos 18 |
| (CAN_IR) Timeout Occurred | |
| #define | CAN_IR_TOO (_U_(0x1) << CAN_IR_TOO_Pos) |
| #define | CAN_IR_DRX_Pos 19 |
| (CAN_IR) Message stored to Dedicated Rx Buffer | |
| #define | CAN_IR_DRX (_U_(0x1) << CAN_IR_DRX_Pos) |
| #define | CAN_IR_BEC_Pos 20 |
| (CAN_IR) Bit Error Corrected | |
| #define | CAN_IR_BEC (_U_(0x1) << CAN_IR_BEC_Pos) |
| #define | CAN_IR_BEU_Pos 21 |
| (CAN_IR) Bit Error Uncorrected | |
| #define | CAN_IR_BEU (_U_(0x1) << CAN_IR_BEU_Pos) |
| #define | CAN_IR_ELO_Pos 22 |
| (CAN_IR) Error Logging Overflow | |
| #define | CAN_IR_ELO (_U_(0x1) << CAN_IR_ELO_Pos) |
| #define | CAN_IR_EP_Pos 23 |
| (CAN_IR) Error Passive | |
| #define | CAN_IR_EP (_U_(0x1) << CAN_IR_EP_Pos) |
| #define | CAN_IR_EW_Pos 24 |
| (CAN_IR) Warning Status | |
| #define | CAN_IR_EW (_U_(0x1) << CAN_IR_EW_Pos) |
| #define | CAN_IR_BO_Pos 25 |
| (CAN_IR) Bus_Off Status | |
| #define | CAN_IR_BO (_U_(0x1) << CAN_IR_BO_Pos) |
| #define | CAN_IR_WDI_Pos 26 |
| (CAN_IR) Watchdog Interrupt | |
| #define | CAN_IR_WDI (_U_(0x1) << CAN_IR_WDI_Pos) |
| #define | CAN_IR_PEA_Pos 27 |
| (CAN_IR) Protocol Error in Arbitration Phase | |
| #define | CAN_IR_PEA (_U_(0x1) << CAN_IR_PEA_Pos) |
| #define | CAN_IR_PED_Pos 28 |
| (CAN_IR) Protocol Error in Data Phase | |
| #define | CAN_IR_PED (_U_(0x1) << CAN_IR_PED_Pos) |
| #define | CAN_IR_ARA_Pos 29 |
| (CAN_IR) Access to Reserved Address | |
| #define | CAN_IR_ARA (_U_(0x1) << CAN_IR_ARA_Pos) |
| #define | CAN_IR_MASK _U_(0x3FFFFFFF) |
| (CAN_IR) MASK Register | |
| #define | CAN_IE_OFFSET 0x54 |
| (CAN_IE offset) Interrupt Enable | |
| #define | CAN_IE_RESETVALUE _U_(0x00000000) |
| (CAN_IE reset_value) Interrupt Enable | |
| #define | CAN_IE_RF0NE_Pos 0 |
| (CAN_IE) Rx FIFO 0 New Message Interrupt Enable | |
| #define | CAN_IE_RF0NE (_U_(0x1) << CAN_IE_RF0NE_Pos) |
| #define | CAN_IE_RF0WE_Pos 1 |
| (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable | |
| #define | CAN_IE_RF0WE (_U_(0x1) << CAN_IE_RF0WE_Pos) |
| #define | CAN_IE_RF0FE_Pos 2 |
| (CAN_IE) Rx FIFO 0 Full Interrupt Enable | |
| #define | CAN_IE_RF0FE (_U_(0x1) << CAN_IE_RF0FE_Pos) |
| #define | CAN_IE_RF0LE_Pos 3 |
| (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable | |
| #define | CAN_IE_RF0LE (_U_(0x1) << CAN_IE_RF0LE_Pos) |
| #define | CAN_IE_RF1NE_Pos 4 |
| (CAN_IE) Rx FIFO 1 New Message Interrupt Enable | |
| #define | CAN_IE_RF1NE (_U_(0x1) << CAN_IE_RF1NE_Pos) |
| #define | CAN_IE_RF1WE_Pos 5 |
| (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable | |
| #define | CAN_IE_RF1WE (_U_(0x1) << CAN_IE_RF1WE_Pos) |
| #define | CAN_IE_RF1FE_Pos 6 |
| (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable | |
| #define | CAN_IE_RF1FE (_U_(0x1) << CAN_IE_RF1FE_Pos) |
| #define | CAN_IE_RF1LE_Pos 7 |
| (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable | |
| #define | CAN_IE_RF1LE (_U_(0x1) << CAN_IE_RF1LE_Pos) |
| #define | CAN_IE_HPME_Pos 8 |
| (CAN_IE) High Priority Message Interrupt Enable | |
| #define | CAN_IE_HPME (_U_(0x1) << CAN_IE_HPME_Pos) |
| #define | CAN_IE_TCE_Pos 9 |
| (CAN_IE) Timestamp Completed Interrupt Enable | |
| #define | CAN_IE_TCE (_U_(0x1) << CAN_IE_TCE_Pos) |
| #define | CAN_IE_TCFE_Pos 10 |
| (CAN_IE) Transmission Cancellation Finished Interrupt Enable | |
| #define | CAN_IE_TCFE (_U_(0x1) << CAN_IE_TCFE_Pos) |
| #define | CAN_IE_TFEE_Pos 11 |
| (CAN_IE) Tx FIFO Empty Interrupt Enable | |
| #define | CAN_IE_TFEE (_U_(0x1) << CAN_IE_TFEE_Pos) |
| #define | CAN_IE_TEFNE_Pos 12 |
| (CAN_IE) Tx Event FIFO New Entry Interrupt Enable | |
| #define | CAN_IE_TEFNE (_U_(0x1) << CAN_IE_TEFNE_Pos) |
| #define | CAN_IE_TEFWE_Pos 13 |
| (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable | |
| #define | CAN_IE_TEFWE (_U_(0x1) << CAN_IE_TEFWE_Pos) |
| #define | CAN_IE_TEFFE_Pos 14 |
| (CAN_IE) Tx Event FIFO Full Interrupt Enable | |
| #define | CAN_IE_TEFFE (_U_(0x1) << CAN_IE_TEFFE_Pos) |
| #define | CAN_IE_TEFLE_Pos 15 |
| (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable | |
| #define | CAN_IE_TEFLE (_U_(0x1) << CAN_IE_TEFLE_Pos) |
| #define | CAN_IE_TSWE_Pos 16 |
| (CAN_IE) Timestamp Wraparound Interrupt Enable | |
| #define | CAN_IE_TSWE (_U_(0x1) << CAN_IE_TSWE_Pos) |
| #define | CAN_IE_MRAFE_Pos 17 |
| (CAN_IE) Message RAM Access Failure Interrupt Enable | |
| #define | CAN_IE_MRAFE (_U_(0x1) << CAN_IE_MRAFE_Pos) |
| #define | CAN_IE_TOOE_Pos 18 |
| (CAN_IE) Timeout Occurred Interrupt Enable | |
| #define | CAN_IE_TOOE (_U_(0x1) << CAN_IE_TOOE_Pos) |
| #define | CAN_IE_DRXE_Pos 19 |
| (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable | |
| #define | CAN_IE_DRXE (_U_(0x1) << CAN_IE_DRXE_Pos) |
| #define | CAN_IE_BECE_Pos 20 |
| (CAN_IE) Bit Error Corrected Interrupt Enable | |
| #define | CAN_IE_BECE (_U_(0x1) << CAN_IE_BECE_Pos) |
| #define | CAN_IE_BEUE_Pos 21 |
| (CAN_IE) Bit Error Uncorrected Interrupt Enable | |
| #define | CAN_IE_BEUE (_U_(0x1) << CAN_IE_BEUE_Pos) |
| #define | CAN_IE_ELOE_Pos 22 |
| (CAN_IE) Error Logging Overflow Interrupt Enable | |
| #define | CAN_IE_ELOE (_U_(0x1) << CAN_IE_ELOE_Pos) |
| #define | CAN_IE_EPE_Pos 23 |
| (CAN_IE) Error Passive Interrupt Enable | |
| #define | CAN_IE_EPE (_U_(0x1) << CAN_IE_EPE_Pos) |
| #define | CAN_IE_EWE_Pos 24 |
| (CAN_IE) Warning Status Interrupt Enable | |
| #define | CAN_IE_EWE (_U_(0x1) << CAN_IE_EWE_Pos) |
| #define | CAN_IE_BOE_Pos 25 |
| (CAN_IE) Bus_Off Status Interrupt Enable | |
| #define | CAN_IE_BOE (_U_(0x1) << CAN_IE_BOE_Pos) |
| #define | CAN_IE_WDIE_Pos 26 |
| (CAN_IE) Watchdog Interrupt Interrupt Enable | |
| #define | CAN_IE_WDIE (_U_(0x1) << CAN_IE_WDIE_Pos) |
| #define | CAN_IE_PEAE_Pos 27 |
| (CAN_IE) Protocol Error in Arbitration Phase Enable | |
| #define | CAN_IE_PEAE (_U_(0x1) << CAN_IE_PEAE_Pos) |
| #define | CAN_IE_PEDE_Pos 28 |
| (CAN_IE) Protocol Error in Data Phase Enable | |
| #define | CAN_IE_PEDE (_U_(0x1) << CAN_IE_PEDE_Pos) |
| #define | CAN_IE_ARAE_Pos 29 |
| (CAN_IE) Access to Reserved Address Enable | |
| #define | CAN_IE_ARAE (_U_(0x1) << CAN_IE_ARAE_Pos) |
| #define | CAN_IE_MASK _U_(0x3FFFFFFF) |
| (CAN_IE) MASK Register | |
| #define | CAN_ILS_OFFSET 0x58 |
| (CAN_ILS offset) Interrupt Line Select | |
| #define | CAN_ILS_RESETVALUE _U_(0x00000000) |
| (CAN_ILS reset_value) Interrupt Line Select | |
| #define | CAN_ILS_RF0NL_Pos 0 |
| (CAN_ILS) Rx FIFO 0 New Message Interrupt Line | |
| #define | CAN_ILS_RF0NL (_U_(0x1) << CAN_ILS_RF0NL_Pos) |
| #define | CAN_ILS_RF0WL_Pos 1 |
| (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line | |
| #define | CAN_ILS_RF0WL (_U_(0x1) << CAN_ILS_RF0WL_Pos) |
| #define | CAN_ILS_RF0FL_Pos 2 |
| (CAN_ILS) Rx FIFO 0 Full Interrupt Line | |
| #define | CAN_ILS_RF0FL (_U_(0x1) << CAN_ILS_RF0FL_Pos) |
| #define | CAN_ILS_RF0LL_Pos 3 |
| (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line | |
| #define | CAN_ILS_RF0LL (_U_(0x1) << CAN_ILS_RF0LL_Pos) |
| #define | CAN_ILS_RF1NL_Pos 4 |
| (CAN_ILS) Rx FIFO 1 New Message Interrupt Line | |
| #define | CAN_ILS_RF1NL (_U_(0x1) << CAN_ILS_RF1NL_Pos) |
| #define | CAN_ILS_RF1WL_Pos 5 |
| (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line | |
| #define | CAN_ILS_RF1WL (_U_(0x1) << CAN_ILS_RF1WL_Pos) |
| #define | CAN_ILS_RF1FL_Pos 6 |
| (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line | |
| #define | CAN_ILS_RF1FL (_U_(0x1) << CAN_ILS_RF1FL_Pos) |
| #define | CAN_ILS_RF1LL_Pos 7 |
| (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line | |
| #define | CAN_ILS_RF1LL (_U_(0x1) << CAN_ILS_RF1LL_Pos) |
| #define | CAN_ILS_HPML_Pos 8 |
| (CAN_ILS) High Priority Message Interrupt Line | |
| #define | CAN_ILS_HPML (_U_(0x1) << CAN_ILS_HPML_Pos) |
| #define | CAN_ILS_TCL_Pos 9 |
| (CAN_ILS) Timestamp Completed Interrupt Line | |
| #define | CAN_ILS_TCL (_U_(0x1) << CAN_ILS_TCL_Pos) |
| #define | CAN_ILS_TCFL_Pos 10 |
| (CAN_ILS) Transmission Cancellation Finished Interrupt Line | |
| #define | CAN_ILS_TCFL (_U_(0x1) << CAN_ILS_TCFL_Pos) |
| #define | CAN_ILS_TFEL_Pos 11 |
| (CAN_ILS) Tx FIFO Empty Interrupt Line | |
| #define | CAN_ILS_TFEL (_U_(0x1) << CAN_ILS_TFEL_Pos) |
| #define | CAN_ILS_TEFNL_Pos 12 |
| (CAN_ILS) Tx Event FIFO New Entry Interrupt Line | |
| #define | CAN_ILS_TEFNL (_U_(0x1) << CAN_ILS_TEFNL_Pos) |
| #define | CAN_ILS_TEFWL_Pos 13 |
| (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line | |
| #define | CAN_ILS_TEFWL (_U_(0x1) << CAN_ILS_TEFWL_Pos) |
| #define | CAN_ILS_TEFFL_Pos 14 |
| (CAN_ILS) Tx Event FIFO Full Interrupt Line | |
| #define | CAN_ILS_TEFFL (_U_(0x1) << CAN_ILS_TEFFL_Pos) |
| #define | CAN_ILS_TEFLL_Pos 15 |
| (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line | |
| #define | CAN_ILS_TEFLL (_U_(0x1) << CAN_ILS_TEFLL_Pos) |
| #define | CAN_ILS_TSWL_Pos 16 |
| (CAN_ILS) Timestamp Wraparound Interrupt Line | |
| #define | CAN_ILS_TSWL (_U_(0x1) << CAN_ILS_TSWL_Pos) |
| #define | CAN_ILS_MRAFL_Pos 17 |
| (CAN_ILS) Message RAM Access Failure Interrupt Line | |
| #define | CAN_ILS_MRAFL (_U_(0x1) << CAN_ILS_MRAFL_Pos) |
| #define | CAN_ILS_TOOL_Pos 18 |
| (CAN_ILS) Timeout Occurred Interrupt Line | |
| #define | CAN_ILS_TOOL (_U_(0x1) << CAN_ILS_TOOL_Pos) |
| #define | CAN_ILS_DRXL_Pos 19 |
| (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line | |
| #define | CAN_ILS_DRXL (_U_(0x1) << CAN_ILS_DRXL_Pos) |
| #define | CAN_ILS_BECL_Pos 20 |
| (CAN_ILS) Bit Error Corrected Interrupt Line | |
| #define | CAN_ILS_BECL (_U_(0x1) << CAN_ILS_BECL_Pos) |
| #define | CAN_ILS_BEUL_Pos 21 |
| (CAN_ILS) Bit Error Uncorrected Interrupt Line | |
| #define | CAN_ILS_BEUL (_U_(0x1) << CAN_ILS_BEUL_Pos) |
| #define | CAN_ILS_ELOL_Pos 22 |
| (CAN_ILS) Error Logging Overflow Interrupt Line | |
| #define | CAN_ILS_ELOL (_U_(0x1) << CAN_ILS_ELOL_Pos) |
| #define | CAN_ILS_EPL_Pos 23 |
| (CAN_ILS) Error Passive Interrupt Line | |
| #define | CAN_ILS_EPL (_U_(0x1) << CAN_ILS_EPL_Pos) |
| #define | CAN_ILS_EWL_Pos 24 |
| (CAN_ILS) Warning Status Interrupt Line | |
| #define | CAN_ILS_EWL (_U_(0x1) << CAN_ILS_EWL_Pos) |
| #define | CAN_ILS_BOL_Pos 25 |
| (CAN_ILS) Bus_Off Status Interrupt Line | |
| #define | CAN_ILS_BOL (_U_(0x1) << CAN_ILS_BOL_Pos) |
| #define | CAN_ILS_WDIL_Pos 26 |
| (CAN_ILS) Watchdog Interrupt Interrupt Line | |
| #define | CAN_ILS_WDIL (_U_(0x1) << CAN_ILS_WDIL_Pos) |
| #define | CAN_ILS_PEAL_Pos 27 |
| (CAN_ILS) Protocol Error in Arbitration Phase Line | |
| #define | CAN_ILS_PEAL (_U_(0x1) << CAN_ILS_PEAL_Pos) |
| #define | CAN_ILS_PEDL_Pos 28 |
| (CAN_ILS) Protocol Error in Data Phase Line | |
| #define | CAN_ILS_PEDL (_U_(0x1) << CAN_ILS_PEDL_Pos) |
| #define | CAN_ILS_ARAL_Pos 29 |
| (CAN_ILS) Access to Reserved Address Line | |
| #define | CAN_ILS_ARAL (_U_(0x1) << CAN_ILS_ARAL_Pos) |
| #define | CAN_ILS_MASK _U_(0x3FFFFFFF) |
| (CAN_ILS) MASK Register | |
| #define | CAN_ILE_OFFSET 0x5C |
| (CAN_ILE offset) Interrupt Line Enable | |
| #define | CAN_ILE_RESETVALUE _U_(0x00000000) |
| (CAN_ILE reset_value) Interrupt Line Enable | |
| #define | CAN_ILE_EINT0_Pos 0 |
| (CAN_ILE) Enable Interrupt Line 0 | |
| #define | CAN_ILE_EINT0 (_U_(0x1) << CAN_ILE_EINT0_Pos) |
| #define | CAN_ILE_EINT1_Pos 1 |
| (CAN_ILE) Enable Interrupt Line 1 | |
| #define | CAN_ILE_EINT1 (_U_(0x1) << CAN_ILE_EINT1_Pos) |
| #define | CAN_ILE_MASK _U_(0x00000003) |
| (CAN_ILE) MASK Register | |
| #define | CAN_GFC_OFFSET 0x80 |
| (CAN_GFC offset) Global Filter Configuration | |
| #define | CAN_GFC_RESETVALUE _U_(0x00000000) |
| (CAN_GFC reset_value) Global Filter Configuration | |
| #define | CAN_GFC_RRFE_Pos 0 |
| (CAN_GFC) Reject Remote Frames Extended | |
| #define | CAN_GFC_RRFE (_U_(0x1) << CAN_GFC_RRFE_Pos) |
| #define | CAN_GFC_RRFS_Pos 1 |
| (CAN_GFC) Reject Remote Frames Standard | |
| #define | CAN_GFC_RRFS (_U_(0x1) << CAN_GFC_RRFS_Pos) |
| #define | CAN_GFC_ANFE_Pos 2 |
| (CAN_GFC) Accept Non-matching Frames Extended | |
| #define | CAN_GFC_ANFE_Msk (_U_(0x3) << CAN_GFC_ANFE_Pos) |
| #define | CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos)) |
| #define | CAN_GFC_ANFE_RXF0_Val _U_(0x0) |
| (CAN_GFC) Accept in Rx FIFO 0 | |
| #define | CAN_GFC_ANFE_RXF1_Val _U_(0x1) |
| (CAN_GFC) Accept in Rx FIFO 1 | |
| #define | CAN_GFC_ANFE_REJECT_Val _U_(0x2) |
| (CAN_GFC) Reject | |
| #define | CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) |
| #define | CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) |
| #define | CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) |
| #define | CAN_GFC_ANFS_Pos 4 |
| (CAN_GFC) Accept Non-matching Frames Standard | |
| #define | CAN_GFC_ANFS_Msk (_U_(0x3) << CAN_GFC_ANFS_Pos) |
| #define | CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos)) |
| #define | CAN_GFC_ANFS_RXF0_Val _U_(0x0) |
| (CAN_GFC) Accept in Rx FIFO 0 | |
| #define | CAN_GFC_ANFS_RXF1_Val _U_(0x1) |
| (CAN_GFC) Accept in Rx FIFO 1 | |
| #define | CAN_GFC_ANFS_REJECT_Val _U_(0x2) |
| (CAN_GFC) Reject | |
| #define | CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) |
| #define | CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) |
| #define | CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) |
| #define | CAN_GFC_MASK _U_(0x0000003F) |
| (CAN_GFC) MASK Register | |
| #define | CAN_SIDFC_OFFSET 0x84 |
| (CAN_SIDFC offset) Standard ID Filter Configuration | |
| #define | CAN_SIDFC_RESETVALUE _U_(0x00000000) |
| (CAN_SIDFC reset_value) Standard ID Filter Configuration | |
| #define | CAN_SIDFC_FLSSA_Pos 0 |
| (CAN_SIDFC) Filter List Standard Start Address | |
| #define | CAN_SIDFC_FLSSA_Msk (_U_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) |
| #define | CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos)) |
| #define | CAN_SIDFC_LSS_Pos 16 |
| (CAN_SIDFC) List Size Standard | |
| #define | CAN_SIDFC_LSS_Msk (_U_(0xFF) << CAN_SIDFC_LSS_Pos) |
| #define | CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos)) |
| #define | CAN_SIDFC_MASK _U_(0x00FFFFFF) |
| (CAN_SIDFC) MASK Register | |
| #define | CAN_XIDFC_OFFSET 0x88 |
| (CAN_XIDFC offset) Extended ID Filter Configuration | |
| #define | CAN_XIDFC_RESETVALUE _U_(0x00000000) |
| (CAN_XIDFC reset_value) Extended ID Filter Configuration | |
| #define | CAN_XIDFC_FLESA_Pos 0 |
| (CAN_XIDFC) Filter List Extended Start Address | |
| #define | CAN_XIDFC_FLESA_Msk (_U_(0xFFFF) << CAN_XIDFC_FLESA_Pos) |
| #define | CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos)) |
| #define | CAN_XIDFC_LSE_Pos 16 |
| (CAN_XIDFC) List Size Extended | |
| #define | CAN_XIDFC_LSE_Msk (_U_(0x7F) << CAN_XIDFC_LSE_Pos) |
| #define | CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos)) |
| #define | CAN_XIDFC_MASK _U_(0x007FFFFF) |
| (CAN_XIDFC) MASK Register | |
| #define | CAN_XIDAM_OFFSET 0x90 |
| (CAN_XIDAM offset) Extended ID AND Mask | |
| #define | CAN_XIDAM_RESETVALUE _U_(0x1FFFFFFF) |
| (CAN_XIDAM reset_value) Extended ID AND Mask | |
| #define | CAN_XIDAM_EIDM_Pos 0 |
| (CAN_XIDAM) Extended ID Mask | |
| #define | CAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) |
| #define | CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos)) |
| #define | CAN_XIDAM_MASK _U_(0x1FFFFFFF) |
| (CAN_XIDAM) MASK Register | |
| #define | CAN_HPMS_OFFSET 0x94 |
| (CAN_HPMS offset) High Priority Message Status | |
| #define | CAN_HPMS_RESETVALUE _U_(0x00000000) |
| (CAN_HPMS reset_value) High Priority Message Status | |
| #define | CAN_HPMS_BIDX_Pos 0 |
| (CAN_HPMS) Buffer Index | |
| #define | CAN_HPMS_BIDX_Msk (_U_(0x3F) << CAN_HPMS_BIDX_Pos) |
| #define | CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos)) |
| #define | CAN_HPMS_MSI_Pos 6 |
| (CAN_HPMS) Message Storage Indicator | |
| #define | CAN_HPMS_MSI_Msk (_U_(0x3) << CAN_HPMS_MSI_Pos) |
| #define | CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos)) |
| #define | CAN_HPMS_MSI_NONE_Val _U_(0x0) |
| (CAN_HPMS) No FIFO selected | |
| #define | CAN_HPMS_MSI_LOST_Val _U_(0x1) |
| (CAN_HPMS) FIFO message lost | |
| #define | CAN_HPMS_MSI_FIFO0_Val _U_(0x2) |
| (CAN_HPMS) Message stored in FIFO 0 | |
| #define | CAN_HPMS_MSI_FIFO1_Val _U_(0x3) |
| (CAN_HPMS) Message stored in FIFO 1 | |
| #define | CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) |
| #define | CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) |
| #define | CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) |
| #define | CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) |
| #define | CAN_HPMS_FIDX_Pos 8 |
| (CAN_HPMS) Filter Index | |
| #define | CAN_HPMS_FIDX_Msk (_U_(0x7F) << CAN_HPMS_FIDX_Pos) |
| #define | CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos)) |
| #define | CAN_HPMS_FLST_Pos 15 |
| (CAN_HPMS) Filter List | |
| #define | CAN_HPMS_FLST (_U_(0x1) << CAN_HPMS_FLST_Pos) |
| #define | CAN_HPMS_MASK _U_(0x0000FFFF) |
| (CAN_HPMS) MASK Register | |
| #define | CAN_NDAT1_OFFSET 0x98 |
| (CAN_NDAT1 offset) New Data 1 | |
| #define | CAN_NDAT1_RESETVALUE _U_(0x00000000) |
| (CAN_NDAT1 reset_value) New Data 1 | |
| #define | CAN_NDAT1_ND0_Pos 0 |
| (CAN_NDAT1) New Data 0 | |
| #define | CAN_NDAT1_ND0 (_U_(0x1) << CAN_NDAT1_ND0_Pos) |
| #define | CAN_NDAT1_ND1_Pos 1 |
| (CAN_NDAT1) New Data 1 | |
| #define | CAN_NDAT1_ND1 (_U_(0x1) << CAN_NDAT1_ND1_Pos) |
| #define | CAN_NDAT1_ND2_Pos 2 |
| (CAN_NDAT1) New Data 2 | |
| #define | CAN_NDAT1_ND2 (_U_(0x1) << CAN_NDAT1_ND2_Pos) |
| #define | CAN_NDAT1_ND3_Pos 3 |
| (CAN_NDAT1) New Data 3 | |
| #define | CAN_NDAT1_ND3 (_U_(0x1) << CAN_NDAT1_ND3_Pos) |
| #define | CAN_NDAT1_ND4_Pos 4 |
| (CAN_NDAT1) New Data 4 | |
| #define | CAN_NDAT1_ND4 (_U_(0x1) << CAN_NDAT1_ND4_Pos) |
| #define | CAN_NDAT1_ND5_Pos 5 |
| (CAN_NDAT1) New Data 5 | |
| #define | CAN_NDAT1_ND5 (_U_(0x1) << CAN_NDAT1_ND5_Pos) |
| #define | CAN_NDAT1_ND6_Pos 6 |
| (CAN_NDAT1) New Data 6 | |
| #define | CAN_NDAT1_ND6 (_U_(0x1) << CAN_NDAT1_ND6_Pos) |
| #define | CAN_NDAT1_ND7_Pos 7 |
| (CAN_NDAT1) New Data 7 | |
| #define | CAN_NDAT1_ND7 (_U_(0x1) << CAN_NDAT1_ND7_Pos) |
| #define | CAN_NDAT1_ND8_Pos 8 |
| (CAN_NDAT1) New Data 8 | |
| #define | CAN_NDAT1_ND8 (_U_(0x1) << CAN_NDAT1_ND8_Pos) |
| #define | CAN_NDAT1_ND9_Pos 9 |
| (CAN_NDAT1) New Data 9 | |
| #define | CAN_NDAT1_ND9 (_U_(0x1) << CAN_NDAT1_ND9_Pos) |
| #define | CAN_NDAT1_ND10_Pos 10 |
| (CAN_NDAT1) New Data 10 | |
| #define | CAN_NDAT1_ND10 (_U_(0x1) << CAN_NDAT1_ND10_Pos) |
| #define | CAN_NDAT1_ND11_Pos 11 |
| (CAN_NDAT1) New Data 11 | |
| #define | CAN_NDAT1_ND11 (_U_(0x1) << CAN_NDAT1_ND11_Pos) |
| #define | CAN_NDAT1_ND12_Pos 12 |
| (CAN_NDAT1) New Data 12 | |
| #define | CAN_NDAT1_ND12 (_U_(0x1) << CAN_NDAT1_ND12_Pos) |
| #define | CAN_NDAT1_ND13_Pos 13 |
| (CAN_NDAT1) New Data 13 | |
| #define | CAN_NDAT1_ND13 (_U_(0x1) << CAN_NDAT1_ND13_Pos) |
| #define | CAN_NDAT1_ND14_Pos 14 |
| (CAN_NDAT1) New Data 14 | |
| #define | CAN_NDAT1_ND14 (_U_(0x1) << CAN_NDAT1_ND14_Pos) |
| #define | CAN_NDAT1_ND15_Pos 15 |
| (CAN_NDAT1) New Data 15 | |
| #define | CAN_NDAT1_ND15 (_U_(0x1) << CAN_NDAT1_ND15_Pos) |
| #define | CAN_NDAT1_ND16_Pos 16 |
| (CAN_NDAT1) New Data 16 | |
| #define | CAN_NDAT1_ND16 (_U_(0x1) << CAN_NDAT1_ND16_Pos) |
| #define | CAN_NDAT1_ND17_Pos 17 |
| (CAN_NDAT1) New Data 17 | |
| #define | CAN_NDAT1_ND17 (_U_(0x1) << CAN_NDAT1_ND17_Pos) |
| #define | CAN_NDAT1_ND18_Pos 18 |
| (CAN_NDAT1) New Data 18 | |
| #define | CAN_NDAT1_ND18 (_U_(0x1) << CAN_NDAT1_ND18_Pos) |
| #define | CAN_NDAT1_ND19_Pos 19 |
| (CAN_NDAT1) New Data 19 | |
| #define | CAN_NDAT1_ND19 (_U_(0x1) << CAN_NDAT1_ND19_Pos) |
| #define | CAN_NDAT1_ND20_Pos 20 |
| (CAN_NDAT1) New Data 20 | |
| #define | CAN_NDAT1_ND20 (_U_(0x1) << CAN_NDAT1_ND20_Pos) |
| #define | CAN_NDAT1_ND21_Pos 21 |
| (CAN_NDAT1) New Data 21 | |
| #define | CAN_NDAT1_ND21 (_U_(0x1) << CAN_NDAT1_ND21_Pos) |
| #define | CAN_NDAT1_ND22_Pos 22 |
| (CAN_NDAT1) New Data 22 | |
| #define | CAN_NDAT1_ND22 (_U_(0x1) << CAN_NDAT1_ND22_Pos) |
| #define | CAN_NDAT1_ND23_Pos 23 |
| (CAN_NDAT1) New Data 23 | |
| #define | CAN_NDAT1_ND23 (_U_(0x1) << CAN_NDAT1_ND23_Pos) |
| #define | CAN_NDAT1_ND24_Pos 24 |
| (CAN_NDAT1) New Data 24 | |
| #define | CAN_NDAT1_ND24 (_U_(0x1) << CAN_NDAT1_ND24_Pos) |
| #define | CAN_NDAT1_ND25_Pos 25 |
| (CAN_NDAT1) New Data 25 | |
| #define | CAN_NDAT1_ND25 (_U_(0x1) << CAN_NDAT1_ND25_Pos) |
| #define | CAN_NDAT1_ND26_Pos 26 |
| (CAN_NDAT1) New Data 26 | |
| #define | CAN_NDAT1_ND26 (_U_(0x1) << CAN_NDAT1_ND26_Pos) |
| #define | CAN_NDAT1_ND27_Pos 27 |
| (CAN_NDAT1) New Data 27 | |
| #define | CAN_NDAT1_ND27 (_U_(0x1) << CAN_NDAT1_ND27_Pos) |
| #define | CAN_NDAT1_ND28_Pos 28 |
| (CAN_NDAT1) New Data 28 | |
| #define | CAN_NDAT1_ND28 (_U_(0x1) << CAN_NDAT1_ND28_Pos) |
| #define | CAN_NDAT1_ND29_Pos 29 |
| (CAN_NDAT1) New Data 29 | |
| #define | CAN_NDAT1_ND29 (_U_(0x1) << CAN_NDAT1_ND29_Pos) |
| #define | CAN_NDAT1_ND30_Pos 30 |
| (CAN_NDAT1) New Data 30 | |
| #define | CAN_NDAT1_ND30 (_U_(0x1) << CAN_NDAT1_ND30_Pos) |
| #define | CAN_NDAT1_ND31_Pos 31 |
| (CAN_NDAT1) New Data 31 | |
| #define | CAN_NDAT1_ND31 (_U_(0x1) << CAN_NDAT1_ND31_Pos) |
| #define | CAN_NDAT1_MASK _U_(0xFFFFFFFF) |
| (CAN_NDAT1) MASK Register | |
| #define | CAN_NDAT2_OFFSET 0x9C |
| (CAN_NDAT2 offset) New Data 2 | |
| #define | CAN_NDAT2_RESETVALUE _U_(0x00000000) |
| (CAN_NDAT2 reset_value) New Data 2 | |
| #define | CAN_NDAT2_ND32_Pos 0 |
| (CAN_NDAT2) New Data 32 | |
| #define | CAN_NDAT2_ND32 (_U_(0x1) << CAN_NDAT2_ND32_Pos) |
| #define | CAN_NDAT2_ND33_Pos 1 |
| (CAN_NDAT2) New Data 33 | |
| #define | CAN_NDAT2_ND33 (_U_(0x1) << CAN_NDAT2_ND33_Pos) |
| #define | CAN_NDAT2_ND34_Pos 2 |
| (CAN_NDAT2) New Data 34 | |
| #define | CAN_NDAT2_ND34 (_U_(0x1) << CAN_NDAT2_ND34_Pos) |
| #define | CAN_NDAT2_ND35_Pos 3 |
| (CAN_NDAT2) New Data 35 | |
| #define | CAN_NDAT2_ND35 (_U_(0x1) << CAN_NDAT2_ND35_Pos) |
| #define | CAN_NDAT2_ND36_Pos 4 |
| (CAN_NDAT2) New Data 36 | |
| #define | CAN_NDAT2_ND36 (_U_(0x1) << CAN_NDAT2_ND36_Pos) |
| #define | CAN_NDAT2_ND37_Pos 5 |
| (CAN_NDAT2) New Data 37 | |
| #define | CAN_NDAT2_ND37 (_U_(0x1) << CAN_NDAT2_ND37_Pos) |
| #define | CAN_NDAT2_ND38_Pos 6 |
| (CAN_NDAT2) New Data 38 | |
| #define | CAN_NDAT2_ND38 (_U_(0x1) << CAN_NDAT2_ND38_Pos) |
| #define | CAN_NDAT2_ND39_Pos 7 |
| (CAN_NDAT2) New Data 39 | |
| #define | CAN_NDAT2_ND39 (_U_(0x1) << CAN_NDAT2_ND39_Pos) |
| #define | CAN_NDAT2_ND40_Pos 8 |
| (CAN_NDAT2) New Data 40 | |
| #define | CAN_NDAT2_ND40 (_U_(0x1) << CAN_NDAT2_ND40_Pos) |
| #define | CAN_NDAT2_ND41_Pos 9 |
| (CAN_NDAT2) New Data 41 | |
| #define | CAN_NDAT2_ND41 (_U_(0x1) << CAN_NDAT2_ND41_Pos) |
| #define | CAN_NDAT2_ND42_Pos 10 |
| (CAN_NDAT2) New Data 42 | |
| #define | CAN_NDAT2_ND42 (_U_(0x1) << CAN_NDAT2_ND42_Pos) |
| #define | CAN_NDAT2_ND43_Pos 11 |
| (CAN_NDAT2) New Data 43 | |
| #define | CAN_NDAT2_ND43 (_U_(0x1) << CAN_NDAT2_ND43_Pos) |
| #define | CAN_NDAT2_ND44_Pos 12 |
| (CAN_NDAT2) New Data 44 | |
| #define | CAN_NDAT2_ND44 (_U_(0x1) << CAN_NDAT2_ND44_Pos) |
| #define | CAN_NDAT2_ND45_Pos 13 |
| (CAN_NDAT2) New Data 45 | |
| #define | CAN_NDAT2_ND45 (_U_(0x1) << CAN_NDAT2_ND45_Pos) |
| #define | CAN_NDAT2_ND46_Pos 14 |
| (CAN_NDAT2) New Data 46 | |
| #define | CAN_NDAT2_ND46 (_U_(0x1) << CAN_NDAT2_ND46_Pos) |
| #define | CAN_NDAT2_ND47_Pos 15 |
| (CAN_NDAT2) New Data 47 | |
| #define | CAN_NDAT2_ND47 (_U_(0x1) << CAN_NDAT2_ND47_Pos) |
| #define | CAN_NDAT2_ND48_Pos 16 |
| (CAN_NDAT2) New Data 48 | |
| #define | CAN_NDAT2_ND48 (_U_(0x1) << CAN_NDAT2_ND48_Pos) |
| #define | CAN_NDAT2_ND49_Pos 17 |
| (CAN_NDAT2) New Data 49 | |
| #define | CAN_NDAT2_ND49 (_U_(0x1) << CAN_NDAT2_ND49_Pos) |
| #define | CAN_NDAT2_ND50_Pos 18 |
| (CAN_NDAT2) New Data 50 | |
| #define | CAN_NDAT2_ND50 (_U_(0x1) << CAN_NDAT2_ND50_Pos) |
| #define | CAN_NDAT2_ND51_Pos 19 |
| (CAN_NDAT2) New Data 51 | |
| #define | CAN_NDAT2_ND51 (_U_(0x1) << CAN_NDAT2_ND51_Pos) |
| #define | CAN_NDAT2_ND52_Pos 20 |
| (CAN_NDAT2) New Data 52 | |
| #define | CAN_NDAT2_ND52 (_U_(0x1) << CAN_NDAT2_ND52_Pos) |
| #define | CAN_NDAT2_ND53_Pos 21 |
| (CAN_NDAT2) New Data 53 | |
| #define | CAN_NDAT2_ND53 (_U_(0x1) << CAN_NDAT2_ND53_Pos) |
| #define | CAN_NDAT2_ND54_Pos 22 |
| (CAN_NDAT2) New Data 54 | |
| #define | CAN_NDAT2_ND54 (_U_(0x1) << CAN_NDAT2_ND54_Pos) |
| #define | CAN_NDAT2_ND55_Pos 23 |
| (CAN_NDAT2) New Data 55 | |
| #define | CAN_NDAT2_ND55 (_U_(0x1) << CAN_NDAT2_ND55_Pos) |
| #define | CAN_NDAT2_ND56_Pos 24 |
| (CAN_NDAT2) New Data 56 | |
| #define | CAN_NDAT2_ND56 (_U_(0x1) << CAN_NDAT2_ND56_Pos) |
| #define | CAN_NDAT2_ND57_Pos 25 |
| (CAN_NDAT2) New Data 57 | |
| #define | CAN_NDAT2_ND57 (_U_(0x1) << CAN_NDAT2_ND57_Pos) |
| #define | CAN_NDAT2_ND58_Pos 26 |
| (CAN_NDAT2) New Data 58 | |
| #define | CAN_NDAT2_ND58 (_U_(0x1) << CAN_NDAT2_ND58_Pos) |
| #define | CAN_NDAT2_ND59_Pos 27 |
| (CAN_NDAT2) New Data 59 | |
| #define | CAN_NDAT2_ND59 (_U_(0x1) << CAN_NDAT2_ND59_Pos) |
| #define | CAN_NDAT2_ND60_Pos 28 |
| (CAN_NDAT2) New Data 60 | |
| #define | CAN_NDAT2_ND60 (_U_(0x1) << CAN_NDAT2_ND60_Pos) |
| #define | CAN_NDAT2_ND61_Pos 29 |
| (CAN_NDAT2) New Data 61 | |
| #define | CAN_NDAT2_ND61 (_U_(0x1) << CAN_NDAT2_ND61_Pos) |
| #define | CAN_NDAT2_ND62_Pos 30 |
| (CAN_NDAT2) New Data 62 | |
| #define | CAN_NDAT2_ND62 (_U_(0x1) << CAN_NDAT2_ND62_Pos) |
| #define | CAN_NDAT2_ND63_Pos 31 |
| (CAN_NDAT2) New Data 63 | |
| #define | CAN_NDAT2_ND63 (_U_(0x1) << CAN_NDAT2_ND63_Pos) |
| #define | CAN_NDAT2_MASK _U_(0xFFFFFFFF) |
| (CAN_NDAT2) MASK Register | |
| #define | CAN_RXF0C_OFFSET 0xA0 |
| (CAN_RXF0C offset) Rx FIFO 0 Configuration | |
| #define | CAN_RXF0C_RESETVALUE _U_(0x00000000) |
| (CAN_RXF0C reset_value) Rx FIFO 0 Configuration | |
| #define | CAN_RXF0C_F0SA_Pos 0 |
| (CAN_RXF0C) Rx FIFO 0 Start Address | |
| #define | CAN_RXF0C_F0SA_Msk (_U_(0xFFFF) << CAN_RXF0C_F0SA_Pos) |
| #define | CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos)) |
| #define | CAN_RXF0C_F0S_Pos 16 |
| (CAN_RXF0C) Rx FIFO 0 Size | |
| #define | CAN_RXF0C_F0S_Msk (_U_(0x7F) << CAN_RXF0C_F0S_Pos) |
| #define | CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos)) |
| #define | CAN_RXF0C_F0WM_Pos 24 |
| (CAN_RXF0C) Rx FIFO 0 Watermark | |
| #define | CAN_RXF0C_F0WM_Msk (_U_(0x7F) << CAN_RXF0C_F0WM_Pos) |
| #define | CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos)) |
| #define | CAN_RXF0C_F0OM_Pos 31 |
| (CAN_RXF0C) FIFO 0 Operation Mode | |
| #define | CAN_RXF0C_F0OM (_U_(0x1) << CAN_RXF0C_F0OM_Pos) |
| #define | CAN_RXF0C_MASK _U_(0xFF7FFFFF) |
| (CAN_RXF0C) MASK Register | |
| #define | CAN_RXF0S_OFFSET 0xA4 |
| (CAN_RXF0S offset) Rx FIFO 0 Status | |
| #define | CAN_RXF0S_RESETVALUE _U_(0x00000000) |
| (CAN_RXF0S reset_value) Rx FIFO 0 Status | |
| #define | CAN_RXF0S_F0FL_Pos 0 |
| (CAN_RXF0S) Rx FIFO 0 Fill Level | |
| #define | CAN_RXF0S_F0FL_Msk (_U_(0x7F) << CAN_RXF0S_F0FL_Pos) |
| #define | CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos)) |
| #define | CAN_RXF0S_F0GI_Pos 8 |
| (CAN_RXF0S) Rx FIFO 0 Get Index | |
| #define | CAN_RXF0S_F0GI_Msk (_U_(0x3F) << CAN_RXF0S_F0GI_Pos) |
| #define | CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos)) |
| #define | CAN_RXF0S_F0PI_Pos 16 |
| (CAN_RXF0S) Rx FIFO 0 Put Index | |
| #define | CAN_RXF0S_F0PI_Msk (_U_(0x3F) << CAN_RXF0S_F0PI_Pos) |
| #define | CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos)) |
| #define | CAN_RXF0S_F0F_Pos 24 |
| (CAN_RXF0S) Rx FIFO 0 Full | |
| #define | CAN_RXF0S_F0F (_U_(0x1) << CAN_RXF0S_F0F_Pos) |
| #define | CAN_RXF0S_RF0L_Pos 25 |
| (CAN_RXF0S) Rx FIFO 0 Message Lost | |
| #define | CAN_RXF0S_RF0L (_U_(0x1) << CAN_RXF0S_RF0L_Pos) |
| #define | CAN_RXF0S_MASK _U_(0x033F3F7F) |
| (CAN_RXF0S) MASK Register | |
| #define | CAN_RXF0A_OFFSET 0xA8 |
| (CAN_RXF0A offset) Rx FIFO 0 Acknowledge | |
| #define | CAN_RXF0A_RESETVALUE _U_(0x00000000) |
| (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge | |
| #define | CAN_RXF0A_F0AI_Pos 0 |
| (CAN_RXF0A) Rx FIFO 0 Acknowledge Index | |
| #define | CAN_RXF0A_F0AI_Msk (_U_(0x3F) << CAN_RXF0A_F0AI_Pos) |
| #define | CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos)) |
| #define | CAN_RXF0A_MASK _U_(0x0000003F) |
| (CAN_RXF0A) MASK Register | |
| #define | CAN_RXBC_OFFSET 0xAC |
| (CAN_RXBC offset) Rx Buffer Configuration | |
| #define | CAN_RXBC_RESETVALUE _U_(0x00000000) |
| (CAN_RXBC reset_value) Rx Buffer Configuration | |
| #define | CAN_RXBC_RBSA_Pos 0 |
| (CAN_RXBC) Rx Buffer Start Address | |
| #define | CAN_RXBC_RBSA_Msk (_U_(0xFFFF) << CAN_RXBC_RBSA_Pos) |
| #define | CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos)) |
| #define | CAN_RXBC_MASK _U_(0x0000FFFF) |
| (CAN_RXBC) MASK Register | |
| #define | CAN_RXF1C_OFFSET 0xB0 |
| (CAN_RXF1C offset) Rx FIFO 1 Configuration | |
| #define | CAN_RXF1C_RESETVALUE _U_(0x00000000) |
| (CAN_RXF1C reset_value) Rx FIFO 1 Configuration | |
| #define | CAN_RXF1C_F1SA_Pos 0 |
| (CAN_RXF1C) Rx FIFO 1 Start Address | |
| #define | CAN_RXF1C_F1SA_Msk (_U_(0xFFFF) << CAN_RXF1C_F1SA_Pos) |
| #define | CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos)) |
| #define | CAN_RXF1C_F1S_Pos 16 |
| (CAN_RXF1C) Rx FIFO 1 Size | |
| #define | CAN_RXF1C_F1S_Msk (_U_(0x7F) << CAN_RXF1C_F1S_Pos) |
| #define | CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos)) |
| #define | CAN_RXF1C_F1WM_Pos 24 |
| (CAN_RXF1C) Rx FIFO 1 Watermark | |
| #define | CAN_RXF1C_F1WM_Msk (_U_(0x7F) << CAN_RXF1C_F1WM_Pos) |
| #define | CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos)) |
| #define | CAN_RXF1C_F1OM_Pos 31 |
| (CAN_RXF1C) FIFO 1 Operation Mode | |
| #define | CAN_RXF1C_F1OM (_U_(0x1) << CAN_RXF1C_F1OM_Pos) |
| #define | CAN_RXF1C_MASK _U_(0xFF7FFFFF) |
| (CAN_RXF1C) MASK Register | |
| #define | CAN_RXF1S_OFFSET 0xB4 |
| (CAN_RXF1S offset) Rx FIFO 1 Status | |
| #define | CAN_RXF1S_RESETVALUE _U_(0x00000000) |
| (CAN_RXF1S reset_value) Rx FIFO 1 Status | |
| #define | CAN_RXF1S_F1FL_Pos 0 |
| (CAN_RXF1S) Rx FIFO 1 Fill Level | |
| #define | CAN_RXF1S_F1FL_Msk (_U_(0x7F) << CAN_RXF1S_F1FL_Pos) |
| #define | CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos)) |
| #define | CAN_RXF1S_F1GI_Pos 8 |
| (CAN_RXF1S) Rx FIFO 1 Get Index | |
| #define | CAN_RXF1S_F1GI_Msk (_U_(0x3F) << CAN_RXF1S_F1GI_Pos) |
| #define | CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos)) |
| #define | CAN_RXF1S_F1PI_Pos 16 |
| (CAN_RXF1S) Rx FIFO 1 Put Index | |
| #define | CAN_RXF1S_F1PI_Msk (_U_(0x3F) << CAN_RXF1S_F1PI_Pos) |
| #define | CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos)) |
| #define | CAN_RXF1S_F1F_Pos 24 |
| (CAN_RXF1S) Rx FIFO 1 Full | |
| #define | CAN_RXF1S_F1F (_U_(0x1) << CAN_RXF1S_F1F_Pos) |
| #define | CAN_RXF1S_RF1L_Pos 25 |
| (CAN_RXF1S) Rx FIFO 1 Message Lost | |
| #define | CAN_RXF1S_RF1L (_U_(0x1) << CAN_RXF1S_RF1L_Pos) |
| #define | CAN_RXF1S_DMS_Pos 30 |
| (CAN_RXF1S) Debug Message Status | |
| #define | CAN_RXF1S_DMS_Msk (_U_(0x3) << CAN_RXF1S_DMS_Pos) |
| #define | CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos)) |
| #define | CAN_RXF1S_DMS_IDLE_Val _U_(0x0) |
| (CAN_RXF1S) Idle state | |
| #define | CAN_RXF1S_DMS_DBGA_Val _U_(0x1) |
| (CAN_RXF1S) Debug message A received | |
| #define | CAN_RXF1S_DMS_DBGB_Val _U_(0x2) |
| (CAN_RXF1S) Debug message A/B received | |
| #define | CAN_RXF1S_DMS_DBGC_Val _U_(0x3) |
| (CAN_RXF1S) Debug message A/B/C received, DMA request set | |
| #define | CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) |
| #define | CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) |
| #define | CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) |
| #define | CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) |
| #define | CAN_RXF1S_MASK _U_(0xC33F3F7F) |
| (CAN_RXF1S) MASK Register | |
| #define | CAN_RXF1A_OFFSET 0xB8 |
| (CAN_RXF1A offset) Rx FIFO 1 Acknowledge | |
| #define | CAN_RXF1A_RESETVALUE _U_(0x00000000) |
| (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge | |
| #define | CAN_RXF1A_F1AI_Pos 0 |
| (CAN_RXF1A) Rx FIFO 1 Acknowledge Index | |
| #define | CAN_RXF1A_F1AI_Msk (_U_(0x3F) << CAN_RXF1A_F1AI_Pos) |
| #define | CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos)) |
| #define | CAN_RXF1A_MASK _U_(0x0000003F) |
| (CAN_RXF1A) MASK Register | |
| #define | CAN_RXESC_OFFSET 0xBC |
| (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration | |
| #define | CAN_RXESC_RESETVALUE _U_(0x00000000) |
| (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration | |
| #define | CAN_RXESC_F0DS_Pos 0 |
| (CAN_RXESC) Rx FIFO 0 Data Field Size | |
| #define | CAN_RXESC_F0DS_Msk (_U_(0x7) << CAN_RXESC_F0DS_Pos) |
| #define | CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos)) |
| #define | CAN_RXESC_F0DS_DATA8_Val _U_(0x0) |
| (CAN_RXESC) 8 byte data field | |
| #define | CAN_RXESC_F0DS_DATA12_Val _U_(0x1) |
| (CAN_RXESC) 12 byte data field | |
| #define | CAN_RXESC_F0DS_DATA16_Val _U_(0x2) |
| (CAN_RXESC) 16 byte data field | |
| #define | CAN_RXESC_F0DS_DATA20_Val _U_(0x3) |
| (CAN_RXESC) 20 byte data field | |
| #define | CAN_RXESC_F0DS_DATA24_Val _U_(0x4) |
| (CAN_RXESC) 24 byte data field | |
| #define | CAN_RXESC_F0DS_DATA32_Val _U_(0x5) |
| (CAN_RXESC) 32 byte data field | |
| #define | CAN_RXESC_F0DS_DATA48_Val _U_(0x6) |
| (CAN_RXESC) 48 byte data field | |
| #define | CAN_RXESC_F0DS_DATA64_Val _U_(0x7) |
| (CAN_RXESC) 64 byte data field | |
| #define | CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) |
| #define | CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) |
| #define | CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) |
| #define | CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) |
| #define | CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) |
| #define | CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) |
| #define | CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) |
| #define | CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) |
| #define | CAN_RXESC_F1DS_Pos 4 |
| (CAN_RXESC) Rx FIFO 1 Data Field Size | |
| #define | CAN_RXESC_F1DS_Msk (_U_(0x7) << CAN_RXESC_F1DS_Pos) |
| #define | CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos)) |
| #define | CAN_RXESC_F1DS_DATA8_Val _U_(0x0) |
| (CAN_RXESC) 8 byte data field | |
| #define | CAN_RXESC_F1DS_DATA12_Val _U_(0x1) |
| (CAN_RXESC) 12 byte data field | |
| #define | CAN_RXESC_F1DS_DATA16_Val _U_(0x2) |
| (CAN_RXESC) 16 byte data field | |
| #define | CAN_RXESC_F1DS_DATA20_Val _U_(0x3) |
| (CAN_RXESC) 20 byte data field | |
| #define | CAN_RXESC_F1DS_DATA24_Val _U_(0x4) |
| (CAN_RXESC) 24 byte data field | |
| #define | CAN_RXESC_F1DS_DATA32_Val _U_(0x5) |
| (CAN_RXESC) 32 byte data field | |
| #define | CAN_RXESC_F1DS_DATA48_Val _U_(0x6) |
| (CAN_RXESC) 48 byte data field | |
| #define | CAN_RXESC_F1DS_DATA64_Val _U_(0x7) |
| (CAN_RXESC) 64 byte data field | |
| #define | CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) |
| #define | CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) |
| #define | CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) |
| #define | CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) |
| #define | CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) |
| #define | CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) |
| #define | CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) |
| #define | CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) |
| #define | CAN_RXESC_RBDS_Pos 8 |
| (CAN_RXESC) Rx Buffer Data Field Size | |
| #define | CAN_RXESC_RBDS_Msk (_U_(0x7) << CAN_RXESC_RBDS_Pos) |
| #define | CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos)) |
| #define | CAN_RXESC_RBDS_DATA8_Val _U_(0x0) |
| (CAN_RXESC) 8 byte data field | |
| #define | CAN_RXESC_RBDS_DATA12_Val _U_(0x1) |
| (CAN_RXESC) 12 byte data field | |
| #define | CAN_RXESC_RBDS_DATA16_Val _U_(0x2) |
| (CAN_RXESC) 16 byte data field | |
| #define | CAN_RXESC_RBDS_DATA20_Val _U_(0x3) |
| (CAN_RXESC) 20 byte data field | |
| #define | CAN_RXESC_RBDS_DATA24_Val _U_(0x4) |
| (CAN_RXESC) 24 byte data field | |
| #define | CAN_RXESC_RBDS_DATA32_Val _U_(0x5) |
| (CAN_RXESC) 32 byte data field | |
| #define | CAN_RXESC_RBDS_DATA48_Val _U_(0x6) |
| (CAN_RXESC) 48 byte data field | |
| #define | CAN_RXESC_RBDS_DATA64_Val _U_(0x7) |
| (CAN_RXESC) 64 byte data field | |
| #define | CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) |
| #define | CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) |
| #define | CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) |
| #define | CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) |
| #define | CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) |
| #define | CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) |
| #define | CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) |
| #define | CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) |
| #define | CAN_RXESC_MASK _U_(0x00000777) |
| (CAN_RXESC) MASK Register | |
| #define | CAN_TXBC_OFFSET 0xC0 |
| (CAN_TXBC offset) Tx Buffer Configuration | |
| #define | CAN_TXBC_RESETVALUE _U_(0x00000000) |
| (CAN_TXBC reset_value) Tx Buffer Configuration | |
| #define | CAN_TXBC_TBSA_Pos 0 |
| (CAN_TXBC) Tx Buffers Start Address | |
| #define | CAN_TXBC_TBSA_Msk (_U_(0xFFFF) << CAN_TXBC_TBSA_Pos) |
| #define | CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos)) |
| #define | CAN_TXBC_NDTB_Pos 16 |
| (CAN_TXBC) Number of Dedicated Transmit Buffers | |
| #define | CAN_TXBC_NDTB_Msk (_U_(0x3F) << CAN_TXBC_NDTB_Pos) |
| #define | CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos)) |
| #define | CAN_TXBC_TFQS_Pos 24 |
| (CAN_TXBC) Transmit FIFO/Queue Size | |
| #define | CAN_TXBC_TFQS_Msk (_U_(0x3F) << CAN_TXBC_TFQS_Pos) |
| #define | CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos)) |
| #define | CAN_TXBC_TFQM_Pos 30 |
| (CAN_TXBC) Tx FIFO/Queue Mode | |
| #define | CAN_TXBC_TFQM (_U_(0x1) << CAN_TXBC_TFQM_Pos) |
| #define | CAN_TXBC_MASK _U_(0x7F3FFFFF) |
| (CAN_TXBC) MASK Register | |
| #define | CAN_TXFQS_OFFSET 0xC4 |
| (CAN_TXFQS offset) Tx FIFO / Queue Status | |
| #define | CAN_TXFQS_RESETVALUE _U_(0x00000000) |
| (CAN_TXFQS reset_value) Tx FIFO / Queue Status | |
| #define | CAN_TXFQS_TFFL_Pos 0 |
| (CAN_TXFQS) Tx FIFO Free Level | |
| #define | CAN_TXFQS_TFFL_Msk (_U_(0x3F) << CAN_TXFQS_TFFL_Pos) |
| #define | CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos)) |
| #define | CAN_TXFQS_TFGI_Pos 8 |
| (CAN_TXFQS) Tx FIFO Get Index | |
| #define | CAN_TXFQS_TFGI_Msk (_U_(0x1F) << CAN_TXFQS_TFGI_Pos) |
| #define | CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos)) |
| #define | CAN_TXFQS_TFQPI_Pos 16 |
| (CAN_TXFQS) Tx FIFO/Queue Put Index | |
| #define | CAN_TXFQS_TFQPI_Msk (_U_(0x1F) << CAN_TXFQS_TFQPI_Pos) |
| #define | CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos)) |
| #define | CAN_TXFQS_TFQF_Pos 21 |
| (CAN_TXFQS) Tx FIFO/Queue Full | |
| #define | CAN_TXFQS_TFQF (_U_(0x1) << CAN_TXFQS_TFQF_Pos) |
| #define | CAN_TXFQS_MASK _U_(0x003F1F3F) |
| (CAN_TXFQS) MASK Register | |
| #define | CAN_TXESC_OFFSET 0xC8 |
| (CAN_TXESC offset) Tx Buffer Element Size Configuration | |
| #define | CAN_TXESC_RESETVALUE _U_(0x00000000) |
| (CAN_TXESC reset_value) Tx Buffer Element Size Configuration | |
| #define | CAN_TXESC_TBDS_Pos 0 |
| (CAN_TXESC) Tx Buffer Data Field Size | |
| #define | CAN_TXESC_TBDS_Msk (_U_(0x7) << CAN_TXESC_TBDS_Pos) |
| #define | CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos)) |
| #define | CAN_TXESC_TBDS_DATA8_Val _U_(0x0) |
| (CAN_TXESC) 8 byte data field | |
| #define | CAN_TXESC_TBDS_DATA12_Val _U_(0x1) |
| (CAN_TXESC) 12 byte data field | |
| #define | CAN_TXESC_TBDS_DATA16_Val _U_(0x2) |
| (CAN_TXESC) 16 byte data field | |
| #define | CAN_TXESC_TBDS_DATA20_Val _U_(0x3) |
| (CAN_TXESC) 20 byte data field | |
| #define | CAN_TXESC_TBDS_DATA24_Val _U_(0x4) |
| (CAN_TXESC) 24 byte data field | |
| #define | CAN_TXESC_TBDS_DATA32_Val _U_(0x5) |
| (CAN_TXESC) 32 byte data field | |
| #define | CAN_TXESC_TBDS_DATA48_Val _U_(0x6) |
| (CAN_TXESC) 48 byte data field | |
| #define | CAN_TXESC_TBDS_DATA64_Val _U_(0x7) |
| (CAN_TXESC) 64 byte data field | |
| #define | CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) |
| #define | CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) |
| #define | CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) |
| #define | CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) |
| #define | CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) |
| #define | CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) |
| #define | CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) |
| #define | CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) |
| #define | CAN_TXESC_MASK _U_(0x00000007) |
| (CAN_TXESC) MASK Register | |
| #define | CAN_TXBRP_OFFSET 0xCC |
| (CAN_TXBRP offset) Tx Buffer Request Pending | |
| #define | CAN_TXBRP_RESETVALUE _U_(0x00000000) |
| (CAN_TXBRP reset_value) Tx Buffer Request Pending | |
| #define | CAN_TXBRP_TRP0_Pos 0 |
| (CAN_TXBRP) Transmission Request Pending 0 | |
| #define | CAN_TXBRP_TRP0 (_U_(0x1) << CAN_TXBRP_TRP0_Pos) |
| #define | CAN_TXBRP_TRP1_Pos 1 |
| (CAN_TXBRP) Transmission Request Pending 1 | |
| #define | CAN_TXBRP_TRP1 (_U_(0x1) << CAN_TXBRP_TRP1_Pos) |
| #define | CAN_TXBRP_TRP2_Pos 2 |
| (CAN_TXBRP) Transmission Request Pending 2 | |
| #define | CAN_TXBRP_TRP2 (_U_(0x1) << CAN_TXBRP_TRP2_Pos) |
| #define | CAN_TXBRP_TRP3_Pos 3 |
| (CAN_TXBRP) Transmission Request Pending 3 | |
| #define | CAN_TXBRP_TRP3 (_U_(0x1) << CAN_TXBRP_TRP3_Pos) |
| #define | CAN_TXBRP_TRP4_Pos 4 |
| (CAN_TXBRP) Transmission Request Pending 4 | |
| #define | CAN_TXBRP_TRP4 (_U_(0x1) << CAN_TXBRP_TRP4_Pos) |
| #define | CAN_TXBRP_TRP5_Pos 5 |
| (CAN_TXBRP) Transmission Request Pending 5 | |
| #define | CAN_TXBRP_TRP5 (_U_(0x1) << CAN_TXBRP_TRP5_Pos) |
| #define | CAN_TXBRP_TRP6_Pos 6 |
| (CAN_TXBRP) Transmission Request Pending 6 | |
| #define | CAN_TXBRP_TRP6 (_U_(0x1) << CAN_TXBRP_TRP6_Pos) |
| #define | CAN_TXBRP_TRP7_Pos 7 |
| (CAN_TXBRP) Transmission Request Pending 7 | |
| #define | CAN_TXBRP_TRP7 (_U_(0x1) << CAN_TXBRP_TRP7_Pos) |
| #define | CAN_TXBRP_TRP8_Pos 8 |
| (CAN_TXBRP) Transmission Request Pending 8 | |
| #define | CAN_TXBRP_TRP8 (_U_(0x1) << CAN_TXBRP_TRP8_Pos) |
| #define | CAN_TXBRP_TRP9_Pos 9 |
| (CAN_TXBRP) Transmission Request Pending 9 | |
| #define | CAN_TXBRP_TRP9 (_U_(0x1) << CAN_TXBRP_TRP9_Pos) |
| #define | CAN_TXBRP_TRP10_Pos 10 |
| (CAN_TXBRP) Transmission Request Pending 10 | |
| #define | CAN_TXBRP_TRP10 (_U_(0x1) << CAN_TXBRP_TRP10_Pos) |
| #define | CAN_TXBRP_TRP11_Pos 11 |
| (CAN_TXBRP) Transmission Request Pending 11 | |
| #define | CAN_TXBRP_TRP11 (_U_(0x1) << CAN_TXBRP_TRP11_Pos) |
| #define | CAN_TXBRP_TRP12_Pos 12 |
| (CAN_TXBRP) Transmission Request Pending 12 | |
| #define | CAN_TXBRP_TRP12 (_U_(0x1) << CAN_TXBRP_TRP12_Pos) |
| #define | CAN_TXBRP_TRP13_Pos 13 |
| (CAN_TXBRP) Transmission Request Pending 13 | |
| #define | CAN_TXBRP_TRP13 (_U_(0x1) << CAN_TXBRP_TRP13_Pos) |
| #define | CAN_TXBRP_TRP14_Pos 14 |
| (CAN_TXBRP) Transmission Request Pending 14 | |
| #define | CAN_TXBRP_TRP14 (_U_(0x1) << CAN_TXBRP_TRP14_Pos) |
| #define | CAN_TXBRP_TRP15_Pos 15 |
| (CAN_TXBRP) Transmission Request Pending 15 | |
| #define | CAN_TXBRP_TRP15 (_U_(0x1) << CAN_TXBRP_TRP15_Pos) |
| #define | CAN_TXBRP_TRP16_Pos 16 |
| (CAN_TXBRP) Transmission Request Pending 16 | |
| #define | CAN_TXBRP_TRP16 (_U_(0x1) << CAN_TXBRP_TRP16_Pos) |
| #define | CAN_TXBRP_TRP17_Pos 17 |
| (CAN_TXBRP) Transmission Request Pending 17 | |
| #define | CAN_TXBRP_TRP17 (_U_(0x1) << CAN_TXBRP_TRP17_Pos) |
| #define | CAN_TXBRP_TRP18_Pos 18 |
| (CAN_TXBRP) Transmission Request Pending 18 | |
| #define | CAN_TXBRP_TRP18 (_U_(0x1) << CAN_TXBRP_TRP18_Pos) |
| #define | CAN_TXBRP_TRP19_Pos 19 |
| (CAN_TXBRP) Transmission Request Pending 19 | |
| #define | CAN_TXBRP_TRP19 (_U_(0x1) << CAN_TXBRP_TRP19_Pos) |
| #define | CAN_TXBRP_TRP20_Pos 20 |
| (CAN_TXBRP) Transmission Request Pending 20 | |
| #define | CAN_TXBRP_TRP20 (_U_(0x1) << CAN_TXBRP_TRP20_Pos) |
| #define | CAN_TXBRP_TRP21_Pos 21 |
| (CAN_TXBRP) Transmission Request Pending 21 | |
| #define | CAN_TXBRP_TRP21 (_U_(0x1) << CAN_TXBRP_TRP21_Pos) |
| #define | CAN_TXBRP_TRP22_Pos 22 |
| (CAN_TXBRP) Transmission Request Pending 22 | |
| #define | CAN_TXBRP_TRP22 (_U_(0x1) << CAN_TXBRP_TRP22_Pos) |
| #define | CAN_TXBRP_TRP23_Pos 23 |
| (CAN_TXBRP) Transmission Request Pending 23 | |
| #define | CAN_TXBRP_TRP23 (_U_(0x1) << CAN_TXBRP_TRP23_Pos) |
| #define | CAN_TXBRP_TRP24_Pos 24 |
| (CAN_TXBRP) Transmission Request Pending 24 | |
| #define | CAN_TXBRP_TRP24 (_U_(0x1) << CAN_TXBRP_TRP24_Pos) |
| #define | CAN_TXBRP_TRP25_Pos 25 |
| (CAN_TXBRP) Transmission Request Pending 25 | |
| #define | CAN_TXBRP_TRP25 (_U_(0x1) << CAN_TXBRP_TRP25_Pos) |
| #define | CAN_TXBRP_TRP26_Pos 26 |
| (CAN_TXBRP) Transmission Request Pending 26 | |
| #define | CAN_TXBRP_TRP26 (_U_(0x1) << CAN_TXBRP_TRP26_Pos) |
| #define | CAN_TXBRP_TRP27_Pos 27 |
| (CAN_TXBRP) Transmission Request Pending 27 | |
| #define | CAN_TXBRP_TRP27 (_U_(0x1) << CAN_TXBRP_TRP27_Pos) |
| #define | CAN_TXBRP_TRP28_Pos 28 |
| (CAN_TXBRP) Transmission Request Pending 28 | |
| #define | CAN_TXBRP_TRP28 (_U_(0x1) << CAN_TXBRP_TRP28_Pos) |
| #define | CAN_TXBRP_TRP29_Pos 29 |
| (CAN_TXBRP) Transmission Request Pending 29 | |
| #define | CAN_TXBRP_TRP29 (_U_(0x1) << CAN_TXBRP_TRP29_Pos) |
| #define | CAN_TXBRP_TRP30_Pos 30 |
| (CAN_TXBRP) Transmission Request Pending 30 | |
| #define | CAN_TXBRP_TRP30 (_U_(0x1) << CAN_TXBRP_TRP30_Pos) |
| #define | CAN_TXBRP_TRP31_Pos 31 |
| (CAN_TXBRP) Transmission Request Pending 31 | |
| #define | CAN_TXBRP_TRP31 (_U_(0x1) << CAN_TXBRP_TRP31_Pos) |
| #define | CAN_TXBRP_MASK _U_(0xFFFFFFFF) |
| (CAN_TXBRP) MASK Register | |
| #define | CAN_TXBAR_OFFSET 0xD0 |
| (CAN_TXBAR offset) Tx Buffer Add Request | |
| #define | CAN_TXBAR_RESETVALUE _U_(0x00000000) |
| (CAN_TXBAR reset_value) Tx Buffer Add Request | |
| #define | CAN_TXBAR_AR0_Pos 0 |
| (CAN_TXBAR) Add Request 0 | |
| #define | CAN_TXBAR_AR0 (_U_(0x1) << CAN_TXBAR_AR0_Pos) |
| #define | CAN_TXBAR_AR1_Pos 1 |
| (CAN_TXBAR) Add Request 1 | |
| #define | CAN_TXBAR_AR1 (_U_(0x1) << CAN_TXBAR_AR1_Pos) |
| #define | CAN_TXBAR_AR2_Pos 2 |
| (CAN_TXBAR) Add Request 2 | |
| #define | CAN_TXBAR_AR2 (_U_(0x1) << CAN_TXBAR_AR2_Pos) |
| #define | CAN_TXBAR_AR3_Pos 3 |
| (CAN_TXBAR) Add Request 3 | |
| #define | CAN_TXBAR_AR3 (_U_(0x1) << CAN_TXBAR_AR3_Pos) |
| #define | CAN_TXBAR_AR4_Pos 4 |
| (CAN_TXBAR) Add Request 4 | |
| #define | CAN_TXBAR_AR4 (_U_(0x1) << CAN_TXBAR_AR4_Pos) |
| #define | CAN_TXBAR_AR5_Pos 5 |
| (CAN_TXBAR) Add Request 5 | |
| #define | CAN_TXBAR_AR5 (_U_(0x1) << CAN_TXBAR_AR5_Pos) |
| #define | CAN_TXBAR_AR6_Pos 6 |
| (CAN_TXBAR) Add Request 6 | |
| #define | CAN_TXBAR_AR6 (_U_(0x1) << CAN_TXBAR_AR6_Pos) |
| #define | CAN_TXBAR_AR7_Pos 7 |
| (CAN_TXBAR) Add Request 7 | |
| #define | CAN_TXBAR_AR7 (_U_(0x1) << CAN_TXBAR_AR7_Pos) |
| #define | CAN_TXBAR_AR8_Pos 8 |
| (CAN_TXBAR) Add Request 8 | |
| #define | CAN_TXBAR_AR8 (_U_(0x1) << CAN_TXBAR_AR8_Pos) |
| #define | CAN_TXBAR_AR9_Pos 9 |
| (CAN_TXBAR) Add Request 9 | |
| #define | CAN_TXBAR_AR9 (_U_(0x1) << CAN_TXBAR_AR9_Pos) |
| #define | CAN_TXBAR_AR10_Pos 10 |
| (CAN_TXBAR) Add Request 10 | |
| #define | CAN_TXBAR_AR10 (_U_(0x1) << CAN_TXBAR_AR10_Pos) |
| #define | CAN_TXBAR_AR11_Pos 11 |
| (CAN_TXBAR) Add Request 11 | |
| #define | CAN_TXBAR_AR11 (_U_(0x1) << CAN_TXBAR_AR11_Pos) |
| #define | CAN_TXBAR_AR12_Pos 12 |
| (CAN_TXBAR) Add Request 12 | |
| #define | CAN_TXBAR_AR12 (_U_(0x1) << CAN_TXBAR_AR12_Pos) |
| #define | CAN_TXBAR_AR13_Pos 13 |
| (CAN_TXBAR) Add Request 13 | |
| #define | CAN_TXBAR_AR13 (_U_(0x1) << CAN_TXBAR_AR13_Pos) |
| #define | CAN_TXBAR_AR14_Pos 14 |
| (CAN_TXBAR) Add Request 14 | |
| #define | CAN_TXBAR_AR14 (_U_(0x1) << CAN_TXBAR_AR14_Pos) |
| #define | CAN_TXBAR_AR15_Pos 15 |
| (CAN_TXBAR) Add Request 15 | |
| #define | CAN_TXBAR_AR15 (_U_(0x1) << CAN_TXBAR_AR15_Pos) |
| #define | CAN_TXBAR_AR16_Pos 16 |
| (CAN_TXBAR) Add Request 16 | |
| #define | CAN_TXBAR_AR16 (_U_(0x1) << CAN_TXBAR_AR16_Pos) |
| #define | CAN_TXBAR_AR17_Pos 17 |
| (CAN_TXBAR) Add Request 17 | |
| #define | CAN_TXBAR_AR17 (_U_(0x1) << CAN_TXBAR_AR17_Pos) |
| #define | CAN_TXBAR_AR18_Pos 18 |
| (CAN_TXBAR) Add Request 18 | |
| #define | CAN_TXBAR_AR18 (_U_(0x1) << CAN_TXBAR_AR18_Pos) |
| #define | CAN_TXBAR_AR19_Pos 19 |
| (CAN_TXBAR) Add Request 19 | |
| #define | CAN_TXBAR_AR19 (_U_(0x1) << CAN_TXBAR_AR19_Pos) |
| #define | CAN_TXBAR_AR20_Pos 20 |
| (CAN_TXBAR) Add Request 20 | |
| #define | CAN_TXBAR_AR20 (_U_(0x1) << CAN_TXBAR_AR20_Pos) |
| #define | CAN_TXBAR_AR21_Pos 21 |
| (CAN_TXBAR) Add Request 21 | |
| #define | CAN_TXBAR_AR21 (_U_(0x1) << CAN_TXBAR_AR21_Pos) |
| #define | CAN_TXBAR_AR22_Pos 22 |
| (CAN_TXBAR) Add Request 22 | |
| #define | CAN_TXBAR_AR22 (_U_(0x1) << CAN_TXBAR_AR22_Pos) |
| #define | CAN_TXBAR_AR23_Pos 23 |
| (CAN_TXBAR) Add Request 23 | |
| #define | CAN_TXBAR_AR23 (_U_(0x1) << CAN_TXBAR_AR23_Pos) |
| #define | CAN_TXBAR_AR24_Pos 24 |
| (CAN_TXBAR) Add Request 24 | |
| #define | CAN_TXBAR_AR24 (_U_(0x1) << CAN_TXBAR_AR24_Pos) |
| #define | CAN_TXBAR_AR25_Pos 25 |
| (CAN_TXBAR) Add Request 25 | |
| #define | CAN_TXBAR_AR25 (_U_(0x1) << CAN_TXBAR_AR25_Pos) |
| #define | CAN_TXBAR_AR26_Pos 26 |
| (CAN_TXBAR) Add Request 26 | |
| #define | CAN_TXBAR_AR26 (_U_(0x1) << CAN_TXBAR_AR26_Pos) |
| #define | CAN_TXBAR_AR27_Pos 27 |
| (CAN_TXBAR) Add Request 27 | |
| #define | CAN_TXBAR_AR27 (_U_(0x1) << CAN_TXBAR_AR27_Pos) |
| #define | CAN_TXBAR_AR28_Pos 28 |
| (CAN_TXBAR) Add Request 28 | |
| #define | CAN_TXBAR_AR28 (_U_(0x1) << CAN_TXBAR_AR28_Pos) |
| #define | CAN_TXBAR_AR29_Pos 29 |
| (CAN_TXBAR) Add Request 29 | |
| #define | CAN_TXBAR_AR29 (_U_(0x1) << CAN_TXBAR_AR29_Pos) |
| #define | CAN_TXBAR_AR30_Pos 30 |
| (CAN_TXBAR) Add Request 30 | |
| #define | CAN_TXBAR_AR30 (_U_(0x1) << CAN_TXBAR_AR30_Pos) |
| #define | CAN_TXBAR_AR31_Pos 31 |
| (CAN_TXBAR) Add Request 31 | |
| #define | CAN_TXBAR_AR31 (_U_(0x1) << CAN_TXBAR_AR31_Pos) |
| #define | CAN_TXBAR_MASK _U_(0xFFFFFFFF) |
| (CAN_TXBAR) MASK Register | |
| #define | CAN_TXBCR_OFFSET 0xD4 |
| (CAN_TXBCR offset) Tx Buffer Cancellation Request | |
| #define | CAN_TXBCR_RESETVALUE _U_(0x00000000) |
| (CAN_TXBCR reset_value) Tx Buffer Cancellation Request | |
| #define | CAN_TXBCR_CR0_Pos 0 |
| (CAN_TXBCR) Cancellation Request 0 | |
| #define | CAN_TXBCR_CR0 (_U_(0x1) << CAN_TXBCR_CR0_Pos) |
| #define | CAN_TXBCR_CR1_Pos 1 |
| (CAN_TXBCR) Cancellation Request 1 | |
| #define | CAN_TXBCR_CR1 (_U_(0x1) << CAN_TXBCR_CR1_Pos) |
| #define | CAN_TXBCR_CR2_Pos 2 |
| (CAN_TXBCR) Cancellation Request 2 | |
| #define | CAN_TXBCR_CR2 (_U_(0x1) << CAN_TXBCR_CR2_Pos) |
| #define | CAN_TXBCR_CR3_Pos 3 |
| (CAN_TXBCR) Cancellation Request 3 | |
| #define | CAN_TXBCR_CR3 (_U_(0x1) << CAN_TXBCR_CR3_Pos) |
| #define | CAN_TXBCR_CR4_Pos 4 |
| (CAN_TXBCR) Cancellation Request 4 | |
| #define | CAN_TXBCR_CR4 (_U_(0x1) << CAN_TXBCR_CR4_Pos) |
| #define | CAN_TXBCR_CR5_Pos 5 |
| (CAN_TXBCR) Cancellation Request 5 | |
| #define | CAN_TXBCR_CR5 (_U_(0x1) << CAN_TXBCR_CR5_Pos) |
| #define | CAN_TXBCR_CR6_Pos 6 |
| (CAN_TXBCR) Cancellation Request 6 | |
| #define | CAN_TXBCR_CR6 (_U_(0x1) << CAN_TXBCR_CR6_Pos) |
| #define | CAN_TXBCR_CR7_Pos 7 |
| (CAN_TXBCR) Cancellation Request 7 | |
| #define | CAN_TXBCR_CR7 (_U_(0x1) << CAN_TXBCR_CR7_Pos) |
| #define | CAN_TXBCR_CR8_Pos 8 |
| (CAN_TXBCR) Cancellation Request 8 | |
| #define | CAN_TXBCR_CR8 (_U_(0x1) << CAN_TXBCR_CR8_Pos) |
| #define | CAN_TXBCR_CR9_Pos 9 |
| (CAN_TXBCR) Cancellation Request 9 | |
| #define | CAN_TXBCR_CR9 (_U_(0x1) << CAN_TXBCR_CR9_Pos) |
| #define | CAN_TXBCR_CR10_Pos 10 |
| (CAN_TXBCR) Cancellation Request 10 | |
| #define | CAN_TXBCR_CR10 (_U_(0x1) << CAN_TXBCR_CR10_Pos) |
| #define | CAN_TXBCR_CR11_Pos 11 |
| (CAN_TXBCR) Cancellation Request 11 | |
| #define | CAN_TXBCR_CR11 (_U_(0x1) << CAN_TXBCR_CR11_Pos) |
| #define | CAN_TXBCR_CR12_Pos 12 |
| (CAN_TXBCR) Cancellation Request 12 | |
| #define | CAN_TXBCR_CR12 (_U_(0x1) << CAN_TXBCR_CR12_Pos) |
| #define | CAN_TXBCR_CR13_Pos 13 |
| (CAN_TXBCR) Cancellation Request 13 | |
| #define | CAN_TXBCR_CR13 (_U_(0x1) << CAN_TXBCR_CR13_Pos) |
| #define | CAN_TXBCR_CR14_Pos 14 |
| (CAN_TXBCR) Cancellation Request 14 | |
| #define | CAN_TXBCR_CR14 (_U_(0x1) << CAN_TXBCR_CR14_Pos) |
| #define | CAN_TXBCR_CR15_Pos 15 |
| (CAN_TXBCR) Cancellation Request 15 | |
| #define | CAN_TXBCR_CR15 (_U_(0x1) << CAN_TXBCR_CR15_Pos) |
| #define | CAN_TXBCR_CR16_Pos 16 |
| (CAN_TXBCR) Cancellation Request 16 | |
| #define | CAN_TXBCR_CR16 (_U_(0x1) << CAN_TXBCR_CR16_Pos) |
| #define | CAN_TXBCR_CR17_Pos 17 |
| (CAN_TXBCR) Cancellation Request 17 | |
| #define | CAN_TXBCR_CR17 (_U_(0x1) << CAN_TXBCR_CR17_Pos) |
| #define | CAN_TXBCR_CR18_Pos 18 |
| (CAN_TXBCR) Cancellation Request 18 | |
| #define | CAN_TXBCR_CR18 (_U_(0x1) << CAN_TXBCR_CR18_Pos) |
| #define | CAN_TXBCR_CR19_Pos 19 |
| (CAN_TXBCR) Cancellation Request 19 | |
| #define | CAN_TXBCR_CR19 (_U_(0x1) << CAN_TXBCR_CR19_Pos) |
| #define | CAN_TXBCR_CR20_Pos 20 |
| (CAN_TXBCR) Cancellation Request 20 | |
| #define | CAN_TXBCR_CR20 (_U_(0x1) << CAN_TXBCR_CR20_Pos) |
| #define | CAN_TXBCR_CR21_Pos 21 |
| (CAN_TXBCR) Cancellation Request 21 | |
| #define | CAN_TXBCR_CR21 (_U_(0x1) << CAN_TXBCR_CR21_Pos) |
| #define | CAN_TXBCR_CR22_Pos 22 |
| (CAN_TXBCR) Cancellation Request 22 | |
| #define | CAN_TXBCR_CR22 (_U_(0x1) << CAN_TXBCR_CR22_Pos) |
| #define | CAN_TXBCR_CR23_Pos 23 |
| (CAN_TXBCR) Cancellation Request 23 | |
| #define | CAN_TXBCR_CR23 (_U_(0x1) << CAN_TXBCR_CR23_Pos) |
| #define | CAN_TXBCR_CR24_Pos 24 |
| (CAN_TXBCR) Cancellation Request 24 | |
| #define | CAN_TXBCR_CR24 (_U_(0x1) << CAN_TXBCR_CR24_Pos) |
| #define | CAN_TXBCR_CR25_Pos 25 |
| (CAN_TXBCR) Cancellation Request 25 | |
| #define | CAN_TXBCR_CR25 (_U_(0x1) << CAN_TXBCR_CR25_Pos) |
| #define | CAN_TXBCR_CR26_Pos 26 |
| (CAN_TXBCR) Cancellation Request 26 | |
| #define | CAN_TXBCR_CR26 (_U_(0x1) << CAN_TXBCR_CR26_Pos) |
| #define | CAN_TXBCR_CR27_Pos 27 |
| (CAN_TXBCR) Cancellation Request 27 | |
| #define | CAN_TXBCR_CR27 (_U_(0x1) << CAN_TXBCR_CR27_Pos) |
| #define | CAN_TXBCR_CR28_Pos 28 |
| (CAN_TXBCR) Cancellation Request 28 | |
| #define | CAN_TXBCR_CR28 (_U_(0x1) << CAN_TXBCR_CR28_Pos) |
| #define | CAN_TXBCR_CR29_Pos 29 |
| (CAN_TXBCR) Cancellation Request 29 | |
| #define | CAN_TXBCR_CR29 (_U_(0x1) << CAN_TXBCR_CR29_Pos) |
| #define | CAN_TXBCR_CR30_Pos 30 |
| (CAN_TXBCR) Cancellation Request 30 | |
| #define | CAN_TXBCR_CR30 (_U_(0x1) << CAN_TXBCR_CR30_Pos) |
| #define | CAN_TXBCR_CR31_Pos 31 |
| (CAN_TXBCR) Cancellation Request 31 | |
| #define | CAN_TXBCR_CR31 (_U_(0x1) << CAN_TXBCR_CR31_Pos) |
| #define | CAN_TXBCR_MASK _U_(0xFFFFFFFF) |
| (CAN_TXBCR) MASK Register | |
| #define | CAN_TXBTO_OFFSET 0xD8 |
| (CAN_TXBTO offset) Tx Buffer Transmission Occurred | |
| #define | CAN_TXBTO_RESETVALUE _U_(0x00000000) |
| (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred | |
| #define | CAN_TXBTO_TO0_Pos 0 |
| (CAN_TXBTO) Transmission Occurred 0 | |
| #define | CAN_TXBTO_TO0 (_U_(0x1) << CAN_TXBTO_TO0_Pos) |
| #define | CAN_TXBTO_TO1_Pos 1 |
| (CAN_TXBTO) Transmission Occurred 1 | |
| #define | CAN_TXBTO_TO1 (_U_(0x1) << CAN_TXBTO_TO1_Pos) |
| #define | CAN_TXBTO_TO2_Pos 2 |
| (CAN_TXBTO) Transmission Occurred 2 | |
| #define | CAN_TXBTO_TO2 (_U_(0x1) << CAN_TXBTO_TO2_Pos) |
| #define | CAN_TXBTO_TO3_Pos 3 |
| (CAN_TXBTO) Transmission Occurred 3 | |
| #define | CAN_TXBTO_TO3 (_U_(0x1) << CAN_TXBTO_TO3_Pos) |
| #define | CAN_TXBTO_TO4_Pos 4 |
| (CAN_TXBTO) Transmission Occurred 4 | |
| #define | CAN_TXBTO_TO4 (_U_(0x1) << CAN_TXBTO_TO4_Pos) |
| #define | CAN_TXBTO_TO5_Pos 5 |
| (CAN_TXBTO) Transmission Occurred 5 | |
| #define | CAN_TXBTO_TO5 (_U_(0x1) << CAN_TXBTO_TO5_Pos) |
| #define | CAN_TXBTO_TO6_Pos 6 |
| (CAN_TXBTO) Transmission Occurred 6 | |
| #define | CAN_TXBTO_TO6 (_U_(0x1) << CAN_TXBTO_TO6_Pos) |
| #define | CAN_TXBTO_TO7_Pos 7 |
| (CAN_TXBTO) Transmission Occurred 7 | |
| #define | CAN_TXBTO_TO7 (_U_(0x1) << CAN_TXBTO_TO7_Pos) |
| #define | CAN_TXBTO_TO8_Pos 8 |
| (CAN_TXBTO) Transmission Occurred 8 | |
| #define | CAN_TXBTO_TO8 (_U_(0x1) << CAN_TXBTO_TO8_Pos) |
| #define | CAN_TXBTO_TO9_Pos 9 |
| (CAN_TXBTO) Transmission Occurred 9 | |
| #define | CAN_TXBTO_TO9 (_U_(0x1) << CAN_TXBTO_TO9_Pos) |
| #define | CAN_TXBTO_TO10_Pos 10 |
| (CAN_TXBTO) Transmission Occurred 10 | |
| #define | CAN_TXBTO_TO10 (_U_(0x1) << CAN_TXBTO_TO10_Pos) |
| #define | CAN_TXBTO_TO11_Pos 11 |
| (CAN_TXBTO) Transmission Occurred 11 | |
| #define | CAN_TXBTO_TO11 (_U_(0x1) << CAN_TXBTO_TO11_Pos) |
| #define | CAN_TXBTO_TO12_Pos 12 |
| (CAN_TXBTO) Transmission Occurred 12 | |
| #define | CAN_TXBTO_TO12 (_U_(0x1) << CAN_TXBTO_TO12_Pos) |
| #define | CAN_TXBTO_TO13_Pos 13 |
| (CAN_TXBTO) Transmission Occurred 13 | |
| #define | CAN_TXBTO_TO13 (_U_(0x1) << CAN_TXBTO_TO13_Pos) |
| #define | CAN_TXBTO_TO14_Pos 14 |
| (CAN_TXBTO) Transmission Occurred 14 | |
| #define | CAN_TXBTO_TO14 (_U_(0x1) << CAN_TXBTO_TO14_Pos) |
| #define | CAN_TXBTO_TO15_Pos 15 |
| (CAN_TXBTO) Transmission Occurred 15 | |
| #define | CAN_TXBTO_TO15 (_U_(0x1) << CAN_TXBTO_TO15_Pos) |
| #define | CAN_TXBTO_TO16_Pos 16 |
| (CAN_TXBTO) Transmission Occurred 16 | |
| #define | CAN_TXBTO_TO16 (_U_(0x1) << CAN_TXBTO_TO16_Pos) |
| #define | CAN_TXBTO_TO17_Pos 17 |
| (CAN_TXBTO) Transmission Occurred 17 | |
| #define | CAN_TXBTO_TO17 (_U_(0x1) << CAN_TXBTO_TO17_Pos) |
| #define | CAN_TXBTO_TO18_Pos 18 |
| (CAN_TXBTO) Transmission Occurred 18 | |
| #define | CAN_TXBTO_TO18 (_U_(0x1) << CAN_TXBTO_TO18_Pos) |
| #define | CAN_TXBTO_TO19_Pos 19 |
| (CAN_TXBTO) Transmission Occurred 19 | |
| #define | CAN_TXBTO_TO19 (_U_(0x1) << CAN_TXBTO_TO19_Pos) |
| #define | CAN_TXBTO_TO20_Pos 20 |
| (CAN_TXBTO) Transmission Occurred 20 | |
| #define | CAN_TXBTO_TO20 (_U_(0x1) << CAN_TXBTO_TO20_Pos) |
| #define | CAN_TXBTO_TO21_Pos 21 |
| (CAN_TXBTO) Transmission Occurred 21 | |
| #define | CAN_TXBTO_TO21 (_U_(0x1) << CAN_TXBTO_TO21_Pos) |
| #define | CAN_TXBTO_TO22_Pos 22 |
| (CAN_TXBTO) Transmission Occurred 22 | |
| #define | CAN_TXBTO_TO22 (_U_(0x1) << CAN_TXBTO_TO22_Pos) |
| #define | CAN_TXBTO_TO23_Pos 23 |
| (CAN_TXBTO) Transmission Occurred 23 | |
| #define | CAN_TXBTO_TO23 (_U_(0x1) << CAN_TXBTO_TO23_Pos) |
| #define | CAN_TXBTO_TO24_Pos 24 |
| (CAN_TXBTO) Transmission Occurred 24 | |
| #define | CAN_TXBTO_TO24 (_U_(0x1) << CAN_TXBTO_TO24_Pos) |
| #define | CAN_TXBTO_TO25_Pos 25 |
| (CAN_TXBTO) Transmission Occurred 25 | |
| #define | CAN_TXBTO_TO25 (_U_(0x1) << CAN_TXBTO_TO25_Pos) |
| #define | CAN_TXBTO_TO26_Pos 26 |
| (CAN_TXBTO) Transmission Occurred 26 | |
| #define | CAN_TXBTO_TO26 (_U_(0x1) << CAN_TXBTO_TO26_Pos) |
| #define | CAN_TXBTO_TO27_Pos 27 |
| (CAN_TXBTO) Transmission Occurred 27 | |
| #define | CAN_TXBTO_TO27 (_U_(0x1) << CAN_TXBTO_TO27_Pos) |
| #define | CAN_TXBTO_TO28_Pos 28 |
| (CAN_TXBTO) Transmission Occurred 28 | |
| #define | CAN_TXBTO_TO28 (_U_(0x1) << CAN_TXBTO_TO28_Pos) |
| #define | CAN_TXBTO_TO29_Pos 29 |
| (CAN_TXBTO) Transmission Occurred 29 | |
| #define | CAN_TXBTO_TO29 (_U_(0x1) << CAN_TXBTO_TO29_Pos) |
| #define | CAN_TXBTO_TO30_Pos 30 |
| (CAN_TXBTO) Transmission Occurred 30 | |
| #define | CAN_TXBTO_TO30 (_U_(0x1) << CAN_TXBTO_TO30_Pos) |
| #define | CAN_TXBTO_TO31_Pos 31 |
| (CAN_TXBTO) Transmission Occurred 31 | |
| #define | CAN_TXBTO_TO31 (_U_(0x1) << CAN_TXBTO_TO31_Pos) |
| #define | CAN_TXBTO_MASK _U_(0xFFFFFFFF) |
| (CAN_TXBTO) MASK Register | |
| #define | CAN_TXBCF_OFFSET 0xDC |
| (CAN_TXBCF offset) Tx Buffer Cancellation Finished | |
| #define | CAN_TXBCF_RESETVALUE _U_(0x00000000) |
| (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished | |
| #define | CAN_TXBCF_CF0_Pos 0 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 0 | |
| #define | CAN_TXBCF_CF0 (_U_(0x1) << CAN_TXBCF_CF0_Pos) |
| #define | CAN_TXBCF_CF1_Pos 1 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 1 | |
| #define | CAN_TXBCF_CF1 (_U_(0x1) << CAN_TXBCF_CF1_Pos) |
| #define | CAN_TXBCF_CF2_Pos 2 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 2 | |
| #define | CAN_TXBCF_CF2 (_U_(0x1) << CAN_TXBCF_CF2_Pos) |
| #define | CAN_TXBCF_CF3_Pos 3 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 3 | |
| #define | CAN_TXBCF_CF3 (_U_(0x1) << CAN_TXBCF_CF3_Pos) |
| #define | CAN_TXBCF_CF4_Pos 4 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 4 | |
| #define | CAN_TXBCF_CF4 (_U_(0x1) << CAN_TXBCF_CF4_Pos) |
| #define | CAN_TXBCF_CF5_Pos 5 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 5 | |
| #define | CAN_TXBCF_CF5 (_U_(0x1) << CAN_TXBCF_CF5_Pos) |
| #define | CAN_TXBCF_CF6_Pos 6 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 6 | |
| #define | CAN_TXBCF_CF6 (_U_(0x1) << CAN_TXBCF_CF6_Pos) |
| #define | CAN_TXBCF_CF7_Pos 7 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 7 | |
| #define | CAN_TXBCF_CF7 (_U_(0x1) << CAN_TXBCF_CF7_Pos) |
| #define | CAN_TXBCF_CF8_Pos 8 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 8 | |
| #define | CAN_TXBCF_CF8 (_U_(0x1) << CAN_TXBCF_CF8_Pos) |
| #define | CAN_TXBCF_CF9_Pos 9 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 9 | |
| #define | CAN_TXBCF_CF9 (_U_(0x1) << CAN_TXBCF_CF9_Pos) |
| #define | CAN_TXBCF_CF10_Pos 10 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 10 | |
| #define | CAN_TXBCF_CF10 (_U_(0x1) << CAN_TXBCF_CF10_Pos) |
| #define | CAN_TXBCF_CF11_Pos 11 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 11 | |
| #define | CAN_TXBCF_CF11 (_U_(0x1) << CAN_TXBCF_CF11_Pos) |
| #define | CAN_TXBCF_CF12_Pos 12 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 12 | |
| #define | CAN_TXBCF_CF12 (_U_(0x1) << CAN_TXBCF_CF12_Pos) |
| #define | CAN_TXBCF_CF13_Pos 13 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 13 | |
| #define | CAN_TXBCF_CF13 (_U_(0x1) << CAN_TXBCF_CF13_Pos) |
| #define | CAN_TXBCF_CF14_Pos 14 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 14 | |
| #define | CAN_TXBCF_CF14 (_U_(0x1) << CAN_TXBCF_CF14_Pos) |
| #define | CAN_TXBCF_CF15_Pos 15 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 15 | |
| #define | CAN_TXBCF_CF15 (_U_(0x1) << CAN_TXBCF_CF15_Pos) |
| #define | CAN_TXBCF_CF16_Pos 16 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 16 | |
| #define | CAN_TXBCF_CF16 (_U_(0x1) << CAN_TXBCF_CF16_Pos) |
| #define | CAN_TXBCF_CF17_Pos 17 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 17 | |
| #define | CAN_TXBCF_CF17 (_U_(0x1) << CAN_TXBCF_CF17_Pos) |
| #define | CAN_TXBCF_CF18_Pos 18 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 18 | |
| #define | CAN_TXBCF_CF18 (_U_(0x1) << CAN_TXBCF_CF18_Pos) |
| #define | CAN_TXBCF_CF19_Pos 19 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 19 | |
| #define | CAN_TXBCF_CF19 (_U_(0x1) << CAN_TXBCF_CF19_Pos) |
| #define | CAN_TXBCF_CF20_Pos 20 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 20 | |
| #define | CAN_TXBCF_CF20 (_U_(0x1) << CAN_TXBCF_CF20_Pos) |
| #define | CAN_TXBCF_CF21_Pos 21 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 21 | |
| #define | CAN_TXBCF_CF21 (_U_(0x1) << CAN_TXBCF_CF21_Pos) |
| #define | CAN_TXBCF_CF22_Pos 22 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 22 | |
| #define | CAN_TXBCF_CF22 (_U_(0x1) << CAN_TXBCF_CF22_Pos) |
| #define | CAN_TXBCF_CF23_Pos 23 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 23 | |
| #define | CAN_TXBCF_CF23 (_U_(0x1) << CAN_TXBCF_CF23_Pos) |
| #define | CAN_TXBCF_CF24_Pos 24 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 24 | |
| #define | CAN_TXBCF_CF24 (_U_(0x1) << CAN_TXBCF_CF24_Pos) |
| #define | CAN_TXBCF_CF25_Pos 25 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 25 | |
| #define | CAN_TXBCF_CF25 (_U_(0x1) << CAN_TXBCF_CF25_Pos) |
| #define | CAN_TXBCF_CF26_Pos 26 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 26 | |
| #define | CAN_TXBCF_CF26 (_U_(0x1) << CAN_TXBCF_CF26_Pos) |
| #define | CAN_TXBCF_CF27_Pos 27 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 27 | |
| #define | CAN_TXBCF_CF27 (_U_(0x1) << CAN_TXBCF_CF27_Pos) |
| #define | CAN_TXBCF_CF28_Pos 28 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 28 | |
| #define | CAN_TXBCF_CF28 (_U_(0x1) << CAN_TXBCF_CF28_Pos) |
| #define | CAN_TXBCF_CF29_Pos 29 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 29 | |
| #define | CAN_TXBCF_CF29 (_U_(0x1) << CAN_TXBCF_CF29_Pos) |
| #define | CAN_TXBCF_CF30_Pos 30 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 30 | |
| #define | CAN_TXBCF_CF30 (_U_(0x1) << CAN_TXBCF_CF30_Pos) |
| #define | CAN_TXBCF_CF31_Pos 31 |
| (CAN_TXBCF) Tx Buffer Cancellation Finished 31 | |
| #define | CAN_TXBCF_CF31 (_U_(0x1) << CAN_TXBCF_CF31_Pos) |
| #define | CAN_TXBCF_MASK _U_(0xFFFFFFFF) |
| (CAN_TXBCF) MASK Register | |
| #define | CAN_TXBTIE_OFFSET 0xE0 |
| (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable | |
| #define | CAN_TXBTIE_RESETVALUE _U_(0x00000000) |
| (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable | |
| #define | CAN_TXBTIE_TIE0_Pos 0 |
| (CAN_TXBTIE) Transmission Interrupt Enable 0 | |
| #define | CAN_TXBTIE_TIE0 (_U_(0x1) << CAN_TXBTIE_TIE0_Pos) |
| #define | CAN_TXBTIE_TIE1_Pos 1 |
| (CAN_TXBTIE) Transmission Interrupt Enable 1 | |
| #define | CAN_TXBTIE_TIE1 (_U_(0x1) << CAN_TXBTIE_TIE1_Pos) |
| #define | CAN_TXBTIE_TIE2_Pos 2 |
| (CAN_TXBTIE) Transmission Interrupt Enable 2 | |
| #define | CAN_TXBTIE_TIE2 (_U_(0x1) << CAN_TXBTIE_TIE2_Pos) |
| #define | CAN_TXBTIE_TIE3_Pos 3 |
| (CAN_TXBTIE) Transmission Interrupt Enable 3 | |
| #define | CAN_TXBTIE_TIE3 (_U_(0x1) << CAN_TXBTIE_TIE3_Pos) |
| #define | CAN_TXBTIE_TIE4_Pos 4 |
| (CAN_TXBTIE) Transmission Interrupt Enable 4 | |
| #define | CAN_TXBTIE_TIE4 (_U_(0x1) << CAN_TXBTIE_TIE4_Pos) |
| #define | CAN_TXBTIE_TIE5_Pos 5 |
| (CAN_TXBTIE) Transmission Interrupt Enable 5 | |
| #define | CAN_TXBTIE_TIE5 (_U_(0x1) << CAN_TXBTIE_TIE5_Pos) |
| #define | CAN_TXBTIE_TIE6_Pos 6 |
| (CAN_TXBTIE) Transmission Interrupt Enable 6 | |
| #define | CAN_TXBTIE_TIE6 (_U_(0x1) << CAN_TXBTIE_TIE6_Pos) |
| #define | CAN_TXBTIE_TIE7_Pos 7 |
| (CAN_TXBTIE) Transmission Interrupt Enable 7 | |
| #define | CAN_TXBTIE_TIE7 (_U_(0x1) << CAN_TXBTIE_TIE7_Pos) |
| #define | CAN_TXBTIE_TIE8_Pos 8 |
| (CAN_TXBTIE) Transmission Interrupt Enable 8 | |
| #define | CAN_TXBTIE_TIE8 (_U_(0x1) << CAN_TXBTIE_TIE8_Pos) |
| #define | CAN_TXBTIE_TIE9_Pos 9 |
| (CAN_TXBTIE) Transmission Interrupt Enable 9 | |
| #define | CAN_TXBTIE_TIE9 (_U_(0x1) << CAN_TXBTIE_TIE9_Pos) |
| #define | CAN_TXBTIE_TIE10_Pos 10 |
| (CAN_TXBTIE) Transmission Interrupt Enable 10 | |
| #define | CAN_TXBTIE_TIE10 (_U_(0x1) << CAN_TXBTIE_TIE10_Pos) |
| #define | CAN_TXBTIE_TIE11_Pos 11 |
| (CAN_TXBTIE) Transmission Interrupt Enable 11 | |
| #define | CAN_TXBTIE_TIE11 (_U_(0x1) << CAN_TXBTIE_TIE11_Pos) |
| #define | CAN_TXBTIE_TIE12_Pos 12 |
| (CAN_TXBTIE) Transmission Interrupt Enable 12 | |
| #define | CAN_TXBTIE_TIE12 (_U_(0x1) << CAN_TXBTIE_TIE12_Pos) |
| #define | CAN_TXBTIE_TIE13_Pos 13 |
| (CAN_TXBTIE) Transmission Interrupt Enable 13 | |
| #define | CAN_TXBTIE_TIE13 (_U_(0x1) << CAN_TXBTIE_TIE13_Pos) |
| #define | CAN_TXBTIE_TIE14_Pos 14 |
| (CAN_TXBTIE) Transmission Interrupt Enable 14 | |
| #define | CAN_TXBTIE_TIE14 (_U_(0x1) << CAN_TXBTIE_TIE14_Pos) |
| #define | CAN_TXBTIE_TIE15_Pos 15 |
| (CAN_TXBTIE) Transmission Interrupt Enable 15 | |
| #define | CAN_TXBTIE_TIE15 (_U_(0x1) << CAN_TXBTIE_TIE15_Pos) |
| #define | CAN_TXBTIE_TIE16_Pos 16 |
| (CAN_TXBTIE) Transmission Interrupt Enable 16 | |
| #define | CAN_TXBTIE_TIE16 (_U_(0x1) << CAN_TXBTIE_TIE16_Pos) |
| #define | CAN_TXBTIE_TIE17_Pos 17 |
| (CAN_TXBTIE) Transmission Interrupt Enable 17 | |
| #define | CAN_TXBTIE_TIE17 (_U_(0x1) << CAN_TXBTIE_TIE17_Pos) |
| #define | CAN_TXBTIE_TIE18_Pos 18 |
| (CAN_TXBTIE) Transmission Interrupt Enable 18 | |
| #define | CAN_TXBTIE_TIE18 (_U_(0x1) << CAN_TXBTIE_TIE18_Pos) |
| #define | CAN_TXBTIE_TIE19_Pos 19 |
| (CAN_TXBTIE) Transmission Interrupt Enable 19 | |
| #define | CAN_TXBTIE_TIE19 (_U_(0x1) << CAN_TXBTIE_TIE19_Pos) |
| #define | CAN_TXBTIE_TIE20_Pos 20 |
| (CAN_TXBTIE) Transmission Interrupt Enable 20 | |
| #define | CAN_TXBTIE_TIE20 (_U_(0x1) << CAN_TXBTIE_TIE20_Pos) |
| #define | CAN_TXBTIE_TIE21_Pos 21 |
| (CAN_TXBTIE) Transmission Interrupt Enable 21 | |
| #define | CAN_TXBTIE_TIE21 (_U_(0x1) << CAN_TXBTIE_TIE21_Pos) |
| #define | CAN_TXBTIE_TIE22_Pos 22 |
| (CAN_TXBTIE) Transmission Interrupt Enable 22 | |
| #define | CAN_TXBTIE_TIE22 (_U_(0x1) << CAN_TXBTIE_TIE22_Pos) |
| #define | CAN_TXBTIE_TIE23_Pos 23 |
| (CAN_TXBTIE) Transmission Interrupt Enable 23 | |
| #define | CAN_TXBTIE_TIE23 (_U_(0x1) << CAN_TXBTIE_TIE23_Pos) |
| #define | CAN_TXBTIE_TIE24_Pos 24 |
| (CAN_TXBTIE) Transmission Interrupt Enable 24 | |
| #define | CAN_TXBTIE_TIE24 (_U_(0x1) << CAN_TXBTIE_TIE24_Pos) |
| #define | CAN_TXBTIE_TIE25_Pos 25 |
| (CAN_TXBTIE) Transmission Interrupt Enable 25 | |
| #define | CAN_TXBTIE_TIE25 (_U_(0x1) << CAN_TXBTIE_TIE25_Pos) |
| #define | CAN_TXBTIE_TIE26_Pos 26 |
| (CAN_TXBTIE) Transmission Interrupt Enable 26 | |
| #define | CAN_TXBTIE_TIE26 (_U_(0x1) << CAN_TXBTIE_TIE26_Pos) |
| #define | CAN_TXBTIE_TIE27_Pos 27 |
| (CAN_TXBTIE) Transmission Interrupt Enable 27 | |
| #define | CAN_TXBTIE_TIE27 (_U_(0x1) << CAN_TXBTIE_TIE27_Pos) |
| #define | CAN_TXBTIE_TIE28_Pos 28 |
| (CAN_TXBTIE) Transmission Interrupt Enable 28 | |
| #define | CAN_TXBTIE_TIE28 (_U_(0x1) << CAN_TXBTIE_TIE28_Pos) |
| #define | CAN_TXBTIE_TIE29_Pos 29 |
| (CAN_TXBTIE) Transmission Interrupt Enable 29 | |
| #define | CAN_TXBTIE_TIE29 (_U_(0x1) << CAN_TXBTIE_TIE29_Pos) |
| #define | CAN_TXBTIE_TIE30_Pos 30 |
| (CAN_TXBTIE) Transmission Interrupt Enable 30 | |
| #define | CAN_TXBTIE_TIE30 (_U_(0x1) << CAN_TXBTIE_TIE30_Pos) |
| #define | CAN_TXBTIE_TIE31_Pos 31 |
| (CAN_TXBTIE) Transmission Interrupt Enable 31 | |
| #define | CAN_TXBTIE_TIE31 (_U_(0x1) << CAN_TXBTIE_TIE31_Pos) |
| #define | CAN_TXBTIE_MASK _U_(0xFFFFFFFF) |
| (CAN_TXBTIE) MASK Register | |
| #define | CAN_TXBCIE_OFFSET 0xE4 |
| (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable | |
| #define | CAN_TXBCIE_RESETVALUE _U_(0x00000000) |
| (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable | |
| #define | CAN_TXBCIE_CFIE0_Pos 0 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 | |
| #define | CAN_TXBCIE_CFIE0 (_U_(0x1) << CAN_TXBCIE_CFIE0_Pos) |
| #define | CAN_TXBCIE_CFIE1_Pos 1 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 | |
| #define | CAN_TXBCIE_CFIE1 (_U_(0x1) << CAN_TXBCIE_CFIE1_Pos) |
| #define | CAN_TXBCIE_CFIE2_Pos 2 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 | |
| #define | CAN_TXBCIE_CFIE2 (_U_(0x1) << CAN_TXBCIE_CFIE2_Pos) |
| #define | CAN_TXBCIE_CFIE3_Pos 3 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 | |
| #define | CAN_TXBCIE_CFIE3 (_U_(0x1) << CAN_TXBCIE_CFIE3_Pos) |
| #define | CAN_TXBCIE_CFIE4_Pos 4 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 | |
| #define | CAN_TXBCIE_CFIE4 (_U_(0x1) << CAN_TXBCIE_CFIE4_Pos) |
| #define | CAN_TXBCIE_CFIE5_Pos 5 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 | |
| #define | CAN_TXBCIE_CFIE5 (_U_(0x1) << CAN_TXBCIE_CFIE5_Pos) |
| #define | CAN_TXBCIE_CFIE6_Pos 6 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 | |
| #define | CAN_TXBCIE_CFIE6 (_U_(0x1) << CAN_TXBCIE_CFIE6_Pos) |
| #define | CAN_TXBCIE_CFIE7_Pos 7 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 | |
| #define | CAN_TXBCIE_CFIE7 (_U_(0x1) << CAN_TXBCIE_CFIE7_Pos) |
| #define | CAN_TXBCIE_CFIE8_Pos 8 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 | |
| #define | CAN_TXBCIE_CFIE8 (_U_(0x1) << CAN_TXBCIE_CFIE8_Pos) |
| #define | CAN_TXBCIE_CFIE9_Pos 9 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 | |
| #define | CAN_TXBCIE_CFIE9 (_U_(0x1) << CAN_TXBCIE_CFIE9_Pos) |
| #define | CAN_TXBCIE_CFIE10_Pos 10 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 | |
| #define | CAN_TXBCIE_CFIE10 (_U_(0x1) << CAN_TXBCIE_CFIE10_Pos) |
| #define | CAN_TXBCIE_CFIE11_Pos 11 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 | |
| #define | CAN_TXBCIE_CFIE11 (_U_(0x1) << CAN_TXBCIE_CFIE11_Pos) |
| #define | CAN_TXBCIE_CFIE12_Pos 12 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 | |
| #define | CAN_TXBCIE_CFIE12 (_U_(0x1) << CAN_TXBCIE_CFIE12_Pos) |
| #define | CAN_TXBCIE_CFIE13_Pos 13 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 | |
| #define | CAN_TXBCIE_CFIE13 (_U_(0x1) << CAN_TXBCIE_CFIE13_Pos) |
| #define | CAN_TXBCIE_CFIE14_Pos 14 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 | |
| #define | CAN_TXBCIE_CFIE14 (_U_(0x1) << CAN_TXBCIE_CFIE14_Pos) |
| #define | CAN_TXBCIE_CFIE15_Pos 15 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 | |
| #define | CAN_TXBCIE_CFIE15 (_U_(0x1) << CAN_TXBCIE_CFIE15_Pos) |
| #define | CAN_TXBCIE_CFIE16_Pos 16 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 | |
| #define | CAN_TXBCIE_CFIE16 (_U_(0x1) << CAN_TXBCIE_CFIE16_Pos) |
| #define | CAN_TXBCIE_CFIE17_Pos 17 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 | |
| #define | CAN_TXBCIE_CFIE17 (_U_(0x1) << CAN_TXBCIE_CFIE17_Pos) |
| #define | CAN_TXBCIE_CFIE18_Pos 18 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 | |
| #define | CAN_TXBCIE_CFIE18 (_U_(0x1) << CAN_TXBCIE_CFIE18_Pos) |
| #define | CAN_TXBCIE_CFIE19_Pos 19 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 | |
| #define | CAN_TXBCIE_CFIE19 (_U_(0x1) << CAN_TXBCIE_CFIE19_Pos) |
| #define | CAN_TXBCIE_CFIE20_Pos 20 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 | |
| #define | CAN_TXBCIE_CFIE20 (_U_(0x1) << CAN_TXBCIE_CFIE20_Pos) |
| #define | CAN_TXBCIE_CFIE21_Pos 21 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 | |
| #define | CAN_TXBCIE_CFIE21 (_U_(0x1) << CAN_TXBCIE_CFIE21_Pos) |
| #define | CAN_TXBCIE_CFIE22_Pos 22 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 | |
| #define | CAN_TXBCIE_CFIE22 (_U_(0x1) << CAN_TXBCIE_CFIE22_Pos) |
| #define | CAN_TXBCIE_CFIE23_Pos 23 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 | |
| #define | CAN_TXBCIE_CFIE23 (_U_(0x1) << CAN_TXBCIE_CFIE23_Pos) |
| #define | CAN_TXBCIE_CFIE24_Pos 24 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 | |
| #define | CAN_TXBCIE_CFIE24 (_U_(0x1) << CAN_TXBCIE_CFIE24_Pos) |
| #define | CAN_TXBCIE_CFIE25_Pos 25 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 | |
| #define | CAN_TXBCIE_CFIE25 (_U_(0x1) << CAN_TXBCIE_CFIE25_Pos) |
| #define | CAN_TXBCIE_CFIE26_Pos 26 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 | |
| #define | CAN_TXBCIE_CFIE26 (_U_(0x1) << CAN_TXBCIE_CFIE26_Pos) |
| #define | CAN_TXBCIE_CFIE27_Pos 27 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 | |
| #define | CAN_TXBCIE_CFIE27 (_U_(0x1) << CAN_TXBCIE_CFIE27_Pos) |
| #define | CAN_TXBCIE_CFIE28_Pos 28 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 | |
| #define | CAN_TXBCIE_CFIE28 (_U_(0x1) << CAN_TXBCIE_CFIE28_Pos) |
| #define | CAN_TXBCIE_CFIE29_Pos 29 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 | |
| #define | CAN_TXBCIE_CFIE29 (_U_(0x1) << CAN_TXBCIE_CFIE29_Pos) |
| #define | CAN_TXBCIE_CFIE30_Pos 30 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 | |
| #define | CAN_TXBCIE_CFIE30 (_U_(0x1) << CAN_TXBCIE_CFIE30_Pos) |
| #define | CAN_TXBCIE_CFIE31_Pos 31 |
| (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 | |
| #define | CAN_TXBCIE_CFIE31 (_U_(0x1) << CAN_TXBCIE_CFIE31_Pos) |
| #define | CAN_TXBCIE_MASK _U_(0xFFFFFFFF) |
| (CAN_TXBCIE) MASK Register | |
| #define | CAN_TXEFC_OFFSET 0xF0 |
| (CAN_TXEFC offset) Tx Event FIFO Configuration | |
| #define | CAN_TXEFC_RESETVALUE _U_(0x00000000) |
| (CAN_TXEFC reset_value) Tx Event FIFO Configuration | |
| #define | CAN_TXEFC_EFSA_Pos 0 |
| (CAN_TXEFC) Event FIFO Start Address | |
| #define | CAN_TXEFC_EFSA_Msk (_U_(0xFFFF) << CAN_TXEFC_EFSA_Pos) |
| #define | CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos)) |
| #define | CAN_TXEFC_EFS_Pos 16 |
| (CAN_TXEFC) Event FIFO Size | |
| #define | CAN_TXEFC_EFS_Msk (_U_(0x3F) << CAN_TXEFC_EFS_Pos) |
| #define | CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos)) |
| #define | CAN_TXEFC_EFWM_Pos 24 |
| (CAN_TXEFC) Event FIFO Watermark | |
| #define | CAN_TXEFC_EFWM_Msk (_U_(0x3F) << CAN_TXEFC_EFWM_Pos) |
| #define | CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos)) |
| #define | CAN_TXEFC_MASK _U_(0x3F3FFFFF) |
| (CAN_TXEFC) MASK Register | |
| #define | CAN_TXEFS_OFFSET 0xF4 |
| (CAN_TXEFS offset) Tx Event FIFO Status | |
| #define | CAN_TXEFS_RESETVALUE _U_(0x00000000) |
| (CAN_TXEFS reset_value) Tx Event FIFO Status | |
| #define | CAN_TXEFS_EFFL_Pos 0 |
| (CAN_TXEFS) Event FIFO Fill Level | |
| #define | CAN_TXEFS_EFFL_Msk (_U_(0x3F) << CAN_TXEFS_EFFL_Pos) |
| #define | CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos)) |
| #define | CAN_TXEFS_EFGI_Pos 8 |
| (CAN_TXEFS) Event FIFO Get Index | |
| #define | CAN_TXEFS_EFGI_Msk (_U_(0x1F) << CAN_TXEFS_EFGI_Pos) |
| #define | CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos)) |
| #define | CAN_TXEFS_EFPI_Pos 16 |
| (CAN_TXEFS) Event FIFO Put Index | |
| #define | CAN_TXEFS_EFPI_Msk (_U_(0x1F) << CAN_TXEFS_EFPI_Pos) |
| #define | CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos)) |
| #define | CAN_TXEFS_EFF_Pos 24 |
| (CAN_TXEFS) Event FIFO Full | |
| #define | CAN_TXEFS_EFF (_U_(0x1) << CAN_TXEFS_EFF_Pos) |
| #define | CAN_TXEFS_TEFL_Pos 25 |
| (CAN_TXEFS) Tx Event FIFO Element Lost | |
| #define | CAN_TXEFS_TEFL (_U_(0x1) << CAN_TXEFS_TEFL_Pos) |
| #define | CAN_TXEFS_MASK _U_(0x031F1F3F) |
| (CAN_TXEFS) MASK Register | |
| #define | CAN_TXEFA_OFFSET 0xF8 |
| (CAN_TXEFA offset) Tx Event FIFO Acknowledge | |
| #define | CAN_TXEFA_RESETVALUE _U_(0x00000000) |
| (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge | |
| #define | CAN_TXEFA_EFAI_Pos 0 |
| (CAN_TXEFA) Event FIFO Acknowledge Index | |
| #define | CAN_TXEFA_EFAI_Msk (_U_(0x1F) << CAN_TXEFA_EFAI_Pos) |
| #define | CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos)) |
| #define | CAN_TXEFA_MASK _U_(0x0000001F) |
| (CAN_TXEFA) MASK Register | |
| #define | CAN_RXBE_0_OFFSET 0x00 |
| (CAN_RXBE_0 offset) Rx Buffer Element 0 | |
| #define | CAN_RXBE_0_RESETVALUE _U_(0x00000000) |
| (CAN_RXBE_0 reset_value) Rx Buffer Element 0 | |
| #define | CAN_RXBE_0_ID_Pos 0 |
| (CAN_RXBE_0) Identifier | |
| #define | CAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) |
| #define | CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos)) |
| #define | CAN_RXBE_0_RTR_Pos 29 |
| (CAN_RXBE_0) Remote Transmission Request | |
| #define | CAN_RXBE_0_RTR (_U_(0x1) << CAN_RXBE_0_RTR_Pos) |
| #define | CAN_RXBE_0_XTD_Pos 30 |
| (CAN_RXBE_0) Extended Identifier | |
| #define | CAN_RXBE_0_XTD (_U_(0x1) << CAN_RXBE_0_XTD_Pos) |
| #define | CAN_RXBE_0_ESI_Pos 31 |
| (CAN_RXBE_0) Error State Indicator | |
| #define | CAN_RXBE_0_ESI (_U_(0x1) << CAN_RXBE_0_ESI_Pos) |
| #define | CAN_RXBE_0_MASK _U_(0xFFFFFFFF) |
| (CAN_RXBE_0) MASK Register | |
| #define | CAN_RXBE_1_OFFSET 0x04 |
| (CAN_RXBE_1 offset) Rx Buffer Element 1 | |
| #define | CAN_RXBE_1_RESETVALUE _U_(0x00000000) |
| (CAN_RXBE_1 reset_value) Rx Buffer Element 1 | |
| #define | CAN_RXBE_1_RXTS_Pos 0 |
| (CAN_RXBE_1) Rx Timestamp | |
| #define | CAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) |
| #define | CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos)) |
| #define | CAN_RXBE_1_DLC_Pos 16 |
| (CAN_RXBE_1) Data Length Code | |
| #define | CAN_RXBE_1_DLC_Msk (_U_(0xF) << CAN_RXBE_1_DLC_Pos) |
| #define | CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos)) |
| #define | CAN_RXBE_1_BRS_Pos 20 |
| (CAN_RXBE_1) Bit Rate Search | |
| #define | CAN_RXBE_1_BRS (_U_(0x1) << CAN_RXBE_1_BRS_Pos) |
| #define | CAN_RXBE_1_FDF_Pos 21 |
| (CAN_RXBE_1) FD Format | |
| #define | CAN_RXBE_1_FDF (_U_(0x1) << CAN_RXBE_1_FDF_Pos) |
| #define | CAN_RXBE_1_FIDX_Pos 24 |
| (CAN_RXBE_1) Filter Index | |
| #define | CAN_RXBE_1_FIDX_Msk (_U_(0x7F) << CAN_RXBE_1_FIDX_Pos) |
| #define | CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos)) |
| #define | CAN_RXBE_1_ANMF_Pos 31 |
| (CAN_RXBE_1) Accepted Non-matching Frame | |
| #define | CAN_RXBE_1_ANMF (_U_(0x1) << CAN_RXBE_1_ANMF_Pos) |
| #define | CAN_RXBE_1_MASK _U_(0xFF3FFFFF) |
| (CAN_RXBE_1) MASK Register | |
| #define | CAN_RXBE_DATA_OFFSET 0x08 |
| (CAN_RXBE_DATA offset) Rx Buffer Element Data | |
| #define | CAN_RXBE_DATA_RESETVALUE _U_(0x00000000) |
| (CAN_RXBE_DATA reset_value) Rx Buffer Element Data | |
| #define | CAN_RXBE_DATA_DB0_Pos 0 |
| (CAN_RXBE_DATA) Data Byte 0 | |
| #define | CAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB0_Pos) |
| #define | CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos)) |
| #define | CAN_RXBE_DATA_DB1_Pos 8 |
| (CAN_RXBE_DATA) Data Byte 1 | |
| #define | CAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB1_Pos) |
| #define | CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos)) |
| #define | CAN_RXBE_DATA_DB2_Pos 16 |
| (CAN_RXBE_DATA) Data Byte 2 | |
| #define | CAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB2_Pos) |
| #define | CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos)) |
| #define | CAN_RXBE_DATA_DB3_Pos 24 |
| (CAN_RXBE_DATA) Data Byte 3 | |
| #define | CAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB3_Pos) |
| #define | CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos)) |
| #define | CAN_RXBE_DATA_MASK _U_(0xFFFFFFFF) |
| (CAN_RXBE_DATA) MASK Register | |
| #define | CAN_RXF0E_0_OFFSET 0x00 |
| (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 | |
| #define | CAN_RXF0E_0_RESETVALUE _U_(0x00000000) |
| (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 | |
| #define | CAN_RXF0E_0_ID_Pos 0 |
| (CAN_RXF0E_0) Identifier | |
| #define | CAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) |
| #define | CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos)) |
| #define | CAN_RXF0E_0_RTR_Pos 29 |
| (CAN_RXF0E_0) Remote Transmission Request | |
| #define | CAN_RXF0E_0_RTR (_U_(0x1) << CAN_RXF0E_0_RTR_Pos) |
| #define | CAN_RXF0E_0_XTD_Pos 30 |
| (CAN_RXF0E_0) Extended Identifier | |
| #define | CAN_RXF0E_0_XTD (_U_(0x1) << CAN_RXF0E_0_XTD_Pos) |
| #define | CAN_RXF0E_0_ESI_Pos 31 |
| (CAN_RXF0E_0) Error State Indicator | |
| #define | CAN_RXF0E_0_ESI (_U_(0x1) << CAN_RXF0E_0_ESI_Pos) |
| #define | CAN_RXF0E_0_MASK _U_(0xFFFFFFFF) |
| (CAN_RXF0E_0) MASK Register | |
| #define | CAN_RXF0E_1_OFFSET 0x04 |
| (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 | |
| #define | CAN_RXF0E_1_RESETVALUE _U_(0x00000000) |
| (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 | |
| #define | CAN_RXF0E_1_RXTS_Pos 0 |
| (CAN_RXF0E_1) Rx Timestamp | |
| #define | CAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) |
| #define | CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos)) |
| #define | CAN_RXF0E_1_DLC_Pos 16 |
| (CAN_RXF0E_1) Data Length Code | |
| #define | CAN_RXF0E_1_DLC_Msk (_U_(0xF) << CAN_RXF0E_1_DLC_Pos) |
| #define | CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos)) |
| #define | CAN_RXF0E_1_BRS_Pos 20 |
| (CAN_RXF0E_1) Bit Rate Search | |
| #define | CAN_RXF0E_1_BRS (_U_(0x1) << CAN_RXF0E_1_BRS_Pos) |
| #define | CAN_RXF0E_1_FDF_Pos 21 |
| (CAN_RXF0E_1) FD Format | |
| #define | CAN_RXF0E_1_FDF (_U_(0x1) << CAN_RXF0E_1_FDF_Pos) |
| #define | CAN_RXF0E_1_FIDX_Pos 24 |
| (CAN_RXF0E_1) Filter Index | |
| #define | CAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF0E_1_FIDX_Pos) |
| #define | CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos)) |
| #define | CAN_RXF0E_1_ANMF_Pos 31 |
| (CAN_RXF0E_1) Accepted Non-matching Frame | |
| #define | CAN_RXF0E_1_ANMF (_U_(0x1) << CAN_RXF0E_1_ANMF_Pos) |
| #define | CAN_RXF0E_1_MASK _U_(0xFF3FFFFF) |
| (CAN_RXF0E_1) MASK Register | |
| #define | CAN_RXF0E_DATA_OFFSET 0x08 |
| (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data | |
| #define | CAN_RXF0E_DATA_RESETVALUE _U_(0x00000000) |
| (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data | |
| #define | CAN_RXF0E_DATA_DB0_Pos 0 |
| (CAN_RXF0E_DATA) Data Byte 0 | |
| #define | CAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) |
| #define | CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos)) |
| #define | CAN_RXF0E_DATA_DB1_Pos 8 |
| (CAN_RXF0E_DATA) Data Byte 1 | |
| #define | CAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) |
| #define | CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos)) |
| #define | CAN_RXF0E_DATA_DB2_Pos 16 |
| (CAN_RXF0E_DATA) Data Byte 2 | |
| #define | CAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) |
| #define | CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos)) |
| #define | CAN_RXF0E_DATA_DB3_Pos 24 |
| (CAN_RXF0E_DATA) Data Byte 3 | |
| #define | CAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) |
| #define | CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos)) |
| #define | CAN_RXF0E_DATA_MASK _U_(0xFFFFFFFF) |
| (CAN_RXF0E_DATA) MASK Register | |
| #define | CAN_RXF1E_0_OFFSET 0x00 |
| (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 | |
| #define | CAN_RXF1E_0_RESETVALUE _U_(0x00000000) |
| (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 | |
| #define | CAN_RXF1E_0_ID_Pos 0 |
| (CAN_RXF1E_0) Identifier | |
| #define | CAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) |
| #define | CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos)) |
| #define | CAN_RXF1E_0_RTR_Pos 29 |
| (CAN_RXF1E_0) Remote Transmission Request | |
| #define | CAN_RXF1E_0_RTR (_U_(0x1) << CAN_RXF1E_0_RTR_Pos) |
| #define | CAN_RXF1E_0_XTD_Pos 30 |
| (CAN_RXF1E_0) Extended Identifier | |
| #define | CAN_RXF1E_0_XTD (_U_(0x1) << CAN_RXF1E_0_XTD_Pos) |
| #define | CAN_RXF1E_0_ESI_Pos 31 |
| (CAN_RXF1E_0) Error State Indicator | |
| #define | CAN_RXF1E_0_ESI (_U_(0x1) << CAN_RXF1E_0_ESI_Pos) |
| #define | CAN_RXF1E_0_MASK _U_(0xFFFFFFFF) |
| (CAN_RXF1E_0) MASK Register | |
| #define | CAN_RXF1E_1_OFFSET 0x04 |
| (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 | |
| #define | CAN_RXF1E_1_RESETVALUE _U_(0x00000000) |
| (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 | |
| #define | CAN_RXF1E_1_RXTS_Pos 0 |
| (CAN_RXF1E_1) Rx Timestamp | |
| #define | CAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) |
| #define | CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos)) |
| #define | CAN_RXF1E_1_DLC_Pos 16 |
| (CAN_RXF1E_1) Data Length Code | |
| #define | CAN_RXF1E_1_DLC_Msk (_U_(0xF) << CAN_RXF1E_1_DLC_Pos) |
| #define | CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos)) |
| #define | CAN_RXF1E_1_BRS_Pos 20 |
| (CAN_RXF1E_1) Bit Rate Search | |
| #define | CAN_RXF1E_1_BRS (_U_(0x1) << CAN_RXF1E_1_BRS_Pos) |
| #define | CAN_RXF1E_1_FDF_Pos 21 |
| (CAN_RXF1E_1) FD Format | |
| #define | CAN_RXF1E_1_FDF (_U_(0x1) << CAN_RXF1E_1_FDF_Pos) |
| #define | CAN_RXF1E_1_FIDX_Pos 24 |
| (CAN_RXF1E_1) Filter Index | |
| #define | CAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF1E_1_FIDX_Pos) |
| #define | CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos)) |
| #define | CAN_RXF1E_1_ANMF_Pos 31 |
| (CAN_RXF1E_1) Accepted Non-matching Frame | |
| #define | CAN_RXF1E_1_ANMF (_U_(0x1) << CAN_RXF1E_1_ANMF_Pos) |
| #define | CAN_RXF1E_1_MASK _U_(0xFF3FFFFF) |
| (CAN_RXF1E_1) MASK Register | |
| #define | CAN_RXF1E_DATA_OFFSET 0x08 |
| (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data | |
| #define | CAN_RXF1E_DATA_RESETVALUE _U_(0x00000000) |
| (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data | |
| #define | CAN_RXF1E_DATA_DB0_Pos 0 |
| (CAN_RXF1E_DATA) Data Byte 0 | |
| #define | CAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) |
| #define | CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos)) |
| #define | CAN_RXF1E_DATA_DB1_Pos 8 |
| (CAN_RXF1E_DATA) Data Byte 1 | |
| #define | CAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) |
| #define | CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos)) |
| #define | CAN_RXF1E_DATA_DB2_Pos 16 |
| (CAN_RXF1E_DATA) Data Byte 2 | |
| #define | CAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) |
| #define | CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos)) |
| #define | CAN_RXF1E_DATA_DB3_Pos 24 |
| (CAN_RXF1E_DATA) Data Byte 3 | |
| #define | CAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) |
| #define | CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos)) |
| #define | CAN_RXF1E_DATA_MASK _U_(0xFFFFFFFF) |
| (CAN_RXF1E_DATA) MASK Register | |
| #define | CAN_SIDFE_0_OFFSET 0x00 |
| (CAN_SIDFE_0 offset) Standard Message ID Filter Element | |
| #define | CAN_SIDFE_0_RESETVALUE _U_(0x00000000) |
| (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element | |
| #define | CAN_SIDFE_0_SFID2_Pos 0 |
| (CAN_SIDFE_0) Standard Filter ID 2 | |
| #define | CAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) |
| #define | CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos)) |
| #define | CAN_SIDFE_0_SFID1_Pos 16 |
| (CAN_SIDFE_0) Standard Filter ID 1 | |
| #define | CAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) |
| #define | CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos)) |
| #define | CAN_SIDFE_0_SFEC_Pos 27 |
| (CAN_SIDFE_0) Standard Filter Element Configuration | |
| #define | CAN_SIDFE_0_SFEC_Msk (_U_(0x7) << CAN_SIDFE_0_SFEC_Pos) |
| #define | CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos)) |
| #define | CAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) |
| (CAN_SIDFE_0) Disable filter element | |
| #define | CAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) |
| (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match | |
| #define | CAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) |
| (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match | |
| #define | CAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) |
| (CAN_SIDFE_0) Reject ID if filter match | |
| #define | CAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) |
| (CAN_SIDFE_0) Set priority if filter match | |
| #define | CAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) |
| (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match | |
| #define | CAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) |
| (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match | |
| #define | CAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) |
| (CAN_SIDFE_0) Store into Rx Buffer | |
| #define | CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) |
| #define | CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) |
| #define | CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) |
| #define | CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) |
| #define | CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) |
| #define | CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) |
| #define | CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) |
| #define | CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) |
| #define | CAN_SIDFE_0_SFT_Pos 30 |
| (CAN_SIDFE_0) Standard Filter Type | |
| #define | CAN_SIDFE_0_SFT_Msk (_U_(0x3) << CAN_SIDFE_0_SFT_Pos) |
| #define | CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos)) |
| #define | CAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) |
| (CAN_SIDFE_0) Range filter from SFID1 to SFID2 | |
| #define | CAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) |
| (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 | |
| #define | CAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) |
| (CAN_SIDFE_0) Classic filter | |
| #define | CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) |
| #define | CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) |
| #define | CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) |
| #define | CAN_SIDFE_0_MASK _U_(0xFFFF07FF) |
| (CAN_SIDFE_0) MASK Register | |
| #define | CAN_TXBE_0_OFFSET 0x00 |
| (CAN_TXBE_0 offset) Tx Buffer Element 0 | |
| #define | CAN_TXBE_0_RESETVALUE _U_(0x00000000) |
| (CAN_TXBE_0 reset_value) Tx Buffer Element 0 | |
| #define | CAN_TXBE_0_ID_Pos 0 |
| (CAN_TXBE_0) Identifier | |
| #define | CAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) |
| #define | CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos)) |
| #define | CAN_TXBE_0_RTR_Pos 29 |
| (CAN_TXBE_0) Remote Transmission Request | |
| #define | CAN_TXBE_0_RTR (_U_(0x1) << CAN_TXBE_0_RTR_Pos) |
| #define | CAN_TXBE_0_XTD_Pos 30 |
| (CAN_TXBE_0) Extended Identifier | |
| #define | CAN_TXBE_0_XTD (_U_(0x1) << CAN_TXBE_0_XTD_Pos) |
| #define | CAN_TXBE_0_ESI_Pos 31 |
| (CAN_TXBE_0) Error State Indicator | |
| #define | CAN_TXBE_0_ESI (_U_(0x1) << CAN_TXBE_0_ESI_Pos) |
| #define | CAN_TXBE_0_MASK _U_(0xFFFFFFFF) |
| (CAN_TXBE_0) MASK Register | |
| #define | CAN_TXBE_1_OFFSET 0x04 |
| (CAN_TXBE_1 offset) Tx Buffer Element 1 | |
| #define | CAN_TXBE_1_RESETVALUE _U_(0x00000000) |
| (CAN_TXBE_1 reset_value) Tx Buffer Element 1 | |
| #define | CAN_TXBE_1_DLC_Pos 16 |
| (CAN_TXBE_1) Identifier | |
| #define | CAN_TXBE_1_DLC_Msk (_U_(0xF) << CAN_TXBE_1_DLC_Pos) |
| #define | CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos)) |
| #define | CAN_TXBE_1_BRS_Pos 20 |
| (CAN_TXBE_1) Bit Rate Search | |
| #define | CAN_TXBE_1_BRS (_U_(0x1) << CAN_TXBE_1_BRS_Pos) |
| #define | CAN_TXBE_1_FDF_Pos 21 |
| (CAN_TXBE_1) FD Format | |
| #define | CAN_TXBE_1_FDF (_U_(0x1) << CAN_TXBE_1_FDF_Pos) |
| #define | CAN_TXBE_1_EFC_Pos 23 |
| (CAN_TXBE_1) Event FIFO Control | |
| #define | CAN_TXBE_1_EFC (_U_(0x1) << CAN_TXBE_1_EFC_Pos) |
| #define | CAN_TXBE_1_MM_Pos 24 |
| (CAN_TXBE_1) Message Marker | |
| #define | CAN_TXBE_1_MM_Msk (_U_(0xFF) << CAN_TXBE_1_MM_Pos) |
| #define | CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos)) |
| #define | CAN_TXBE_1_MASK _U_(0xFFBF0000) |
| (CAN_TXBE_1) MASK Register | |
| #define | CAN_TXBE_DATA_OFFSET 0x08 |
| (CAN_TXBE_DATA offset) Tx Buffer Element Data | |
| #define | CAN_TXBE_DATA_RESETVALUE _U_(0x00000000) |
| (CAN_TXBE_DATA reset_value) Tx Buffer Element Data | |
| #define | CAN_TXBE_DATA_DB0_Pos 0 |
| (CAN_TXBE_DATA) Data Byte 0 | |
| #define | CAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB0_Pos) |
| #define | CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos)) |
| #define | CAN_TXBE_DATA_DB1_Pos 8 |
| (CAN_TXBE_DATA) Data Byte 1 | |
| #define | CAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB1_Pos) |
| #define | CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos)) |
| #define | CAN_TXBE_DATA_DB2_Pos 16 |
| (CAN_TXBE_DATA) Data Byte 2 | |
| #define | CAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB2_Pos) |
| #define | CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos)) |
| #define | CAN_TXBE_DATA_DB3_Pos 24 |
| (CAN_TXBE_DATA) Data Byte 3 | |
| #define | CAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB3_Pos) |
| #define | CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos)) |
| #define | CAN_TXBE_DATA_MASK _U_(0xFFFFFFFF) |
| (CAN_TXBE_DATA) MASK Register | |
| #define | CAN_TXEFE_0_OFFSET 0x00 |
| (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 | |
| #define | CAN_TXEFE_0_RESETVALUE _U_(0x00000000) |
| (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 | |
| #define | CAN_TXEFE_0_ID_Pos 0 |
| (CAN_TXEFE_0) Identifier | |
| #define | CAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) |
| #define | CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos)) |
| #define | CAN_TXEFE_0_RTR_Pos 29 |
| (CAN_TXEFE_0) Remote Transmission Request | |
| #define | CAN_TXEFE_0_RTR (_U_(0x1) << CAN_TXEFE_0_RTR_Pos) |
| #define | CAN_TXEFE_0_XTD_Pos 30 |
| (CAN_TXEFE_0) Extended Indentifier | |
| #define | CAN_TXEFE_0_XTD (_U_(0x1) << CAN_TXEFE_0_XTD_Pos) |
| #define | CAN_TXEFE_0_ESI_Pos 31 |
| (CAN_TXEFE_0) Error State Indicator | |
| #define | CAN_TXEFE_0_ESI (_U_(0x1) << CAN_TXEFE_0_ESI_Pos) |
| #define | CAN_TXEFE_0_MASK _U_(0xFFFFFFFF) |
| (CAN_TXEFE_0) MASK Register | |
| #define | CAN_TXEFE_1_OFFSET 0x04 |
| (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 | |
| #define | CAN_TXEFE_1_RESETVALUE _U_(0x00000000) |
| (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 | |
| #define | CAN_TXEFE_1_TXTS_Pos 0 |
| (CAN_TXEFE_1) Tx Timestamp | |
| #define | CAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) |
| #define | CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos)) |
| #define | CAN_TXEFE_1_DLC_Pos 16 |
| (CAN_TXEFE_1) Data Length Code | |
| #define | CAN_TXEFE_1_DLC_Msk (_U_(0xF) << CAN_TXEFE_1_DLC_Pos) |
| #define | CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos)) |
| #define | CAN_TXEFE_1_BRS_Pos 20 |
| (CAN_TXEFE_1) Bit Rate Search | |
| #define | CAN_TXEFE_1_BRS (_U_(0x1) << CAN_TXEFE_1_BRS_Pos) |
| #define | CAN_TXEFE_1_FDF_Pos 21 |
| (CAN_TXEFE_1) FD Format | |
| #define | CAN_TXEFE_1_FDF (_U_(0x1) << CAN_TXEFE_1_FDF_Pos) |
| #define | CAN_TXEFE_1_ET_Pos 22 |
| (CAN_TXEFE_1) Event Type | |
| #define | CAN_TXEFE_1_ET_Msk (_U_(0x3) << CAN_TXEFE_1_ET_Pos) |
| #define | CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos)) |
| #define | CAN_TXEFE_1_ET_TXE_Val _U_(0x1) |
| (CAN_TXEFE_1) Tx event | |
| #define | CAN_TXEFE_1_ET_TXC_Val _U_(0x2) |
| (CAN_TXEFE_1) Transmission in spite of cancellation | |
| #define | CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) |
| #define | CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) |
| #define | CAN_TXEFE_1_MM_Pos 24 |
| (CAN_TXEFE_1) Message Marker | |
| #define | CAN_TXEFE_1_MM_Msk (_U_(0xFF) << CAN_TXEFE_1_MM_Pos) |
| #define | CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos)) |
| #define | CAN_TXEFE_1_MASK _U_(0xFFFFFFFF) |
| (CAN_TXEFE_1) MASK Register | |
| #define | CAN_XIDFE_0_OFFSET 0x00 |
| (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 | |
| #define | CAN_XIDFE_0_RESETVALUE _U_(0x00000000) |
| (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 | |
| #define | CAN_XIDFE_0_EFID1_Pos 0 |
| (CAN_XIDFE_0) Extended Filter ID 1 | |
| #define | CAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) |
| #define | CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos)) |
| #define | CAN_XIDFE_0_EFEC_Pos 29 |
| (CAN_XIDFE_0) Extended Filter Element Configuration | |
| #define | CAN_XIDFE_0_EFEC_Msk (_U_(0x7) << CAN_XIDFE_0_EFEC_Pos) |
| #define | CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos)) |
| #define | CAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) |
| (CAN_XIDFE_0) Disable filter element | |
| #define | CAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) |
| (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match | |
| #define | CAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) |
| (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match | |
| #define | CAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) |
| (CAN_XIDFE_0) Reject ID if filter match | |
| #define | CAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) |
| (CAN_XIDFE_0) Set priority if filter match | |
| #define | CAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) |
| (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match | |
| #define | CAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) |
| (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match | |
| #define | CAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) |
| (CAN_XIDFE_0) Store into Rx Buffer | |
| #define | CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) |
| #define | CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) |
| #define | CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) |
| #define | CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) |
| #define | CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) |
| #define | CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) |
| #define | CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) |
| #define | CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) |
| #define | CAN_XIDFE_0_MASK _U_(0xFFFFFFFF) |
| (CAN_XIDFE_0) MASK Register | |
| #define | CAN_XIDFE_1_OFFSET 0x04 |
| (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 | |
| #define | CAN_XIDFE_1_RESETVALUE _U_(0x00000000) |
| (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 | |
| #define | CAN_XIDFE_1_EFID2_Pos 0 |
| (CAN_XIDFE_1) Extended Filter ID 2 | |
| #define | CAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) |
| #define | CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos)) |
| #define | CAN_XIDFE_1_EFT_Pos 30 |
| (CAN_XIDFE_1) Extended Filter Type | |
| #define | CAN_XIDFE_1_EFT_Msk (_U_(0x3) << CAN_XIDFE_1_EFT_Pos) |
| #define | CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos)) |
| #define | CAN_XIDFE_1_EFT_RANGEM_Val _U_(0x0) |
| (CAN_XIDFE_1) Range filter from EFID1 to EFID2 | |
| #define | CAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) |
| (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 | |
| #define | CAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) |
| (CAN_XIDFE_1) Classic filter | |
| #define | CAN_XIDFE_1_EFT_RANGE_Val _U_(0x3) |
| (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask | |
| #define | CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) |
| #define | CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) |
| #define | CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) |
| #define | CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) |
| #define | CAN_XIDFE_1_MASK _U_(0xDFFFFFFF) |
| (CAN_XIDFE_1) MASK Register | |
| #define | SECTION_CAN_MRAM_RXBE |
| #define | SECTION_CAN_MRAM_RXF0E |
| #define | SECTION_CAN_MRAM_RXF1E |
| #define | SECTION_CAN_MRAM_SIDFE |
| #define | SECTION_CAN_MRAM_TXBE |
| #define | SECTION_CAN_MRAM_TXEFE |
| #define | SECTION_CAN_MRAM_XIFDE |
Component description for CAN.
Copyright (c) 2019 Microchip Technology Inc.
\asf_license_start
Definition in file can.h.
1.8.20