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470 lines
47 KiB
C
470 lines
47 KiB
C
4 years ago
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/**
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* \brief Component description for TC
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2019-11-25T06:52:33Z */
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#ifndef _SAMD21_TC_COMPONENT_H_
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#define _SAMD21_TC_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR TC */
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/* ************************************************************************** */
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/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
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#define TC_CTRLA_RESETVALUE _U_(0x00) /**< (TC_CTRLA) Control A Reset Value */
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#define TC_CTRLA_SWRST_Pos _U_(0) /**< (TC_CTRLA) Software Reset Position */
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#define TC_CTRLA_SWRST_Msk (_U_(0x1) << TC_CTRLA_SWRST_Pos) /**< (TC_CTRLA) Software Reset Mask */
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#define TC_CTRLA_SWRST(value) (TC_CTRLA_SWRST_Msk & ((value) << TC_CTRLA_SWRST_Pos))
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#define TC_CTRLA_ENABLE_Pos _U_(1) /**< (TC_CTRLA) Enable Position */
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#define TC_CTRLA_ENABLE_Msk (_U_(0x1) << TC_CTRLA_ENABLE_Pos) /**< (TC_CTRLA) Enable Mask */
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#define TC_CTRLA_ENABLE(value) (TC_CTRLA_ENABLE_Msk & ((value) << TC_CTRLA_ENABLE_Pos))
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#define TC_CTRLA_MODE_Pos _U_(2) /**< (TC_CTRLA) TC Mode Position */
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#define TC_CTRLA_MODE_Msk (_U_(0x3) << TC_CTRLA_MODE_Pos) /**< (TC_CTRLA) TC Mode Mask */
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#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
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#define TC_CTRLA_MODE_COUNT16_Val _U_(0x0) /**< (TC_CTRLA) Counter in 16-bit mode */
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#define TC_CTRLA_MODE_COUNT8_Val _U_(0x1) /**< (TC_CTRLA) Counter in 8-bit mode */
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#define TC_CTRLA_MODE_COUNT32_Val _U_(0x2) /**< (TC_CTRLA) Counter in 32-bit mode */
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#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos) /**< (TC_CTRLA) Counter in 16-bit mode Position */
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#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos) /**< (TC_CTRLA) Counter in 8-bit mode Position */
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#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos) /**< (TC_CTRLA) Counter in 32-bit mode Position */
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#define TC_CTRLA_WAVEGEN_Pos _U_(5) /**< (TC_CTRLA) Waveform Generation Operation Position */
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#define TC_CTRLA_WAVEGEN_Msk (_U_(0x3) << TC_CTRLA_WAVEGEN_Pos) /**< (TC_CTRLA) Waveform Generation Operation Mask */
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#define TC_CTRLA_WAVEGEN(value) (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))
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#define TC_CTRLA_WAVEGEN_NFRQ_Val _U_(0x0) /**< (TC_CTRLA) */
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#define TC_CTRLA_WAVEGEN_MFRQ_Val _U_(0x1) /**< (TC_CTRLA) */
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#define TC_CTRLA_WAVEGEN_NPWM_Val _U_(0x2) /**< (TC_CTRLA) */
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#define TC_CTRLA_WAVEGEN_MPWM_Val _U_(0x3) /**< (TC_CTRLA) */
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#define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos) /**< (TC_CTRLA) Position */
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#define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos) /**< (TC_CTRLA) Position */
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#define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos) /**< (TC_CTRLA) Position */
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#define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos) /**< (TC_CTRLA) Position */
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#define TC_CTRLA_PRESCALER_Pos _U_(8) /**< (TC_CTRLA) Prescaler Position */
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#define TC_CTRLA_PRESCALER_Msk (_U_(0x7) << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler Mask */
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#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
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#define TC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< (TC_CTRLA) Prescaler: GCLK_TC */
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#define TC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< (TC_CTRLA) Prescaler: GCLK_TC/2 */
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#define TC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< (TC_CTRLA) Prescaler: GCLK_TC/4 */
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#define TC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< (TC_CTRLA) Prescaler: GCLK_TC/8 */
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#define TC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< (TC_CTRLA) Prescaler: GCLK_TC/16 */
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#define TC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< (TC_CTRLA) Prescaler: GCLK_TC/64 */
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#define TC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< (TC_CTRLA) Prescaler: GCLK_TC/256 */
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#define TC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< (TC_CTRLA) Prescaler: GCLK_TC/1024 */
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#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC Position */
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#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/2 Position */
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#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/4 Position */
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#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/8 Position */
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#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/16 Position */
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#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/64 Position */
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#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/256 Position */
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#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/1024 Position */
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#define TC_CTRLA_RUNSTDBY_Pos _U_(11) /**< (TC_CTRLA) Run in Standby Position */
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#define TC_CTRLA_RUNSTDBY_Msk (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos) /**< (TC_CTRLA) Run in Standby Mask */
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#define TC_CTRLA_RUNSTDBY(value) (TC_CTRLA_RUNSTDBY_Msk & ((value) << TC_CTRLA_RUNSTDBY_Pos))
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#define TC_CTRLA_PRESCSYNC_Pos _U_(12) /**< (TC_CTRLA) Prescaler and Counter Synchronization Position */
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#define TC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos) /**< (TC_CTRLA) Prescaler and Counter Synchronization Mask */
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#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
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#define TC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< (TC_CTRLA) Reload or reset the counter on next generic clock */
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#define TC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< (TC_CTRLA) Reload or reset the counter on next prescaler clock */
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#define TC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
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#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) /**< (TC_CTRLA) Reload or reset the counter on next generic clock Position */
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#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) /**< (TC_CTRLA) Reload or reset the counter on next prescaler clock Position */
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#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) /**< (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter Position */
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#define TC_CTRLA_Msk _U_(0x3F6F) /**< (TC_CTRLA) Register Mask */
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/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
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#define TC_READREQ_RESETVALUE _U_(0x00) /**< (TC_READREQ) Read Request Reset Value */
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#define TC_READREQ_ADDR_Pos _U_(0) /**< (TC_READREQ) Address Position */
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#define TC_READREQ_ADDR_Msk (_U_(0x1F) << TC_READREQ_ADDR_Pos) /**< (TC_READREQ) Address Mask */
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#define TC_READREQ_ADDR(value) (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))
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#define TC_READREQ_RCONT_Pos _U_(14) /**< (TC_READREQ) Read Continuously Position */
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#define TC_READREQ_RCONT_Msk (_U_(0x1) << TC_READREQ_RCONT_Pos) /**< (TC_READREQ) Read Continuously Mask */
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#define TC_READREQ_RCONT(value) (TC_READREQ_RCONT_Msk & ((value) << TC_READREQ_RCONT_Pos))
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#define TC_READREQ_RREQ_Pos _U_(15) /**< (TC_READREQ) Read Request Position */
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#define TC_READREQ_RREQ_Msk (_U_(0x1) << TC_READREQ_RREQ_Pos) /**< (TC_READREQ) Read Request Mask */
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#define TC_READREQ_RREQ(value) (TC_READREQ_RREQ_Msk & ((value) << TC_READREQ_RREQ_Pos))
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#define TC_READREQ_Msk _U_(0xC01F) /**< (TC_READREQ) Register Mask */
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/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
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#define TC_CTRLBCLR_RESETVALUE _U_(0x02) /**< (TC_CTRLBCLR) Control B Clear Reset Value */
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#define TC_CTRLBCLR_DIR_Pos _U_(0) /**< (TC_CTRLBCLR) Counter Direction Position */
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#define TC_CTRLBCLR_DIR_Msk (_U_(0x1) << TC_CTRLBCLR_DIR_Pos) /**< (TC_CTRLBCLR) Counter Direction Mask */
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#define TC_CTRLBCLR_DIR(value) (TC_CTRLBCLR_DIR_Msk & ((value) << TC_CTRLBCLR_DIR_Pos))
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#define TC_CTRLBCLR_ONESHOT_Pos _U_(2) /**< (TC_CTRLBCLR) One-Shot Position */
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#define TC_CTRLBCLR_ONESHOT_Msk (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos) /**< (TC_CTRLBCLR) One-Shot Mask */
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#define TC_CTRLBCLR_ONESHOT(value) (TC_CTRLBCLR_ONESHOT_Msk & ((value) << TC_CTRLBCLR_ONESHOT_Pos))
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#define TC_CTRLBCLR_CMD_Pos _U_(6) /**< (TC_CTRLBCLR) Command Position */
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#define TC_CTRLBCLR_CMD_Msk (_U_(0x3) << TC_CTRLBCLR_CMD_Pos) /**< (TC_CTRLBCLR) Command Mask */
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#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
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#define TC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< (TC_CTRLBCLR) No action */
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#define TC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< (TC_CTRLBCLR) Force a start, restart or retrigger */
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#define TC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< (TC_CTRLBCLR) Force a stop */
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#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos) /**< (TC_CTRLBCLR) No action Position */
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#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) /**< (TC_CTRLBCLR) Force a start, restart or retrigger Position */
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#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos) /**< (TC_CTRLBCLR) Force a stop Position */
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#define TC_CTRLBCLR_Msk _U_(0xC5) /**< (TC_CTRLBCLR) Register Mask */
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/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
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#define TC_CTRLBSET_RESETVALUE _U_(0x00) /**< (TC_CTRLBSET) Control B Set Reset Value */
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#define TC_CTRLBSET_DIR_Pos _U_(0) /**< (TC_CTRLBSET) Counter Direction Position */
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#define TC_CTRLBSET_DIR_Msk (_U_(0x1) << TC_CTRLBSET_DIR_Pos) /**< (TC_CTRLBSET) Counter Direction Mask */
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#define TC_CTRLBSET_DIR(value) (TC_CTRLBSET_DIR_Msk & ((value) << TC_CTRLBSET_DIR_Pos))
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#define TC_CTRLBSET_ONESHOT_Pos _U_(2) /**< (TC_CTRLBSET) One-Shot Position */
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#define TC_CTRLBSET_ONESHOT_Msk (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos) /**< (TC_CTRLBSET) One-Shot Mask */
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#define TC_CTRLBSET_ONESHOT(value) (TC_CTRLBSET_ONESHOT_Msk & ((value) << TC_CTRLBSET_ONESHOT_Pos))
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#define TC_CTRLBSET_CMD_Pos _U_(6) /**< (TC_CTRLBSET) Command Position */
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#define TC_CTRLBSET_CMD_Msk (_U_(0x3) << TC_CTRLBSET_CMD_Pos) /**< (TC_CTRLBSET) Command Mask */
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#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
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#define TC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< (TC_CTRLBSET) No action */
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#define TC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< (TC_CTRLBSET) Force a start, restart or retrigger */
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#define TC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< (TC_CTRLBSET) Force a stop */
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#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos) /**< (TC_CTRLBSET) No action Position */
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#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) /**< (TC_CTRLBSET) Force a start, restart or retrigger Position */
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#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos) /**< (TC_CTRLBSET) Force a stop Position */
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#define TC_CTRLBSET_Msk _U_(0xC5) /**< (TC_CTRLBSET) Register Mask */
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/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
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#define TC_CTRLC_RESETVALUE _U_(0x00) /**< (TC_CTRLC) Control C Reset Value */
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#define TC_CTRLC_INVEN0_Pos _U_(0) /**< (TC_CTRLC) Output Waveform 0 Invert Enable Position */
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#define TC_CTRLC_INVEN0_Msk (_U_(0x1) << TC_CTRLC_INVEN0_Pos) /**< (TC_CTRLC) Output Waveform 0 Invert Enable Mask */
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#define TC_CTRLC_INVEN0(value) (TC_CTRLC_INVEN0_Msk & ((value) << TC_CTRLC_INVEN0_Pos))
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#define TC_CTRLC_INVEN1_Pos _U_(1) /**< (TC_CTRLC) Output Waveform 1 Invert Enable Position */
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#define TC_CTRLC_INVEN1_Msk (_U_(0x1) << TC_CTRLC_INVEN1_Pos) /**< (TC_CTRLC) Output Waveform 1 Invert Enable Mask */
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#define TC_CTRLC_INVEN1(value) (TC_CTRLC_INVEN1_Msk & ((value) << TC_CTRLC_INVEN1_Pos))
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#define TC_CTRLC_CPTEN0_Pos _U_(4) /**< (TC_CTRLC) Capture Channel 0 Enable Position */
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#define TC_CTRLC_CPTEN0_Msk (_U_(0x1) << TC_CTRLC_CPTEN0_Pos) /**< (TC_CTRLC) Capture Channel 0 Enable Mask */
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#define TC_CTRLC_CPTEN0(value) (TC_CTRLC_CPTEN0_Msk & ((value) << TC_CTRLC_CPTEN0_Pos))
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#define TC_CTRLC_CPTEN1_Pos _U_(5) /**< (TC_CTRLC) Capture Channel 1 Enable Position */
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#define TC_CTRLC_CPTEN1_Msk (_U_(0x1) << TC_CTRLC_CPTEN1_Pos) /**< (TC_CTRLC) Capture Channel 1 Enable Mask */
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#define TC_CTRLC_CPTEN1(value) (TC_CTRLC_CPTEN1_Msk & ((value) << TC_CTRLC_CPTEN1_Pos))
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#define TC_CTRLC_Msk _U_(0x33) /**< (TC_CTRLC) Register Mask */
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#define TC_CTRLC_INVEN_Pos _U_(0) /**< (TC_CTRLC Position) Output Waveform x Invert Enable */
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#define TC_CTRLC_INVEN_Msk (_U_(0x3) << TC_CTRLC_INVEN_Pos) /**< (TC_CTRLC Mask) INVEN */
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#define TC_CTRLC_INVEN(value) (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos))
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#define TC_CTRLC_CPTEN_Pos _U_(4) /**< (TC_CTRLC Position) Capture Channel x Enable */
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#define TC_CTRLC_CPTEN_Msk (_U_(0x3) << TC_CTRLC_CPTEN_Pos) /**< (TC_CTRLC Mask) CPTEN */
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#define TC_CTRLC_CPTEN(value) (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos))
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/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
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#define TC_DBGCTRL_RESETVALUE _U_(0x00) /**< (TC_DBGCTRL) Debug Control Reset Value */
|
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|
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|
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#define TC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (TC_DBGCTRL) Debug Run Mode Position */
|
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|
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#define TC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos) /**< (TC_DBGCTRL) Debug Run Mode Mask */
|
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|
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#define TC_DBGCTRL_DBGRUN(value) (TC_DBGCTRL_DBGRUN_Msk & ((value) << TC_DBGCTRL_DBGRUN_Pos))
|
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|
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#define TC_DBGCTRL_Msk _U_(0x01) /**< (TC_DBGCTRL) Register Mask */
|
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|
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|
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|
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/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
|
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|
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#define TC_EVCTRL_RESETVALUE _U_(0x00) /**< (TC_EVCTRL) Event Control Reset Value */
|
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|
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|
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#define TC_EVCTRL_EVACT_Pos _U_(0) /**< (TC_EVCTRL) Event Action Position */
|
||
|
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#define TC_EVCTRL_EVACT_Msk (_U_(0x7) << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Event Action Mask */
|
||
|
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#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
|
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|
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#define TC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< (TC_EVCTRL) Event action disabled */
|
||
|
|
#define TC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< (TC_EVCTRL) Start, restart or retrigger TC on event */
|
||
|
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#define TC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< (TC_EVCTRL) Count on event */
|
||
|
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#define TC_EVCTRL_EVACT_START_Val _U_(0x3) /**< (TC_EVCTRL) Start TC on event */
|
||
|
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#define TC_EVCTRL_EVACT_PPW_Val _U_(0x5) /**< (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */
|
||
|
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#define TC_EVCTRL_EVACT_PWP_Val _U_(0x6) /**< (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */
|
||
|
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#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Event action disabled Position */
|
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|
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#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Start, restart or retrigger TC on event Position */
|
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|
|
#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Count on event Position */
|
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|
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#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Start TC on event Position */
|
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|
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#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Period captured in CC0, pulse width in CC1 Position */
|
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#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Period captured in CC1, pulse width in CC0 Position */
|
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#define TC_EVCTRL_TCINV_Pos _U_(4) /**< (TC_EVCTRL) TC Inverted Event Input Position */
|
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|
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#define TC_EVCTRL_TCINV_Msk (_U_(0x1) << TC_EVCTRL_TCINV_Pos) /**< (TC_EVCTRL) TC Inverted Event Input Mask */
|
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|
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#define TC_EVCTRL_TCINV(value) (TC_EVCTRL_TCINV_Msk & ((value) << TC_EVCTRL_TCINV_Pos))
|
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|
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#define TC_EVCTRL_TCEI_Pos _U_(5) /**< (TC_EVCTRL) TC Event Input Position */
|
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|
|
#define TC_EVCTRL_TCEI_Msk (_U_(0x1) << TC_EVCTRL_TCEI_Pos) /**< (TC_EVCTRL) TC Event Input Mask */
|
||
|
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#define TC_EVCTRL_TCEI(value) (TC_EVCTRL_TCEI_Msk & ((value) << TC_EVCTRL_TCEI_Pos))
|
||
|
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#define TC_EVCTRL_OVFEO_Pos _U_(8) /**< (TC_EVCTRL) Overflow/Underflow Event Output Enable Position */
|
||
|
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#define TC_EVCTRL_OVFEO_Msk (_U_(0x1) << TC_EVCTRL_OVFEO_Pos) /**< (TC_EVCTRL) Overflow/Underflow Event Output Enable Mask */
|
||
|
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#define TC_EVCTRL_OVFEO(value) (TC_EVCTRL_OVFEO_Msk & ((value) << TC_EVCTRL_OVFEO_Pos))
|
||
|
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#define TC_EVCTRL_MCEO0_Pos _U_(12) /**< (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable Position */
|
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|
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#define TC_EVCTRL_MCEO0_Msk (_U_(0x1) << TC_EVCTRL_MCEO0_Pos) /**< (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable Mask */
|
||
|
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#define TC_EVCTRL_MCEO0(value) (TC_EVCTRL_MCEO0_Msk & ((value) << TC_EVCTRL_MCEO0_Pos))
|
||
|
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#define TC_EVCTRL_MCEO1_Pos _U_(13) /**< (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable Position */
|
||
|
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#define TC_EVCTRL_MCEO1_Msk (_U_(0x1) << TC_EVCTRL_MCEO1_Pos) /**< (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable Mask */
|
||
|
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#define TC_EVCTRL_MCEO1(value) (TC_EVCTRL_MCEO1_Msk & ((value) << TC_EVCTRL_MCEO1_Pos))
|
||
|
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#define TC_EVCTRL_Msk _U_(0x3137) /**< (TC_EVCTRL) Register Mask */
|
||
|
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|
||
|
|
#define TC_EVCTRL_MCEO_Pos _U_(12) /**< (TC_EVCTRL Position) Match or Capture Channel x Event Output Enable */
|
||
|
|
#define TC_EVCTRL_MCEO_Msk (_U_(0x3) << TC_EVCTRL_MCEO_Pos) /**< (TC_EVCTRL Mask) MCEO */
|
||
|
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#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
|
||
|
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|
||
|
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/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
|
||
|
|
#define TC_INTENCLR_RESETVALUE _U_(0x00) /**< (TC_INTENCLR) Interrupt Enable Clear Reset Value */
|
||
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|
||
|
|
#define TC_INTENCLR_OVF_Pos _U_(0) /**< (TC_INTENCLR) Overflow Interrupt Enable Position */
|
||
|
|
#define TC_INTENCLR_OVF_Msk (_U_(0x1) << TC_INTENCLR_OVF_Pos) /**< (TC_INTENCLR) Overflow Interrupt Enable Mask */
|
||
|
|
#define TC_INTENCLR_OVF(value) (TC_INTENCLR_OVF_Msk & ((value) << TC_INTENCLR_OVF_Pos))
|
||
|
|
#define TC_INTENCLR_ERR_Pos _U_(1) /**< (TC_INTENCLR) Error Interrupt Enable Position */
|
||
|
|
#define TC_INTENCLR_ERR_Msk (_U_(0x1) << TC_INTENCLR_ERR_Pos) /**< (TC_INTENCLR) Error Interrupt Enable Mask */
|
||
|
|
#define TC_INTENCLR_ERR(value) (TC_INTENCLR_ERR_Msk & ((value) << TC_INTENCLR_ERR_Pos))
|
||
|
|
#define TC_INTENCLR_SYNCRDY_Pos _U_(3) /**< (TC_INTENCLR) Synchronization Ready Interrupt Enable Position */
|
||
|
|
#define TC_INTENCLR_SYNCRDY_Msk (_U_(0x1) << TC_INTENCLR_SYNCRDY_Pos) /**< (TC_INTENCLR) Synchronization Ready Interrupt Enable Mask */
|
||
|
|
#define TC_INTENCLR_SYNCRDY(value) (TC_INTENCLR_SYNCRDY_Msk & ((value) << TC_INTENCLR_SYNCRDY_Pos))
|
||
|
|
#define TC_INTENCLR_MC0_Pos _U_(4) /**< (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable Position */
|
||
|
|
#define TC_INTENCLR_MC0_Msk (_U_(0x1) << TC_INTENCLR_MC0_Pos) /**< (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable Mask */
|
||
|
|
#define TC_INTENCLR_MC0(value) (TC_INTENCLR_MC0_Msk & ((value) << TC_INTENCLR_MC0_Pos))
|
||
|
|
#define TC_INTENCLR_MC1_Pos _U_(5) /**< (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable Position */
|
||
|
|
#define TC_INTENCLR_MC1_Msk (_U_(0x1) << TC_INTENCLR_MC1_Pos) /**< (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable Mask */
|
||
|
|
#define TC_INTENCLR_MC1(value) (TC_INTENCLR_MC1_Msk & ((value) << TC_INTENCLR_MC1_Pos))
|
||
|
|
#define TC_INTENCLR_Msk _U_(0x3B) /**< (TC_INTENCLR) Register Mask */
|
||
|
|
|
||
|
|
#define TC_INTENCLR_MC_Pos _U_(4) /**< (TC_INTENCLR Position) Match or Capture Channel x Interrupt Enable */
|
||
|
|
#define TC_INTENCLR_MC_Msk (_U_(0x3) << TC_INTENCLR_MC_Pos) /**< (TC_INTENCLR Mask) MC */
|
||
|
|
#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
|
||
|
|
|
||
|
|
/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
|
||
|
|
#define TC_INTENSET_RESETVALUE _U_(0x00) /**< (TC_INTENSET) Interrupt Enable Set Reset Value */
|
||
|
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|
||
|
|
#define TC_INTENSET_OVF_Pos _U_(0) /**< (TC_INTENSET) Overflow Interrupt Enable Position */
|
||
|
|
#define TC_INTENSET_OVF_Msk (_U_(0x1) << TC_INTENSET_OVF_Pos) /**< (TC_INTENSET) Overflow Interrupt Enable Mask */
|
||
|
|
#define TC_INTENSET_OVF(value) (TC_INTENSET_OVF_Msk & ((value) << TC_INTENSET_OVF_Pos))
|
||
|
|
#define TC_INTENSET_ERR_Pos _U_(1) /**< (TC_INTENSET) Error Interrupt Enable Position */
|
||
|
|
#define TC_INTENSET_ERR_Msk (_U_(0x1) << TC_INTENSET_ERR_Pos) /**< (TC_INTENSET) Error Interrupt Enable Mask */
|
||
|
|
#define TC_INTENSET_ERR(value) (TC_INTENSET_ERR_Msk & ((value) << TC_INTENSET_ERR_Pos))
|
||
|
|
#define TC_INTENSET_SYNCRDY_Pos _U_(3) /**< (TC_INTENSET) Synchronization Ready Interrupt Enable Position */
|
||
|
|
#define TC_INTENSET_SYNCRDY_Msk (_U_(0x1) << TC_INTENSET_SYNCRDY_Pos) /**< (TC_INTENSET) Synchronization Ready Interrupt Enable Mask */
|
||
|
|
#define TC_INTENSET_SYNCRDY(value) (TC_INTENSET_SYNCRDY_Msk & ((value) << TC_INTENSET_SYNCRDY_Pos))
|
||
|
|
#define TC_INTENSET_MC0_Pos _U_(4) /**< (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable Position */
|
||
|
|
#define TC_INTENSET_MC0_Msk (_U_(0x1) << TC_INTENSET_MC0_Pos) /**< (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable Mask */
|
||
|
|
#define TC_INTENSET_MC0(value) (TC_INTENSET_MC0_Msk & ((value) << TC_INTENSET_MC0_Pos))
|
||
|
|
#define TC_INTENSET_MC1_Pos _U_(5) /**< (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable Position */
|
||
|
|
#define TC_INTENSET_MC1_Msk (_U_(0x1) << TC_INTENSET_MC1_Pos) /**< (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable Mask */
|
||
|
|
#define TC_INTENSET_MC1(value) (TC_INTENSET_MC1_Msk & ((value) << TC_INTENSET_MC1_Pos))
|
||
|
|
#define TC_INTENSET_Msk _U_(0x3B) /**< (TC_INTENSET) Register Mask */
|
||
|
|
|
||
|
|
#define TC_INTENSET_MC_Pos _U_(4) /**< (TC_INTENSET Position) Match or Capture Channel x Interrupt Enable */
|
||
|
|
#define TC_INTENSET_MC_Msk (_U_(0x3) << TC_INTENSET_MC_Pos) /**< (TC_INTENSET Mask) MC */
|
||
|
|
#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
|
||
|
|
|
||
|
|
/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||
|
|
#define TC_INTFLAG_RESETVALUE _U_(0x00) /**< (TC_INTFLAG) Interrupt Flag Status and Clear Reset Value */
|
||
|
|
|
||
|
|
#define TC_INTFLAG_OVF_Pos _U_(0) /**< (TC_INTFLAG) Overflow Position */
|
||
|
|
#define TC_INTFLAG_OVF_Msk (_U_(0x1) << TC_INTFLAG_OVF_Pos) /**< (TC_INTFLAG) Overflow Mask */
|
||
|
|
#define TC_INTFLAG_OVF(value) (TC_INTFLAG_OVF_Msk & ((value) << TC_INTFLAG_OVF_Pos))
|
||
|
|
#define TC_INTFLAG_ERR_Pos _U_(1) /**< (TC_INTFLAG) Error Position */
|
||
|
|
#define TC_INTFLAG_ERR_Msk (_U_(0x1) << TC_INTFLAG_ERR_Pos) /**< (TC_INTFLAG) Error Mask */
|
||
|
|
#define TC_INTFLAG_ERR(value) (TC_INTFLAG_ERR_Msk & ((value) << TC_INTFLAG_ERR_Pos))
|
||
|
|
#define TC_INTFLAG_SYNCRDY_Pos _U_(3) /**< (TC_INTFLAG) Synchronization Ready Position */
|
||
|
|
#define TC_INTFLAG_SYNCRDY_Msk (_U_(0x1) << TC_INTFLAG_SYNCRDY_Pos) /**< (TC_INTFLAG) Synchronization Ready Mask */
|
||
|
|
#define TC_INTFLAG_SYNCRDY(value) (TC_INTFLAG_SYNCRDY_Msk & ((value) << TC_INTFLAG_SYNCRDY_Pos))
|
||
|
|
#define TC_INTFLAG_MC0_Pos _U_(4) /**< (TC_INTFLAG) Match or Capture Channel 0 Position */
|
||
|
|
#define TC_INTFLAG_MC0_Msk (_U_(0x1) << TC_INTFLAG_MC0_Pos) /**< (TC_INTFLAG) Match or Capture Channel 0 Mask */
|
||
|
|
#define TC_INTFLAG_MC0(value) (TC_INTFLAG_MC0_Msk & ((value) << TC_INTFLAG_MC0_Pos))
|
||
|
|
#define TC_INTFLAG_MC1_Pos _U_(5) /**< (TC_INTFLAG) Match or Capture Channel 1 Position */
|
||
|
|
#define TC_INTFLAG_MC1_Msk (_U_(0x1) << TC_INTFLAG_MC1_Pos) /**< (TC_INTFLAG) Match or Capture Channel 1 Mask */
|
||
|
|
#define TC_INTFLAG_MC1(value) (TC_INTFLAG_MC1_Msk & ((value) << TC_INTFLAG_MC1_Pos))
|
||
|
|
#define TC_INTFLAG_Msk _U_(0x3B) /**< (TC_INTFLAG) Register Mask */
|
||
|
|
|
||
|
|
#define TC_INTFLAG_MC_Pos _U_(4) /**< (TC_INTFLAG Position) Match or Capture Channel x */
|
||
|
|
#define TC_INTFLAG_MC_Msk (_U_(0x3) << TC_INTFLAG_MC_Pos) /**< (TC_INTFLAG Mask) MC */
|
||
|
|
#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
|
||
|
|
|
||
|
|
/* -------- TC_STATUS : (TC Offset: 0x0F) ( R/ 8) Status -------- */
|
||
|
|
#define TC_STATUS_RESETVALUE _U_(0x08) /**< (TC_STATUS) Status Reset Value */
|
||
|
|
|
||
|
|
#define TC_STATUS_STOP_Pos _U_(3) /**< (TC_STATUS) Stop Position */
|
||
|
|
#define TC_STATUS_STOP_Msk (_U_(0x1) << TC_STATUS_STOP_Pos) /**< (TC_STATUS) Stop Mask */
|
||
|
|
#define TC_STATUS_STOP(value) (TC_STATUS_STOP_Msk & ((value) << TC_STATUS_STOP_Pos))
|
||
|
|
#define TC_STATUS_SLAVE_Pos _U_(4) /**< (TC_STATUS) Slave Position */
|
||
|
|
#define TC_STATUS_SLAVE_Msk (_U_(0x1) << TC_STATUS_SLAVE_Pos) /**< (TC_STATUS) Slave Mask */
|
||
|
|
#define TC_STATUS_SLAVE(value) (TC_STATUS_SLAVE_Msk & ((value) << TC_STATUS_SLAVE_Pos))
|
||
|
|
#define TC_STATUS_SYNCBUSY_Pos _U_(7) /**< (TC_STATUS) Synchronization Busy Position */
|
||
|
|
#define TC_STATUS_SYNCBUSY_Msk (_U_(0x1) << TC_STATUS_SYNCBUSY_Pos) /**< (TC_STATUS) Synchronization Busy Mask */
|
||
|
|
#define TC_STATUS_SYNCBUSY(value) (TC_STATUS_SYNCBUSY_Msk & ((value) << TC_STATUS_SYNCBUSY_Pos))
|
||
|
|
#define TC_STATUS_Msk _U_(0x98) /**< (TC_STATUS) Register Mask */
|
||
|
|
|
||
|
|
|
||
|
|
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 Counter Value -------- */
|
||
|
|
#define TC_COUNT8_COUNT_RESETVALUE _U_(0x00) /**< (TC_COUNT8_COUNT) COUNT8 Counter Value Reset Value */
|
||
|
|
|
||
|
|
#define TC_COUNT8_COUNT_COUNT_Pos _U_(0) /**< (TC_COUNT8_COUNT) Counter Value Position */
|
||
|
|
#define TC_COUNT8_COUNT_COUNT_Msk (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos) /**< (TC_COUNT8_COUNT) Counter Value Mask */
|
||
|
|
#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
|
||
|
|
#define TC_COUNT8_COUNT_Msk _U_(0xFF) /**< (TC_COUNT8_COUNT) Register Mask */
|
||
|
|
|
||
|
|
|
||
|
|
/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 Counter Value -------- */
|
||
|
|
#define TC_COUNT16_COUNT_RESETVALUE _U_(0x00) /**< (TC_COUNT16_COUNT) COUNT16 Counter Value Reset Value */
|
||
|
|
|
||
|
|
#define TC_COUNT16_COUNT_COUNT_Pos _U_(0) /**< (TC_COUNT16_COUNT) Count Value Position */
|
||
|
|
#define TC_COUNT16_COUNT_COUNT_Msk (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos) /**< (TC_COUNT16_COUNT) Count Value Mask */
|
||
|
|
#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
|
||
|
|
#define TC_COUNT16_COUNT_Msk _U_(0xFFFF) /**< (TC_COUNT16_COUNT) Register Mask */
|
||
|
|
|
||
|
|
|
||
|
|
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 Counter Value -------- */
|
||
|
|
#define TC_COUNT32_COUNT_RESETVALUE _U_(0x00) /**< (TC_COUNT32_COUNT) COUNT32 Counter Value Reset Value */
|
||
|
|
|
||
|
|
#define TC_COUNT32_COUNT_COUNT_Pos _U_(0) /**< (TC_COUNT32_COUNT) Count Value Position */
|
||
|
|
#define TC_COUNT32_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos) /**< (TC_COUNT32_COUNT) Count Value Mask */
|
||
|
|
#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
|
||
|
|
#define TC_COUNT32_COUNT_Msk _U_(0xFFFFFFFF) /**< (TC_COUNT32_COUNT) Register Mask */
|
||
|
|
|
||
|
|
|
||
|
|
/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 Period Value -------- */
|
||
|
|
#define TC_COUNT8_PER_RESETVALUE _U_(0xFF) /**< (TC_COUNT8_PER) COUNT8 Period Value Reset Value */
|
||
|
|
|
||
|
|
#define TC_COUNT8_PER_PER_Pos _U_(0) /**< (TC_COUNT8_PER) Period Value Position */
|
||
|
|
#define TC_COUNT8_PER_PER_Msk (_U_(0xFF) << TC_COUNT8_PER_PER_Pos) /**< (TC_COUNT8_PER) Period Value Mask */
|
||
|
|
#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
|
||
|
|
#define TC_COUNT8_PER_Msk _U_(0xFF) /**< (TC_COUNT8_PER) Register Mask */
|
||
|
|
|
||
|
|
|
||
|
|
/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 Compare/Capture -------- */
|
||
|
|
#define TC_COUNT8_CC_RESETVALUE _U_(0x00) /**< (TC_COUNT8_CC) COUNT8 Compare/Capture Reset Value */
|
||
|
|
|
||
|
|
#define TC_COUNT8_CC_CC_Pos _U_(0) /**< (TC_COUNT8_CC) Compare/Capture Value Position */
|
||
|
|
#define TC_COUNT8_CC_CC_Msk (_U_(0xFF) << TC_COUNT8_CC_CC_Pos) /**< (TC_COUNT8_CC) Compare/Capture Value Mask */
|
||
|
|
#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
|
||
|
|
#define TC_COUNT8_CC_Msk _U_(0xFF) /**< (TC_COUNT8_CC) Register Mask */
|
||
|
|
|
||
|
|
|
||
|
|
/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 Compare/Capture -------- */
|
||
|
|
#define TC_COUNT16_CC_RESETVALUE _U_(0x00) /**< (TC_COUNT16_CC) COUNT16 Compare/Capture Reset Value */
|
||
|
|
|
||
|
|
#define TC_COUNT16_CC_CC_Pos _U_(0) /**< (TC_COUNT16_CC) Compare/Capture Value Position */
|
||
|
|
#define TC_COUNT16_CC_CC_Msk (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos) /**< (TC_COUNT16_CC) Compare/Capture Value Mask */
|
||
|
|
#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
|
||
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#define TC_COUNT16_CC_Msk _U_(0xFFFF) /**< (TC_COUNT16_CC) Register Mask */
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/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 Compare/Capture -------- */
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#define TC_COUNT32_CC_RESETVALUE _U_(0x00) /**< (TC_COUNT32_CC) COUNT32 Compare/Capture Reset Value */
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#define TC_COUNT32_CC_CC_Pos _U_(0) /**< (TC_COUNT32_CC) Compare/Capture Value Position */
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#define TC_COUNT32_CC_CC_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos) /**< (TC_COUNT32_CC) Compare/Capture Value Mask */
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#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
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#define TC_COUNT32_CC_Msk _U_(0xFFFFFFFF) /**< (TC_COUNT32_CC) Register Mask */
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/** \brief TC register offsets definitions */
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#define TC_CTRLA_REG_OFST (0x00) /**< (TC_CTRLA) Control A Offset */
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#define TC_READREQ_REG_OFST (0x02) /**< (TC_READREQ) Read Request Offset */
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#define TC_CTRLBCLR_REG_OFST (0x04) /**< (TC_CTRLBCLR) Control B Clear Offset */
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#define TC_CTRLBSET_REG_OFST (0x05) /**< (TC_CTRLBSET) Control B Set Offset */
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#define TC_CTRLC_REG_OFST (0x06) /**< (TC_CTRLC) Control C Offset */
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#define TC_DBGCTRL_REG_OFST (0x08) /**< (TC_DBGCTRL) Debug Control Offset */
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#define TC_EVCTRL_REG_OFST (0x0A) /**< (TC_EVCTRL) Event Control Offset */
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#define TC_INTENCLR_REG_OFST (0x0C) /**< (TC_INTENCLR) Interrupt Enable Clear Offset */
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#define TC_INTENSET_REG_OFST (0x0D) /**< (TC_INTENSET) Interrupt Enable Set Offset */
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#define TC_INTFLAG_REG_OFST (0x0E) /**< (TC_INTFLAG) Interrupt Flag Status and Clear Offset */
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#define TC_STATUS_REG_OFST (0x0F) /**< (TC_STATUS) Status Offset */
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#define TC_COUNT8_COUNT_REG_OFST (0x10) /**< (TC_COUNT8_COUNT) COUNT8 Counter Value Offset */
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#define TC_COUNT16_COUNT_REG_OFST (0x10) /**< (TC_COUNT16_COUNT) COUNT16 Counter Value Offset */
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#define TC_COUNT32_COUNT_REG_OFST (0x10) /**< (TC_COUNT32_COUNT) COUNT32 Counter Value Offset */
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#define TC_COUNT8_PER_REG_OFST (0x14) /**< (TC_COUNT8_PER) COUNT8 Period Value Offset */
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#define TC_COUNT8_CC_REG_OFST (0x18) /**< (TC_COUNT8_CC) COUNT8 Compare/Capture Offset */
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#define TC_COUNT16_CC_REG_OFST (0x18) /**< (TC_COUNT16_CC) COUNT16 Compare/Capture Offset */
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#define TC_COUNT32_CC_REG_OFST (0x18) /**< (TC_COUNT32_CC) COUNT32 Compare/Capture Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief TC register API structure */
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typedef struct
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{ /* Basic Timer Counter */
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__IO uint16_t TC_CTRLA; /**< Offset: 0x00 (R/W 16) Control A */
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__IO uint16_t TC_READREQ; /**< Offset: 0x02 (R/W 16) Read Request */
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__IO uint8_t TC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clear */
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__IO uint8_t TC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set */
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__IO uint8_t TC_CTRLC; /**< Offset: 0x06 (R/W 8) Control C */
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__I uint8_t Reserved1[0x01];
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__IO uint8_t TC_DBGCTRL; /**< Offset: 0x08 (R/W 8) Debug Control */
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__I uint8_t Reserved2[0x01];
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__IO uint16_t TC_EVCTRL; /**< Offset: 0x0A (R/W 16) Event Control */
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__IO uint8_t TC_INTENCLR; /**< Offset: 0x0C (R/W 8) Interrupt Enable Clear */
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__IO uint8_t TC_INTENSET; /**< Offset: 0x0D (R/W 8) Interrupt Enable Set */
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__IO uint8_t TC_INTFLAG; /**< Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
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__I uint8_t TC_STATUS; /**< Offset: 0x0F (R/ 8) Status */
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__IO uint8_t TC_COUNT; /**< Offset: 0x10 (R/W 8) COUNT8 Counter Value */
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__I uint8_t Reserved3[0x03];
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__IO uint8_t TC_PER; /**< Offset: 0x14 (R/W 8) COUNT8 Period Value */
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__I uint8_t Reserved4[0x03];
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__IO uint8_t TC_CC[2]; /**< Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
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} tc_count8_registers_t;
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/** \brief TC register API structure */
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typedef struct
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{ /* Basic Timer Counter */
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__IO uint16_t TC_CTRLA; /**< Offset: 0x00 (R/W 16) Control A */
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__IO uint16_t TC_READREQ; /**< Offset: 0x02 (R/W 16) Read Request */
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__IO uint8_t TC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clear */
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__IO uint8_t TC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set */
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__IO uint8_t TC_CTRLC; /**< Offset: 0x06 (R/W 8) Control C */
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__I uint8_t Reserved1[0x01];
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__IO uint8_t TC_DBGCTRL; /**< Offset: 0x08 (R/W 8) Debug Control */
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__I uint8_t Reserved2[0x01];
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__IO uint16_t TC_EVCTRL; /**< Offset: 0x0A (R/W 16) Event Control */
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__IO uint8_t TC_INTENCLR; /**< Offset: 0x0C (R/W 8) Interrupt Enable Clear */
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__IO uint8_t TC_INTENSET; /**< Offset: 0x0D (R/W 8) Interrupt Enable Set */
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__IO uint8_t TC_INTFLAG; /**< Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
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__I uint8_t TC_STATUS; /**< Offset: 0x0F (R/ 8) Status */
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__IO uint16_t TC_COUNT; /**< Offset: 0x10 (R/W 16) COUNT16 Counter Value */
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__I uint8_t Reserved3[0x06];
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__IO uint16_t TC_CC[2]; /**< Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
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} tc_count16_registers_t;
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/** \brief TC register API structure */
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typedef struct
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{ /* Basic Timer Counter */
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__IO uint16_t TC_CTRLA; /**< Offset: 0x00 (R/W 16) Control A */
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__IO uint16_t TC_READREQ; /**< Offset: 0x02 (R/W 16) Read Request */
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__IO uint8_t TC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clear */
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__IO uint8_t TC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set */
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__IO uint8_t TC_CTRLC; /**< Offset: 0x06 (R/W 8) Control C */
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__I uint8_t Reserved1[0x01];
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__IO uint8_t TC_DBGCTRL; /**< Offset: 0x08 (R/W 8) Debug Control */
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__I uint8_t Reserved2[0x01];
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__IO uint16_t TC_EVCTRL; /**< Offset: 0x0A (R/W 16) Event Control */
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__IO uint8_t TC_INTENCLR; /**< Offset: 0x0C (R/W 8) Interrupt Enable Clear */
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__IO uint8_t TC_INTENSET; /**< Offset: 0x0D (R/W 8) Interrupt Enable Set */
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__IO uint8_t TC_INTFLAG; /**< Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
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__I uint8_t TC_STATUS; /**< Offset: 0x0F (R/ 8) Status */
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__IO uint32_t TC_COUNT; /**< Offset: 0x10 (R/W 32) COUNT32 Counter Value */
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__I uint8_t Reserved3[0x04];
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__IO uint32_t TC_CC[2]; /**< Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
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} tc_count32_registers_t;
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/** \brief TC hardware registers */
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||
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typedef union
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||
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{ /* Basic Timer Counter */
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||
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tc_count8_registers_t COUNT8; /**< 8-bit Counter Mode */
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tc_count16_registers_t COUNT16; /**< 16-bit Counter Mode */
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tc_count32_registers_t COUNT32; /**< 32-bit Counter Mode */
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} tc_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAMD21_TC_COMPONENT_H_ */
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