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123 lines
8.4 KiB
C
123 lines
8.4 KiB
C
4 years ago
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/**
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* \file
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*
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* \brief Instance description for TCC3
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*
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* Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_TCC3_INSTANCE_
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#define _SAMD21_TCC3_INSTANCE_
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/* ========== Register definition for TCC3 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TCC3_CTRLA (0x42006000) /**< \brief (TCC3) Control A */
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#define REG_TCC3_CTRLBCLR (0x42006004) /**< \brief (TCC3) Control B Clear */
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#define REG_TCC3_CTRLBSET (0x42006005) /**< \brief (TCC3) Control B Set */
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#define REG_TCC3_SYNCBUSY (0x42006008) /**< \brief (TCC3) Synchronization Busy */
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#define REG_TCC3_FCTRLA (0x4200600C) /**< \brief (TCC3) Recoverable Fault A Configuration */
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#define REG_TCC3_FCTRLB (0x42006010) /**< \brief (TCC3) Recoverable Fault B Configuration */
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#define REG_TCC3_WEXCTRL (0x42006014) /**< \brief (TCC3) Waveform Extension Configuration */
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#define REG_TCC3_DRVCTRL (0x42006018) /**< \brief (TCC3) Driver Control */
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#define REG_TCC3_DBGCTRL (0x4200601E) /**< \brief (TCC3) Debug Control */
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#define REG_TCC3_EVCTRL (0x42006020) /**< \brief (TCC3) Event Control */
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#define REG_TCC3_INTENCLR (0x42006024) /**< \brief (TCC3) Interrupt Enable Clear */
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#define REG_TCC3_INTENSET (0x42006028) /**< \brief (TCC3) Interrupt Enable Set */
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#define REG_TCC3_INTFLAG (0x4200602C) /**< \brief (TCC3) Interrupt Flag Status and Clear */
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#define REG_TCC3_STATUS (0x42006030) /**< \brief (TCC3) Status */
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#define REG_TCC3_COUNT (0x42006034) /**< \brief (TCC3) Count */
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#define REG_TCC3_PATT (0x42006038) /**< \brief (TCC3) Pattern */
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#define REG_TCC3_WAVE (0x4200603C) /**< \brief (TCC3) Waveform Control */
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#define REG_TCC3_PER (0x42006040) /**< \brief (TCC3) Period */
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#define REG_TCC3_CC0 (0x42006044) /**< \brief (TCC3) Compare and Capture 0 */
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#define REG_TCC3_CC1 (0x42006048) /**< \brief (TCC3) Compare and Capture 1 */
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#define REG_TCC3_CC2 (0x4200604C) /**< \brief (TCC3) Compare and Capture 2 */
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#define REG_TCC3_CC3 (0x42006050) /**< \brief (TCC3) Compare and Capture 3 */
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#define REG_TCC3_PATTB (0x42006064) /**< \brief (TCC3) Pattern Buffer */
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#define REG_TCC3_WAVEB (0x42006068) /**< \brief (TCC3) Waveform Control Buffer */
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#define REG_TCC3_PERB (0x4200606C) /**< \brief (TCC3) Period Buffer */
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#define REG_TCC3_CCB0 (0x42006070) /**< \brief (TCC3) Compare and Capture Buffer 0 */
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#define REG_TCC3_CCB1 (0x42006074) /**< \brief (TCC3) Compare and Capture Buffer 1 */
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#define REG_TCC3_CCB2 (0x42006078) /**< \brief (TCC3) Compare and Capture Buffer 2 */
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#define REG_TCC3_CCB3 (0x4200607C) /**< \brief (TCC3) Compare and Capture Buffer 3 */
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#else
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#define REG_TCC3_CTRLA (*(RwReg *)0x42006000UL) /**< \brief (TCC3) Control A */
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#define REG_TCC3_CTRLBCLR (*(RwReg8 *)0x42006004UL) /**< \brief (TCC3) Control B Clear */
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#define REG_TCC3_CTRLBSET (*(RwReg8 *)0x42006005UL) /**< \brief (TCC3) Control B Set */
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#define REG_TCC3_SYNCBUSY (*(RoReg *)0x42006008UL) /**< \brief (TCC3) Synchronization Busy */
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#define REG_TCC3_FCTRLA (*(RwReg *)0x4200600CUL) /**< \brief (TCC3) Recoverable Fault A Configuration */
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#define REG_TCC3_FCTRLB (*(RwReg *)0x42006010UL) /**< \brief (TCC3) Recoverable Fault B Configuration */
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#define REG_TCC3_WEXCTRL (*(RwReg *)0x42006014UL) /**< \brief (TCC3) Waveform Extension Configuration */
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#define REG_TCC3_DRVCTRL (*(RwReg *)0x42006018UL) /**< \brief (TCC3) Driver Control */
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#define REG_TCC3_DBGCTRL (*(RwReg8 *)0x4200601EUL) /**< \brief (TCC3) Debug Control */
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#define REG_TCC3_EVCTRL (*(RwReg *)0x42006020UL) /**< \brief (TCC3) Event Control */
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#define REG_TCC3_INTENCLR (*(RwReg *)0x42006024UL) /**< \brief (TCC3) Interrupt Enable Clear */
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#define REG_TCC3_INTENSET (*(RwReg *)0x42006028UL) /**< \brief (TCC3) Interrupt Enable Set */
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#define REG_TCC3_INTFLAG (*(RwReg *)0x4200602CUL) /**< \brief (TCC3) Interrupt Flag Status and Clear */
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#define REG_TCC3_STATUS (*(RwReg *)0x42006030UL) /**< \brief (TCC3) Status */
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#define REG_TCC3_COUNT (*(RwReg *)0x42006034UL) /**< \brief (TCC3) Count */
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#define REG_TCC3_PATT (*(RwReg16*)0x42006038UL) /**< \brief (TCC3) Pattern */
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#define REG_TCC3_WAVE (*(RwReg *)0x4200603CUL) /**< \brief (TCC3) Waveform Control */
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#define REG_TCC3_PER (*(RwReg *)0x42006040UL) /**< \brief (TCC3) Period */
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#define REG_TCC3_CC0 (*(RwReg *)0x42006044UL) /**< \brief (TCC3) Compare and Capture 0 */
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#define REG_TCC3_CC1 (*(RwReg *)0x42006048UL) /**< \brief (TCC3) Compare and Capture 1 */
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#define REG_TCC3_CC2 (*(RwReg *)0x4200604CUL) /**< \brief (TCC3) Compare and Capture 2 */
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#define REG_TCC3_CC3 (*(RwReg *)0x42006050UL) /**< \brief (TCC3) Compare and Capture 3 */
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#define REG_TCC3_PATTB (*(RwReg16*)0x42006064UL) /**< \brief (TCC3) Pattern Buffer */
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#define REG_TCC3_WAVEB (*(RwReg *)0x42006068UL) /**< \brief (TCC3) Waveform Control Buffer */
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#define REG_TCC3_PERB (*(RwReg *)0x4200606CUL) /**< \brief (TCC3) Period Buffer */
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#define REG_TCC3_CCB0 (*(RwReg *)0x42006070UL) /**< \brief (TCC3) Compare and Capture Buffer 0 */
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#define REG_TCC3_CCB1 (*(RwReg *)0x42006074UL) /**< \brief (TCC3) Compare and Capture Buffer 1 */
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#define REG_TCC3_CCB2 (*(RwReg *)0x42006078UL) /**< \brief (TCC3) Compare and Capture Buffer 2 */
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#define REG_TCC3_CCB3 (*(RwReg *)0x4200607CUL) /**< \brief (TCC3) Compare and Capture Buffer 3 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for TCC3 peripheral ========== */
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#define TCC3_CC_NUM 4 // Number of Compare/Capture units
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#define TCC3_DITHERING 1 // Dithering feature implemented
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#define TCC3_DMAC_ID_MC_0 46
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#define TCC3_DMAC_ID_MC_1 47
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#define TCC3_DMAC_ID_MC_2 48
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#define TCC3_DMAC_ID_MC_3 49
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#define TCC3_DMAC_ID_MC_LSB 46
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#define TCC3_DMAC_ID_MC_MSB 49
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#define TCC3_DMAC_ID_MC_SIZE 4
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#define TCC3_DMAC_ID_OVF 45 // DMA overflow/underflow/retrigger trigger
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#define TCC3_DTI 1 // Dead-Time-Insertion feature implemented
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#define TCC3_EXT 31 // Coding of implemented extended features
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#define TCC3_GCLK_ID 37 // Index of Generic Clock
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#define TCC3_MASTER 0
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#define TCC3_OTMX 1 // Output Matrix feature implemented
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#define TCC3_OW_NUM 8 // Number of Output Waveforms
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#define TCC3_PG 1 // Pattern Generation feature implemented
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#define TCC3_SIZE 24
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#define TCC3_SWAP 1 // DTI outputs swap feature implemented
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#define TCC3_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
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#endif /* _SAMD21_TCC3_INSTANCE_ */
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