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added doxygen... i hate it
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<p>PICOP hardware registers.
<a href="structPicop.html#details">More...</a></p>
<p><code>#include &lt;<a class="el" href="component_2picop_8h_source.html">picop.h</a>&gt;</code></p>
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<tr class="memdesc:af453bf8cf953a6aa86afd3e39ba4a1a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x094 (R/W 32) R23 to 20. <br /></td></tr>
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<tr class="memdesc:ae2e771bb0ad76f346d2d232e16aa0ef6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x098 (R/W 32) R27 to 24: XH, XL, R25, R24. <br /></td></tr>
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<tr class="memdesc:a1768e1ba57d37694dd706f142622cc0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x09C (R/W 32) R31 to 28: ZH, ZL, YH, YL. <br /></td></tr>
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<tr class="memitem:a726f15d25e0cce72852da3375b1ae04f"><td class="memItemLeft" align="right" valign="top"><a id="a726f15d25e0cce72852da3375b1ae04f"></a>
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<tr class="memdesc:a726f15d25e0cce72852da3375b1ae04f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0A0 (R/W 32) System Regs 1 to 0: SR. <br /></td></tr>
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<tr class="memitem:add53643aae577046c29980c7e8b445c9"><td class="memItemLeft" align="right" valign="top"><a id="add53643aae577046c29980c7e8b445c9"></a>
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<tr class="memdesc:add53643aae577046c29980c7e8b445c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0A4 (R/W 32) System Regs 3 to 2: CTRL. <br /></td></tr>
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<tr class="memitem:a0424733cecb32caa268d74d44e78894a"><td class="memItemLeft" align="right" valign="top"><a id="a0424733cecb32caa268d74d44e78894a"></a>
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<tr class="memdesc:a0424733cecb32caa268d74d44e78894a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0A8 (R/W 32) System Regs 5 to 4: SREG, CCR. <br /></td></tr>
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<tr class="memitem:afddf398dcc03f96956ffe63e048668f7"><td class="memItemLeft" align="right" valign="top"><a id="afddf398dcc03f96956ffe63e048668f7"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a>&#160;</td><td class="memItemRight" valign="bottom"><b>Reserved4</b> [0x8]</td></tr>
<tr class="separator:afddf398dcc03f96956ffe63e048668f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8370ed32bf0f8c299085169f07b4bd14"><td class="memItemLeft" align="right" valign="top"><a id="a8370ed32bf0f8c299085169f07b4bd14"></a>
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<tr class="memitem:a13f70fef9f202e157ba106f2c56eb4e1"><td class="memItemLeft" align="right" valign="top"><a id="a13f70fef9f202e157ba106f2c56eb4e1"></a>
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<tr class="memdesc:a13f70fef9f202e157ba106f2c56eb4e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0B8 (R/W 32) Link. <br /></td></tr>
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<tr class="memdesc:a3b82e4cb1776c77816ba0bf16eae0bfe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0BC (R/W 32) Stack Pointer. <br /></td></tr>
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<tr class="memitem:a8d89ce4edfb46f2678ede119c3089a61"><td class="memItemLeft" align="right" valign="top"><a id="a8d89ce4edfb46f2678ede119c3089a61"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a>&#160;</td><td class="memItemRight" valign="bottom"><b>Reserved5</b> [0x40]</td></tr>
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<tr class="memitem:a052b6a7a264ff7f6ebf6e8b5fe36f1af"><td class="memItemLeft" align="right" valign="top"><a id="a052b6a7a264ff7f6ebf6e8b5fe36f1af"></a>
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<tr class="memdesc:a052b6a7a264ff7f6ebf6e8b5fe36f1af"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x100 (R/W 32) MMU mapping for flash. <br /></td></tr>
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<tr class="memdesc:a4b019cca1c976fa47fcda394db203e50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x118 (R/W 32) MMU mapping user 0. <br /></td></tr>
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<tr class="memdesc:acb04d87fb9f3a9f52732243fa5a9846f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x11C (R/W 32) MMU mapping user 1. <br /></td></tr>
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<tr class="memdesc:ad781f325652dffdb3e472aa8ed09aa60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x120 (R/W 32) MMU Control. <br /></td></tr>
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<tr class="memitem:a090e18940522a41928828aebf2668710"><td class="memItemLeft" align="right" valign="top"><a id="a090e18940522a41928828aebf2668710"></a>
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<tr class="memitem:a225dc570334332dfa9db45ffc8ae5184"><td class="memItemLeft" align="right" valign="top"><a id="a225dc570334332dfa9db45ffc8ae5184"></a>
__IO <a class="el" href="unionPICOP__ICACHE__Type.html">PICOP_ICACHE_Type</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a225dc570334332dfa9db45ffc8ae5184">ICACHE</a></td></tr>
<tr class="memdesc:a225dc570334332dfa9db45ffc8ae5184"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x180 (R/W 32) Instruction Cache Control. <br /></td></tr>
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<tr class="memdesc:ae63b2539dcc65e1c490e891d7f098130"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x184 (R/W 32) Instruction Cache LRU. <br /></td></tr>
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<tr class="memitem:ae3caacd32da29b6f6152ec8663b5986b"><td class="memItemLeft" align="right" valign="top"><a id="ae3caacd32da29b6f6152ec8663b5986b"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a>&#160;</td><td class="memItemRight" valign="bottom"><b>Reserved8</b> [0x78]</td></tr>
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<tr class="memitem:a1546159caebf63df278d15554a0cb692"><td class="memItemLeft" align="right" valign="top"><a id="a1546159caebf63df278d15554a0cb692"></a>
__IO <a class="el" href="unionPICOP__QOSCTRL__Type.html">PICOP_QOSCTRL_Type</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a1546159caebf63df278d15554a0cb692">QOSCTRL</a></td></tr>
<tr class="memdesc:a1546159caebf63df278d15554a0cb692"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x200 (R/W 32) QOS Control. <br /></td></tr>
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</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>PICOP hardware registers. </p>
<p class="definition">Definition at line <a class="el" href="component_2picop_8h_source.html#l01270">1270</a> of file <a class="el" href="component_2picop_8h_source.html">picop.h</a>.</p>
</div><hr/>The documentation for this struct was generated from the following file:<ul>
<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2picop_8h_source.html">picop.h</a></li>
</ul>
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