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317 lines
41 KiB
HTML
317 lines
41 KiB
HTML
4 years ago
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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/sdhc1.h File Reference</title>
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<div id="projectname">SAME54P20A Test Project
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<ul>
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="summary">
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<a href="#define-members">Macros</a> </div>
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<div class="headertitle">
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<div class="title">sdhc1.h File Reference</div> </div>
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</div><!--header-->
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<div class="contents">
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<p>Instance description for SDHC1.
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<a href="#details">More...</a></p>
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<p><a href="sdhc1_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a6bbb4d593120cfa1463ac4a44e693b84"><td class="memItemLeft" align="right" valign="top"><a id="a6bbb4d593120cfa1463ac4a44e693b84"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a6bbb4d593120cfa1463ac4a44e693b84">REG_SDHC1_SSAR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x46000000UL)</td></tr>
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<tr class="memdesc:a6bbb4d593120cfa1463ac4a44e693b84"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) SDMA System Address / Argument 2 <br /></td></tr>
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<tr class="separator:a6bbb4d593120cfa1463ac4a44e693b84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a865e934a053ebb9d4f2f688812bbe1ab"><td class="memItemLeft" align="right" valign="top"><a id="a865e934a053ebb9d4f2f688812bbe1ab"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a865e934a053ebb9d4f2f688812bbe1ab">REG_SDHC1_BSR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x46000004UL)</td></tr>
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<tr class="memdesc:a865e934a053ebb9d4f2f688812bbe1ab"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Block Size <br /></td></tr>
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<tr class="separator:a865e934a053ebb9d4f2f688812bbe1ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a198673fecd34391f3384da6226dc49b2"><td class="memItemLeft" align="right" valign="top"><a id="a198673fecd34391f3384da6226dc49b2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a198673fecd34391f3384da6226dc49b2">REG_SDHC1_BCR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x46000006UL)</td></tr>
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<tr class="memdesc:a198673fecd34391f3384da6226dc49b2"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Block Count <br /></td></tr>
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<tr class="separator:a198673fecd34391f3384da6226dc49b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aad163f93ccff808a9a456182ecca91b5"><td class="memItemLeft" align="right" valign="top"><a id="aad163f93ccff808a9a456182ecca91b5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#aad163f93ccff808a9a456182ecca91b5">REG_SDHC1_ARG1R</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x46000008UL)</td></tr>
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<tr class="memdesc:aad163f93ccff808a9a456182ecca91b5"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Argument 1 <br /></td></tr>
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<tr class="separator:aad163f93ccff808a9a456182ecca91b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a933e870d94460933803f1296691ffa78"><td class="memItemLeft" align="right" valign="top"><a id="a933e870d94460933803f1296691ffa78"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a933e870d94460933803f1296691ffa78">REG_SDHC1_TMR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4600000CUL)</td></tr>
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<tr class="memdesc:a933e870d94460933803f1296691ffa78"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Transfer Mode <br /></td></tr>
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<tr class="separator:a933e870d94460933803f1296691ffa78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b4ad7b6433c8d523e69c44a3484eb90"><td class="memItemLeft" align="right" valign="top"><a id="a8b4ad7b6433c8d523e69c44a3484eb90"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a8b4ad7b6433c8d523e69c44a3484eb90">REG_SDHC1_CR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4600000EUL)</td></tr>
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<tr class="memdesc:a8b4ad7b6433c8d523e69c44a3484eb90"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Command <br /></td></tr>
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<tr class="separator:a8b4ad7b6433c8d523e69c44a3484eb90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abb30e3244ea714d7636ee4983d325bce"><td class="memItemLeft" align="right" valign="top"><a id="abb30e3244ea714d7636ee4983d325bce"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#abb30e3244ea714d7636ee4983d325bce">REG_SDHC1_RR0</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x46000010UL)</td></tr>
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<tr class="memdesc:abb30e3244ea714d7636ee4983d325bce"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Response 0 <br /></td></tr>
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<tr class="separator:abb30e3244ea714d7636ee4983d325bce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a784db29f8476ce74a9e9581bcfcd3bd2"><td class="memItemLeft" align="right" valign="top"><a id="a784db29f8476ce74a9e9581bcfcd3bd2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a784db29f8476ce74a9e9581bcfcd3bd2">REG_SDHC1_RR1</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x46000014UL)</td></tr>
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<tr class="memdesc:a784db29f8476ce74a9e9581bcfcd3bd2"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Response 1 <br /></td></tr>
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<tr class="separator:a784db29f8476ce74a9e9581bcfcd3bd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adc54afd610c144ca5deaa1a9e3d2cabe"><td class="memItemLeft" align="right" valign="top"><a id="adc54afd610c144ca5deaa1a9e3d2cabe"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#adc54afd610c144ca5deaa1a9e3d2cabe">REG_SDHC1_RR2</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x46000018UL)</td></tr>
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<tr class="memdesc:adc54afd610c144ca5deaa1a9e3d2cabe"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Response 2 <br /></td></tr>
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<tr class="separator:adc54afd610c144ca5deaa1a9e3d2cabe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9390382f21a99d523624672449bf86be"><td class="memItemLeft" align="right" valign="top"><a id="a9390382f21a99d523624672449bf86be"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a9390382f21a99d523624672449bf86be">REG_SDHC1_RR3</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4600001CUL)</td></tr>
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<tr class="memdesc:a9390382f21a99d523624672449bf86be"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Response 3 <br /></td></tr>
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<tr class="separator:a9390382f21a99d523624672449bf86be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a29715c479708548ece5e4afc4dd1f774"><td class="memItemLeft" align="right" valign="top"><a id="a29715c479708548ece5e4afc4dd1f774"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a29715c479708548ece5e4afc4dd1f774">REG_SDHC1_BDPR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x46000020UL)</td></tr>
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<tr class="memdesc:a29715c479708548ece5e4afc4dd1f774"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Buffer Data <a class="el" href="structPort.html" title="PORT hardware registers.">Port</a> <br /></td></tr>
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<tr class="separator:a29715c479708548ece5e4afc4dd1f774"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a427d7cbf9738f53cc222e81d8273185f"><td class="memItemLeft" align="right" valign="top"><a id="a427d7cbf9738f53cc222e81d8273185f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a427d7cbf9738f53cc222e81d8273185f">REG_SDHC1_PSR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x46000024UL)</td></tr>
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<tr class="memdesc:a427d7cbf9738f53cc222e81d8273185f"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Present State <br /></td></tr>
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<tr class="separator:a427d7cbf9738f53cc222e81d8273185f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaa3d8d9ca72cb98118dd8383a8e00646"><td class="memItemLeft" align="right" valign="top"><a id="aaa3d8d9ca72cb98118dd8383a8e00646"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#aaa3d8d9ca72cb98118dd8383a8e00646">REG_SDHC1_HC1R</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x46000028UL)</td></tr>
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<tr class="memdesc:aaa3d8d9ca72cb98118dd8383a8e00646"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Host Control 1 <br /></td></tr>
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<tr class="separator:aaa3d8d9ca72cb98118dd8383a8e00646"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5cec30317d3298d583245e5f98ec2241"><td class="memItemLeft" align="right" valign="top"><a id="a5cec30317d3298d583245e5f98ec2241"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a5cec30317d3298d583245e5f98ec2241">REG_SDHC1_PCR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x46000029UL)</td></tr>
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<tr class="memdesc:a5cec30317d3298d583245e5f98ec2241"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Power Control <br /></td></tr>
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<tr class="separator:a5cec30317d3298d583245e5f98ec2241"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac32466a4e40e068f1d306260d6722a77"><td class="memItemLeft" align="right" valign="top"><a id="ac32466a4e40e068f1d306260d6722a77"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#ac32466a4e40e068f1d306260d6722a77">REG_SDHC1_BGCR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4600002AUL)</td></tr>
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<tr class="memdesc:ac32466a4e40e068f1d306260d6722a77"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Block Gap Control <br /></td></tr>
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<tr class="separator:ac32466a4e40e068f1d306260d6722a77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab413464f41c6dfbea3caf6bb81285c6c"><td class="memItemLeft" align="right" valign="top"><a id="ab413464f41c6dfbea3caf6bb81285c6c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#ab413464f41c6dfbea3caf6bb81285c6c">REG_SDHC1_WCR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4600002BUL)</td></tr>
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<tr class="memdesc:ab413464f41c6dfbea3caf6bb81285c6c"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Wakeup Control <br /></td></tr>
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<tr class="separator:ab413464f41c6dfbea3caf6bb81285c6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a79adad14b1b67193772044385479cea7"><td class="memItemLeft" align="right" valign="top"><a id="a79adad14b1b67193772044385479cea7"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a79adad14b1b67193772044385479cea7">REG_SDHC1_CCR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4600002CUL)</td></tr>
|
||
|
|
<tr class="memdesc:a79adad14b1b67193772044385479cea7"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Clock Control <br /></td></tr>
|
||
|
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<tr class="separator:a79adad14b1b67193772044385479cea7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a774ef8e66b70ad41cc0ac8b587c14b67"><td class="memItemLeft" align="right" valign="top"><a id="a774ef8e66b70ad41cc0ac8b587c14b67"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a774ef8e66b70ad41cc0ac8b587c14b67">REG_SDHC1_TCR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4600002EUL)</td></tr>
|
||
|
|
<tr class="memdesc:a774ef8e66b70ad41cc0ac8b587c14b67"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Timeout Control <br /></td></tr>
|
||
|
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<tr class="separator:a774ef8e66b70ad41cc0ac8b587c14b67"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a50d6aeb1ed8d901b68e49e99530c08c9"><td class="memItemLeft" align="right" valign="top"><a id="a50d6aeb1ed8d901b68e49e99530c08c9"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a50d6aeb1ed8d901b68e49e99530c08c9">REG_SDHC1_SRR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4600002FUL)</td></tr>
|
||
|
|
<tr class="memdesc:a50d6aeb1ed8d901b68e49e99530c08c9"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Software Reset <br /></td></tr>
|
||
|
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<tr class="separator:a50d6aeb1ed8d901b68e49e99530c08c9"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a8ea5f015005bd56d6b139f23d964d7d8"><td class="memItemLeft" align="right" valign="top"><a id="a8ea5f015005bd56d6b139f23d964d7d8"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a8ea5f015005bd56d6b139f23d964d7d8">REG_SDHC1_NISTR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x46000030UL)</td></tr>
|
||
|
|
<tr class="memdesc:a8ea5f015005bd56d6b139f23d964d7d8"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Normal Interrupt Status <br /></td></tr>
|
||
|
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<tr class="separator:a8ea5f015005bd56d6b139f23d964d7d8"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aaf211937d241f48aea26b13021954c47"><td class="memItemLeft" align="right" valign="top"><a id="aaf211937d241f48aea26b13021954c47"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#aaf211937d241f48aea26b13021954c47">REG_SDHC1_EISTR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x46000032UL)</td></tr>
|
||
|
|
<tr class="memdesc:aaf211937d241f48aea26b13021954c47"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Error Interrupt Status <br /></td></tr>
|
||
|
|
<tr class="separator:aaf211937d241f48aea26b13021954c47"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a4edd7093f3722ac71a28318df6e14260"><td class="memItemLeft" align="right" valign="top"><a id="a4edd7093f3722ac71a28318df6e14260"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a4edd7093f3722ac71a28318df6e14260">REG_SDHC1_NISTER</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x46000034UL)</td></tr>
|
||
|
|
<tr class="memdesc:a4edd7093f3722ac71a28318df6e14260"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Normal Interrupt Status Enable <br /></td></tr>
|
||
|
|
<tr class="separator:a4edd7093f3722ac71a28318df6e14260"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab6b0a91762d01272dbde049c825b09b9"><td class="memItemLeft" align="right" valign="top"><a id="ab6b0a91762d01272dbde049c825b09b9"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#ab6b0a91762d01272dbde049c825b09b9">REG_SDHC1_EISTER</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x46000036UL)</td></tr>
|
||
|
|
<tr class="memdesc:ab6b0a91762d01272dbde049c825b09b9"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Error Interrupt Status Enable <br /></td></tr>
|
||
|
|
<tr class="separator:ab6b0a91762d01272dbde049c825b09b9"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab686a50cd009672b0c7405e62a297b6c"><td class="memItemLeft" align="right" valign="top"><a id="ab686a50cd009672b0c7405e62a297b6c"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#ab686a50cd009672b0c7405e62a297b6c">REG_SDHC1_NISIER</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x46000038UL)</td></tr>
|
||
|
|
<tr class="memdesc:ab686a50cd009672b0c7405e62a297b6c"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Normal Interrupt Signal Enable <br /></td></tr>
|
||
|
|
<tr class="separator:ab686a50cd009672b0c7405e62a297b6c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a2d290a0715aec4fe95778a15444721ed"><td class="memItemLeft" align="right" valign="top"><a id="a2d290a0715aec4fe95778a15444721ed"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a2d290a0715aec4fe95778a15444721ed">REG_SDHC1_EISIER</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4600003AUL)</td></tr>
|
||
|
|
<tr class="memdesc:a2d290a0715aec4fe95778a15444721ed"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Error Interrupt Signal Enable <br /></td></tr>
|
||
|
|
<tr class="separator:a2d290a0715aec4fe95778a15444721ed"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a11d52e22e8c1e3ce88d39ff604ed16e9"><td class="memItemLeft" align="right" valign="top"><a id="a11d52e22e8c1e3ce88d39ff604ed16e9"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a11d52e22e8c1e3ce88d39ff604ed16e9">REG_SDHC1_ACESR</a>   (*(<a class="el" href="same54n19a_8h.html#aebf6e33c2d49a802e06e22a95ea9d0d0">RoReg16</a>*)0x4600003CUL)</td></tr>
|
||
|
|
<tr class="memdesc:a11d52e22e8c1e3ce88d39ff604ed16e9"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Auto CMD Error Status <br /></td></tr>
|
||
|
|
<tr class="separator:a11d52e22e8c1e3ce88d39ff604ed16e9"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ac33a9b96ab0675be66d4793c05bf282b"><td class="memItemLeft" align="right" valign="top"><a id="ac33a9b96ab0675be66d4793c05bf282b"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#ac33a9b96ab0675be66d4793c05bf282b">REG_SDHC1_HC2R</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4600003EUL)</td></tr>
|
||
|
|
<tr class="memdesc:ac33a9b96ab0675be66d4793c05bf282b"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Host Control 2 <br /></td></tr>
|
||
|
|
<tr class="separator:ac33a9b96ab0675be66d4793c05bf282b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ad72a4b840413d2167ae20c275e367ee1"><td class="memItemLeft" align="right" valign="top"><a id="ad72a4b840413d2167ae20c275e367ee1"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#ad72a4b840413d2167ae20c275e367ee1">REG_SDHC1_CA0R</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x46000040UL)</td></tr>
|
||
|
|
<tr class="memdesc:ad72a4b840413d2167ae20c275e367ee1"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Capabilities 0 <br /></td></tr>
|
||
|
|
<tr class="separator:ad72a4b840413d2167ae20c275e367ee1"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a7ad18a3a56a1ec47073648d7ca78e48d"><td class="memItemLeft" align="right" valign="top"><a id="a7ad18a3a56a1ec47073648d7ca78e48d"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a7ad18a3a56a1ec47073648d7ca78e48d">REG_SDHC1_CA1R</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x46000044UL)</td></tr>
|
||
|
|
<tr class="memdesc:a7ad18a3a56a1ec47073648d7ca78e48d"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Capabilities 1 <br /></td></tr>
|
||
|
|
<tr class="separator:a7ad18a3a56a1ec47073648d7ca78e48d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a1ea423a45a54dcca0f89dbab88fa941a"><td class="memItemLeft" align="right" valign="top"><a id="a1ea423a45a54dcca0f89dbab88fa941a"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a1ea423a45a54dcca0f89dbab88fa941a">REG_SDHC1_MCCAR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x46000048UL)</td></tr>
|
||
|
|
<tr class="memdesc:a1ea423a45a54dcca0f89dbab88fa941a"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Maximum Current Capabilities <br /></td></tr>
|
||
|
|
<tr class="separator:a1ea423a45a54dcca0f89dbab88fa941a"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ae260a343bd219fb789777f073416fd2e"><td class="memItemLeft" align="right" valign="top"><a id="ae260a343bd219fb789777f073416fd2e"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#ae260a343bd219fb789777f073416fd2e">REG_SDHC1_FERACES</a>   (*(<a class="el" href="same54n19a_8h.html#a0ab0e5f6c8301aa1c2068e511d854094">WoReg16</a>*)0x46000050UL)</td></tr>
|
||
|
|
<tr class="memdesc:ae260a343bd219fb789777f073416fd2e"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Force Event for Auto CMD Error Status <br /></td></tr>
|
||
|
|
<tr class="separator:ae260a343bd219fb789777f073416fd2e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:af82ef2af4a0fb0fe57e282486e444597"><td class="memItemLeft" align="right" valign="top"><a id="af82ef2af4a0fb0fe57e282486e444597"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#af82ef2af4a0fb0fe57e282486e444597">REG_SDHC1_FEREIS</a>   (*(<a class="el" href="same54n19a_8h.html#a0ab0e5f6c8301aa1c2068e511d854094">WoReg16</a>*)0x46000052UL)</td></tr>
|
||
|
|
<tr class="memdesc:af82ef2af4a0fb0fe57e282486e444597"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Force Event for Error Interrupt Status <br /></td></tr>
|
||
|
|
<tr class="separator:af82ef2af4a0fb0fe57e282486e444597"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a86928886c9e1f43e0bdc92600786cca0"><td class="memItemLeft" align="right" valign="top"><a id="a86928886c9e1f43e0bdc92600786cca0"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a86928886c9e1f43e0bdc92600786cca0">REG_SDHC1_AESR</a>   (*(<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> *)0x46000054UL)</td></tr>
|
||
|
|
<tr class="memdesc:a86928886c9e1f43e0bdc92600786cca0"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) ADMA Error Status <br /></td></tr>
|
||
|
|
<tr class="separator:a86928886c9e1f43e0bdc92600786cca0"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a1ebb727f9d2cbd58150ec97d3e94d2d8"><td class="memItemLeft" align="right" valign="top"><a id="a1ebb727f9d2cbd58150ec97d3e94d2d8"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a1ebb727f9d2cbd58150ec97d3e94d2d8">REG_SDHC1_ASAR0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x46000058UL)</td></tr>
|
||
|
|
<tr class="memdesc:a1ebb727f9d2cbd58150ec97d3e94d2d8"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) ADMA System Address 0 <br /></td></tr>
|
||
|
|
<tr class="separator:a1ebb727f9d2cbd58150ec97d3e94d2d8"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a2cddba3819a0d45545250523ed37085a"><td class="memItemLeft" align="right" valign="top"><a id="a2cddba3819a0d45545250523ed37085a"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a2cddba3819a0d45545250523ed37085a">REG_SDHC1_PVR0</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x46000060UL)</td></tr>
|
||
|
|
<tr class="memdesc:a2cddba3819a0d45545250523ed37085a"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Preset Value 0 <br /></td></tr>
|
||
|
|
<tr class="separator:a2cddba3819a0d45545250523ed37085a"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a2e19ae4ea03e9edbac7c821b24dc4d81"><td class="memItemLeft" align="right" valign="top"><a id="a2e19ae4ea03e9edbac7c821b24dc4d81"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a2e19ae4ea03e9edbac7c821b24dc4d81">REG_SDHC1_PVR1</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x46000062UL)</td></tr>
|
||
|
|
<tr class="memdesc:a2e19ae4ea03e9edbac7c821b24dc4d81"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Preset Value 1 <br /></td></tr>
|
||
|
|
<tr class="separator:a2e19ae4ea03e9edbac7c821b24dc4d81"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aba247026d48f0f37361757d51f4862b1"><td class="memItemLeft" align="right" valign="top"><a id="aba247026d48f0f37361757d51f4862b1"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#aba247026d48f0f37361757d51f4862b1">REG_SDHC1_PVR2</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x46000064UL)</td></tr>
|
||
|
|
<tr class="memdesc:aba247026d48f0f37361757d51f4862b1"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Preset Value 2 <br /></td></tr>
|
||
|
|
<tr class="separator:aba247026d48f0f37361757d51f4862b1"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a7d9a5bc86f1a33fddd84aed1721c8b36"><td class="memItemLeft" align="right" valign="top"><a id="a7d9a5bc86f1a33fddd84aed1721c8b36"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a7d9a5bc86f1a33fddd84aed1721c8b36">REG_SDHC1_PVR3</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x46000066UL)</td></tr>
|
||
|
|
<tr class="memdesc:a7d9a5bc86f1a33fddd84aed1721c8b36"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Preset Value 3 <br /></td></tr>
|
||
|
|
<tr class="separator:a7d9a5bc86f1a33fddd84aed1721c8b36"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a999451324e22353856b184645ed80c2f"><td class="memItemLeft" align="right" valign="top"><a id="a999451324e22353856b184645ed80c2f"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a999451324e22353856b184645ed80c2f">REG_SDHC1_PVR4</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x46000068UL)</td></tr>
|
||
|
|
<tr class="memdesc:a999451324e22353856b184645ed80c2f"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Preset Value 4 <br /></td></tr>
|
||
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<tr class="separator:a999451324e22353856b184645ed80c2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5d87cdcda20335386f49a0e61608fb8c"><td class="memItemLeft" align="right" valign="top"><a id="a5d87cdcda20335386f49a0e61608fb8c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a5d87cdcda20335386f49a0e61608fb8c">REG_SDHC1_PVR5</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4600006AUL)</td></tr>
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<tr class="memdesc:a5d87cdcda20335386f49a0e61608fb8c"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Preset Value 5 <br /></td></tr>
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<tr class="separator:a5d87cdcda20335386f49a0e61608fb8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac0f90b430987f769641c2e248a49a8a6"><td class="memItemLeft" align="right" valign="top"><a id="ac0f90b430987f769641c2e248a49a8a6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#ac0f90b430987f769641c2e248a49a8a6">REG_SDHC1_PVR6</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4600006CUL)</td></tr>
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<tr class="memdesc:ac0f90b430987f769641c2e248a49a8a6"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Preset Value 6 <br /></td></tr>
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<tr class="separator:ac0f90b430987f769641c2e248a49a8a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1271c803bb327c16180eab019910d055"><td class="memItemLeft" align="right" valign="top"><a id="a1271c803bb327c16180eab019910d055"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a1271c803bb327c16180eab019910d055">REG_SDHC1_PVR7</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4600006EUL)</td></tr>
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<tr class="memdesc:a1271c803bb327c16180eab019910d055"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Preset Value 7 <br /></td></tr>
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<tr class="separator:a1271c803bb327c16180eab019910d055"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab946d2cfa4c133e1fe77c537fa7d18a9"><td class="memItemLeft" align="right" valign="top"><a id="ab946d2cfa4c133e1fe77c537fa7d18a9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#ab946d2cfa4c133e1fe77c537fa7d18a9">REG_SDHC1_SISR</a>   (*(<a class="el" href="same54n19a_8h.html#aebf6e33c2d49a802e06e22a95ea9d0d0">RoReg16</a>*)0x460000FCUL)</td></tr>
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<tr class="memdesc:ab946d2cfa4c133e1fe77c537fa7d18a9"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Slot Interrupt Status <br /></td></tr>
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<tr class="separator:ab946d2cfa4c133e1fe77c537fa7d18a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a361d0a9e8311a29b6e545a6c0ae5d6"><td class="memItemLeft" align="right" valign="top"><a id="a0a361d0a9e8311a29b6e545a6c0ae5d6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a0a361d0a9e8311a29b6e545a6c0ae5d6">REG_SDHC1_HCVR</a>   (*(<a class="el" href="same54n19a_8h.html#aebf6e33c2d49a802e06e22a95ea9d0d0">RoReg16</a>*)0x460000FEUL)</td></tr>
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||
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<tr class="memdesc:a0a361d0a9e8311a29b6e545a6c0ae5d6"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Host Controller Version <br /></td></tr>
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<tr class="separator:a0a361d0a9e8311a29b6e545a6c0ae5d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a81e6acf57a91944319b102d9cae2449b"><td class="memItemLeft" align="right" valign="top"><a id="a81e6acf57a91944319b102d9cae2449b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a81e6acf57a91944319b102d9cae2449b">REG_SDHC1_MC1R</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x46000204UL)</td></tr>
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<tr class="memdesc:a81e6acf57a91944319b102d9cae2449b"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) MMC Control 1 <br /></td></tr>
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<tr class="separator:a81e6acf57a91944319b102d9cae2449b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b67d3d8a51088d71bfb61f1d79834df"><td class="memItemLeft" align="right" valign="top"><a id="a8b67d3d8a51088d71bfb61f1d79834df"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a8b67d3d8a51088d71bfb61f1d79834df">REG_SDHC1_MC2R</a>   (*(<a class="el" href="same54n19a_8h.html#a5e336e5a36ee12ebeafb021108e5275b">WoReg8</a> *)0x46000205UL)</td></tr>
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||
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<tr class="memdesc:a8b67d3d8a51088d71bfb61f1d79834df"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) MMC Control 2 <br /></td></tr>
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<tr class="separator:a8b67d3d8a51088d71bfb61f1d79834df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6e629d8fd6a6c7bff2e5fbdf64c1e120"><td class="memItemLeft" align="right" valign="top"><a id="a6e629d8fd6a6c7bff2e5fbdf64c1e120"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#a6e629d8fd6a6c7bff2e5fbdf64c1e120">REG_SDHC1_ACR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x46000208UL)</td></tr>
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<tr class="memdesc:a6e629d8fd6a6c7bff2e5fbdf64c1e120"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) AHB Control <br /></td></tr>
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<tr class="separator:a6e629d8fd6a6c7bff2e5fbdf64c1e120"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af30d449cd3b164982fbc15b9bde221d6"><td class="memItemLeft" align="right" valign="top"><a id="af30d449cd3b164982fbc15b9bde221d6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#af30d449cd3b164982fbc15b9bde221d6">REG_SDHC1_CC2R</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4600020CUL)</td></tr>
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||
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<tr class="memdesc:af30d449cd3b164982fbc15b9bde221d6"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Clock Control 2 <br /></td></tr>
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<tr class="separator:af30d449cd3b164982fbc15b9bde221d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abf0d1c263c97e3f5522f1c8b07b98c75"><td class="memItemLeft" align="right" valign="top"><a id="abf0d1c263c97e3f5522f1c8b07b98c75"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#abf0d1c263c97e3f5522f1c8b07b98c75">REG_SDHC1_CACR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x46000230UL)</td></tr>
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||
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<tr class="memdesc:abf0d1c263c97e3f5522f1c8b07b98c75"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Capabilities Control <br /></td></tr>
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<tr class="separator:abf0d1c263c97e3f5522f1c8b07b98c75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adc19835330fd733d0f06e56968dfd3f7"><td class="memItemLeft" align="right" valign="top"><a id="adc19835330fd733d0f06e56968dfd3f7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc1_8h.html#adc19835330fd733d0f06e56968dfd3f7">REG_SDHC1_DBGR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x46000234UL)</td></tr>
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||
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<tr class="memdesc:adc19835330fd733d0f06e56968dfd3f7"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC1) Debug <br /></td></tr>
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<tr class="separator:adc19835330fd733d0f06e56968dfd3f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaeffe8931549701886e400a25c5f8f98"><td class="memItemLeft" align="right" valign="top"><a id="aaeffe8931549701886e400a25c5f8f98"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC1_CARD_DATA_SIZE</b>   4</td></tr>
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<tr class="separator:aaeffe8931549701886e400a25c5f8f98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aabe45974c58625969bc304d72b89eddc"><td class="memItemLeft" align="right" valign="top"><a id="aabe45974c58625969bc304d72b89eddc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC1_CLK_AHB_ID</b>   16</td></tr>
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<tr class="separator:aabe45974c58625969bc304d72b89eddc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2a05f69b3a98c39b61d32fa6c24c66bc"><td class="memItemLeft" align="right" valign="top"><a id="a2a05f69b3a98c39b61d32fa6c24c66bc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC1_GCLK_ID</b>   46</td></tr>
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<tr class="separator:a2a05f69b3a98c39b61d32fa6c24c66bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8c21fe6e6577e94f4819b58d2497cfb6"><td class="memItemLeft" align="right" valign="top"><a id="a8c21fe6e6577e94f4819b58d2497cfb6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC1_GCLK_ID_SLOW</b>   3</td></tr>
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<tr class="separator:a8c21fe6e6577e94f4819b58d2497cfb6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeed143100ee1eba2db26f9d6fb53d03d"><td class="memItemLeft" align="right" valign="top"><a id="aeed143100ee1eba2db26f9d6fb53d03d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC1_NB_OF_DEVICES</b>   1</td></tr>
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<tr class="separator:aeed143100ee1eba2db26f9d6fb53d03d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a63e08034d08edf224cace625f51c6f04"><td class="memItemLeft" align="right" valign="top"><a id="a63e08034d08edf224cace625f51c6f04"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC1_NB_REG_PVR</b>   8</td></tr>
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<tr class="separator:a63e08034d08edf224cace625f51c6f04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a699f1e8def507128c5a23f99599cc2fe"><td class="memItemLeft" align="right" valign="top"><a id="a699f1e8def507128c5a23f99599cc2fe"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC1_NB_REG_RR</b>   4</td></tr>
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<tr class="separator:a699f1e8def507128c5a23f99599cc2fe"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
|
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<div class="textblock"><p>Instance description for SDHC1. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="sdhc1_8h_source.html">sdhc1.h</a>.</p>
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</div></div><!-- contents -->
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<!-- start footer part -->
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<hr class="footer"/><address class="footer"><small>
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Generated by <a href="http://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.8.20
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</small></address>
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</body>
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