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419 lines
54 KiB
HTML
419 lines
54 KiB
HTML
4 years ago
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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/sercom0.h File Reference</title>
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<div id="projectname">SAME54P20A Test Project
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<ul>
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<a href="#define-members">Macros</a> </div>
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<div class="title">sercom0.h File Reference</div> </div>
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<div class="contents">
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<p>Instance description for SERCOM0.
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<a href="#details">More...</a></p>
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<p><a href="sercom0_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:ad4b291b9277b5c9ea5c77701a623a6b5"><td class="memItemLeft" align="right" valign="top"><a id="ad4b291b9277b5c9ea5c77701a623a6b5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#ad4b291b9277b5c9ea5c77701a623a6b5">REG_SERCOM0_I2CM_CTRLA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003000UL)</td></tr>
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<tr class="memdesc:ad4b291b9277b5c9ea5c77701a623a6b5"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CM Control A <br /></td></tr>
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<tr class="separator:ad4b291b9277b5c9ea5c77701a623a6b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afeaa7c456d8525839deb406557a38869"><td class="memItemLeft" align="right" valign="top"><a id="afeaa7c456d8525839deb406557a38869"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#afeaa7c456d8525839deb406557a38869">REG_SERCOM0_I2CM_CTRLB</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003004UL)</td></tr>
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<tr class="memdesc:afeaa7c456d8525839deb406557a38869"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CM Control B <br /></td></tr>
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<tr class="separator:afeaa7c456d8525839deb406557a38869"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a364cf14dab67e650cb086902ebd2922a"><td class="memItemLeft" align="right" valign="top"><a id="a364cf14dab67e650cb086902ebd2922a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a364cf14dab67e650cb086902ebd2922a">REG_SERCOM0_I2CM_CTRLC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003008UL)</td></tr>
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<tr class="memdesc:a364cf14dab67e650cb086902ebd2922a"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CM Control C <br /></td></tr>
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<tr class="separator:a364cf14dab67e650cb086902ebd2922a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aabe802c56a36ee200bf5e507ae557d3d"><td class="memItemLeft" align="right" valign="top"><a id="aabe802c56a36ee200bf5e507ae557d3d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#aabe802c56a36ee200bf5e507ae557d3d">REG_SERCOM0_I2CM_BAUD</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4000300CUL)</td></tr>
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<tr class="memdesc:aabe802c56a36ee200bf5e507ae557d3d"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CM Baud Rate <br /></td></tr>
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<tr class="separator:aabe802c56a36ee200bf5e507ae557d3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4a6420da8fb423e9ada305607a4b3d67"><td class="memItemLeft" align="right" valign="top"><a id="a4a6420da8fb423e9ada305607a4b3d67"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a4a6420da8fb423e9ada305607a4b3d67">REG_SERCOM0_I2CM_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003014UL)</td></tr>
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<tr class="memdesc:a4a6420da8fb423e9ada305607a4b3d67"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CM Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:a4a6420da8fb423e9ada305607a4b3d67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8a3699b38b46d9ceee8aa8cf047c154d"><td class="memItemLeft" align="right" valign="top"><a id="a8a3699b38b46d9ceee8aa8cf047c154d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a8a3699b38b46d9ceee8aa8cf047c154d">REG_SERCOM0_I2CM_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003016UL)</td></tr>
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<tr class="memdesc:a8a3699b38b46d9ceee8aa8cf047c154d"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CM Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a8a3699b38b46d9ceee8aa8cf047c154d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aed271d62542f606284df63ba17a19653"><td class="memItemLeft" align="right" valign="top"><a id="aed271d62542f606284df63ba17a19653"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#aed271d62542f606284df63ba17a19653">REG_SERCOM0_I2CM_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003018UL)</td></tr>
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<tr class="memdesc:aed271d62542f606284df63ba17a19653"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CM Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:aed271d62542f606284df63ba17a19653"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad53bf6068cd3862c31b5452c8048bf32"><td class="memItemLeft" align="right" valign="top"><a id="ad53bf6068cd3862c31b5452c8048bf32"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#ad53bf6068cd3862c31b5452c8048bf32">REG_SERCOM0_I2CM_STATUS</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4000301AUL)</td></tr>
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<tr class="memdesc:ad53bf6068cd3862c31b5452c8048bf32"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CM Status <br /></td></tr>
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<tr class="separator:ad53bf6068cd3862c31b5452c8048bf32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a89819d5a3ca6fabe8ec8d603b541f3f7"><td class="memItemLeft" align="right" valign="top"><a id="a89819d5a3ca6fabe8ec8d603b541f3f7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a89819d5a3ca6fabe8ec8d603b541f3f7">REG_SERCOM0_I2CM_SYNCBUSY</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4000301CUL)</td></tr>
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<tr class="memdesc:a89819d5a3ca6fabe8ec8d603b541f3f7"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CM Synchronization Busy <br /></td></tr>
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<tr class="separator:a89819d5a3ca6fabe8ec8d603b541f3f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad4b538c07cd9afc7290c52dbe0d8838a"><td class="memItemLeft" align="right" valign="top"><a id="ad4b538c07cd9afc7290c52dbe0d8838a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#ad4b538c07cd9afc7290c52dbe0d8838a">REG_SERCOM0_I2CM_ADDR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003024UL)</td></tr>
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||
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<tr class="memdesc:ad4b538c07cd9afc7290c52dbe0d8838a"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CM Address <br /></td></tr>
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<tr class="separator:ad4b538c07cd9afc7290c52dbe0d8838a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afbdef519ca8b5dad1aabad1f34114545"><td class="memItemLeft" align="right" valign="top"><a id="afbdef519ca8b5dad1aabad1f34114545"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#afbdef519ca8b5dad1aabad1f34114545">REG_SERCOM0_I2CM_DATA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003028UL)</td></tr>
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<tr class="memdesc:afbdef519ca8b5dad1aabad1f34114545"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CM Data <br /></td></tr>
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<tr class="separator:afbdef519ca8b5dad1aabad1f34114545"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae4c47984edcb9ca7b8cedfc192d693c1"><td class="memItemLeft" align="right" valign="top"><a id="ae4c47984edcb9ca7b8cedfc192d693c1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#ae4c47984edcb9ca7b8cedfc192d693c1">REG_SERCOM0_I2CM_DBGCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003030UL)</td></tr>
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||
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<tr class="memdesc:ae4c47984edcb9ca7b8cedfc192d693c1"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CM Debug Control <br /></td></tr>
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<tr class="separator:ae4c47984edcb9ca7b8cedfc192d693c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaa1cd4825d7e9f61223bf3fba6410b6d"><td class="memItemLeft" align="right" valign="top"><a id="aaa1cd4825d7e9f61223bf3fba6410b6d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#aaa1cd4825d7e9f61223bf3fba6410b6d">REG_SERCOM0_I2CS_CTRLA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003000UL)</td></tr>
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<tr class="memdesc:aaa1cd4825d7e9f61223bf3fba6410b6d"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CS Control A <br /></td></tr>
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<tr class="separator:aaa1cd4825d7e9f61223bf3fba6410b6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a068302ea3dffbdecacc8f50f2d485dc0"><td class="memItemLeft" align="right" valign="top"><a id="a068302ea3dffbdecacc8f50f2d485dc0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a068302ea3dffbdecacc8f50f2d485dc0">REG_SERCOM0_I2CS_CTRLB</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003004UL)</td></tr>
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||
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<tr class="memdesc:a068302ea3dffbdecacc8f50f2d485dc0"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CS Control B <br /></td></tr>
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<tr class="separator:a068302ea3dffbdecacc8f50f2d485dc0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af116a0c3ac230afa10a15799fc3782f1"><td class="memItemLeft" align="right" valign="top"><a id="af116a0c3ac230afa10a15799fc3782f1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#af116a0c3ac230afa10a15799fc3782f1">REG_SERCOM0_I2CS_CTRLC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003008UL)</td></tr>
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||
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<tr class="memdesc:af116a0c3ac230afa10a15799fc3782f1"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CS Control C <br /></td></tr>
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<tr class="separator:af116a0c3ac230afa10a15799fc3782f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2d7c77381b32df9784869f0692b79374"><td class="memItemLeft" align="right" valign="top"><a id="a2d7c77381b32df9784869f0692b79374"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a2d7c77381b32df9784869f0692b79374">REG_SERCOM0_I2CS_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003014UL)</td></tr>
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<tr class="memdesc:a2d7c77381b32df9784869f0692b79374"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CS Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:a2d7c77381b32df9784869f0692b79374"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a41ba952e44b276ad1fa9eabbe4537b7c"><td class="memItemLeft" align="right" valign="top"><a id="a41ba952e44b276ad1fa9eabbe4537b7c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a41ba952e44b276ad1fa9eabbe4537b7c">REG_SERCOM0_I2CS_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003016UL)</td></tr>
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<tr class="memdesc:a41ba952e44b276ad1fa9eabbe4537b7c"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CS Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a41ba952e44b276ad1fa9eabbe4537b7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad808c665c2f1d940e07613c384278b5b"><td class="memItemLeft" align="right" valign="top"><a id="ad808c665c2f1d940e07613c384278b5b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#ad808c665c2f1d940e07613c384278b5b">REG_SERCOM0_I2CS_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003018UL)</td></tr>
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<tr class="memdesc:ad808c665c2f1d940e07613c384278b5b"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CS Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:ad808c665c2f1d940e07613c384278b5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa59fe9f46d29c1bc3234c0dbccaacb85"><td class="memItemLeft" align="right" valign="top"><a id="aa59fe9f46d29c1bc3234c0dbccaacb85"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#aa59fe9f46d29c1bc3234c0dbccaacb85">REG_SERCOM0_I2CS_STATUS</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4000301AUL)</td></tr>
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||
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<tr class="memdesc:aa59fe9f46d29c1bc3234c0dbccaacb85"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CS Status <br /></td></tr>
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<tr class="separator:aa59fe9f46d29c1bc3234c0dbccaacb85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a37f49740d3e544a90ff5c3d284c6e9a7"><td class="memItemLeft" align="right" valign="top"><a id="a37f49740d3e544a90ff5c3d284c6e9a7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a37f49740d3e544a90ff5c3d284c6e9a7">REG_SERCOM0_I2CS_SYNCBUSY</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4000301CUL)</td></tr>
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<tr class="memdesc:a37f49740d3e544a90ff5c3d284c6e9a7"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CS Synchronization Busy <br /></td></tr>
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<tr class="separator:a37f49740d3e544a90ff5c3d284c6e9a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2d13537b37a02e051ff3e31bf8115d87"><td class="memItemLeft" align="right" valign="top"><a id="a2d13537b37a02e051ff3e31bf8115d87"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a2d13537b37a02e051ff3e31bf8115d87">REG_SERCOM0_I2CS_LENGTH</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x40003022UL)</td></tr>
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<tr class="memdesc:a2d13537b37a02e051ff3e31bf8115d87"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CS Length <br /></td></tr>
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<tr class="separator:a2d13537b37a02e051ff3e31bf8115d87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a954a3808bf65119b3f7944a69a85121b"><td class="memItemLeft" align="right" valign="top"><a id="a954a3808bf65119b3f7944a69a85121b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a954a3808bf65119b3f7944a69a85121b">REG_SERCOM0_I2CS_ADDR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003024UL)</td></tr>
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<tr class="memdesc:a954a3808bf65119b3f7944a69a85121b"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CS Address <br /></td></tr>
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<tr class="separator:a954a3808bf65119b3f7944a69a85121b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2eb577465c1f3197c528e1228210f5c4"><td class="memItemLeft" align="right" valign="top"><a id="a2eb577465c1f3197c528e1228210f5c4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a2eb577465c1f3197c528e1228210f5c4">REG_SERCOM0_I2CS_DATA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003028UL)</td></tr>
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<tr class="memdesc:a2eb577465c1f3197c528e1228210f5c4"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) I2CS Data <br /></td></tr>
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<tr class="separator:a2eb577465c1f3197c528e1228210f5c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a611b0e64c4841c95dbfe30ead56687b7"><td class="memItemLeft" align="right" valign="top"><a id="a611b0e64c4841c95dbfe30ead56687b7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a611b0e64c4841c95dbfe30ead56687b7">REG_SERCOM0_SPI_CTRLA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003000UL)</td></tr>
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<tr class="memdesc:a611b0e64c4841c95dbfe30ead56687b7"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) SPI Control A <br /></td></tr>
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<tr class="separator:a611b0e64c4841c95dbfe30ead56687b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adb85a4cea9c13620e77145edf1f76bbf"><td class="memItemLeft" align="right" valign="top"><a id="adb85a4cea9c13620e77145edf1f76bbf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#adb85a4cea9c13620e77145edf1f76bbf">REG_SERCOM0_SPI_CTRLB</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003004UL)</td></tr>
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||
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<tr class="memdesc:adb85a4cea9c13620e77145edf1f76bbf"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) SPI Control B <br /></td></tr>
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<tr class="separator:adb85a4cea9c13620e77145edf1f76bbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a350c1d81e98806a39716e6e38096c014"><td class="memItemLeft" align="right" valign="top"><a id="a350c1d81e98806a39716e6e38096c014"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a350c1d81e98806a39716e6e38096c014">REG_SERCOM0_SPI_CTRLC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003008UL)</td></tr>
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<tr class="memdesc:a350c1d81e98806a39716e6e38096c014"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) SPI Control C <br /></td></tr>
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<tr class="separator:a350c1d81e98806a39716e6e38096c014"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad8be8e1f5afb52f404121c5962a57167"><td class="memItemLeft" align="right" valign="top"><a id="ad8be8e1f5afb52f404121c5962a57167"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#ad8be8e1f5afb52f404121c5962a57167">REG_SERCOM0_SPI_BAUD</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4000300CUL)</td></tr>
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||
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<tr class="memdesc:ad8be8e1f5afb52f404121c5962a57167"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) SPI Baud Rate <br /></td></tr>
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<tr class="separator:ad8be8e1f5afb52f404121c5962a57167"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a03cb35b2070c40442eef73597c2768e6"><td class="memItemLeft" align="right" valign="top"><a id="a03cb35b2070c40442eef73597c2768e6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a03cb35b2070c40442eef73597c2768e6">REG_SERCOM0_SPI_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003014UL)</td></tr>
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<tr class="memdesc:a03cb35b2070c40442eef73597c2768e6"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) SPI Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:a03cb35b2070c40442eef73597c2768e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a47365e88c4312db68754823a4637f520"><td class="memItemLeft" align="right" valign="top"><a id="a47365e88c4312db68754823a4637f520"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a47365e88c4312db68754823a4637f520">REG_SERCOM0_SPI_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003016UL)</td></tr>
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||
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<tr class="memdesc:a47365e88c4312db68754823a4637f520"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) SPI Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a47365e88c4312db68754823a4637f520"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab82e08af9f9471becf48bff27e5f5004"><td class="memItemLeft" align="right" valign="top"><a id="ab82e08af9f9471becf48bff27e5f5004"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#ab82e08af9f9471becf48bff27e5f5004">REG_SERCOM0_SPI_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003018UL)</td></tr>
|
||
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<tr class="memdesc:ab82e08af9f9471becf48bff27e5f5004"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) SPI Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:ab82e08af9f9471becf48bff27e5f5004"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad53d9d865862d4ffc424f0a5946c552c"><td class="memItemLeft" align="right" valign="top"><a id="ad53d9d865862d4ffc424f0a5946c552c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#ad53d9d865862d4ffc424f0a5946c552c">REG_SERCOM0_SPI_STATUS</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4000301AUL)</td></tr>
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||
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<tr class="memdesc:ad53d9d865862d4ffc424f0a5946c552c"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) SPI Status <br /></td></tr>
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<tr class="separator:ad53d9d865862d4ffc424f0a5946c552c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8d93a02b0c4d28dc08c6bdba63a52d0b"><td class="memItemLeft" align="right" valign="top"><a id="a8d93a02b0c4d28dc08c6bdba63a52d0b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a8d93a02b0c4d28dc08c6bdba63a52d0b">REG_SERCOM0_SPI_SYNCBUSY</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4000301CUL)</td></tr>
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||
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<tr class="memdesc:a8d93a02b0c4d28dc08c6bdba63a52d0b"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) SPI Synchronization Busy <br /></td></tr>
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<tr class="separator:a8d93a02b0c4d28dc08c6bdba63a52d0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1946252112eb2b053f9ddc2b60404c98"><td class="memItemLeft" align="right" valign="top"><a id="a1946252112eb2b053f9ddc2b60404c98"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a1946252112eb2b053f9ddc2b60404c98">REG_SERCOM0_SPI_LENGTH</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x40003022UL)</td></tr>
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<tr class="memdesc:a1946252112eb2b053f9ddc2b60404c98"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) SPI Length <br /></td></tr>
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<tr class="separator:a1946252112eb2b053f9ddc2b60404c98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adaa828a0e1ae130ac97f384545a2de10"><td class="memItemLeft" align="right" valign="top"><a id="adaa828a0e1ae130ac97f384545a2de10"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#adaa828a0e1ae130ac97f384545a2de10">REG_SERCOM0_SPI_ADDR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003024UL)</td></tr>
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||
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<tr class="memdesc:adaa828a0e1ae130ac97f384545a2de10"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) SPI Address <br /></td></tr>
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<tr class="separator:adaa828a0e1ae130ac97f384545a2de10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a925046e3fc54e1c40453d2b111f33ccb"><td class="memItemLeft" align="right" valign="top"><a id="a925046e3fc54e1c40453d2b111f33ccb"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a925046e3fc54e1c40453d2b111f33ccb">REG_SERCOM0_SPI_DATA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003028UL)</td></tr>
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||
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<tr class="memdesc:a925046e3fc54e1c40453d2b111f33ccb"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) SPI Data <br /></td></tr>
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<tr class="separator:a925046e3fc54e1c40453d2b111f33ccb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aab6f8a404a9629192d8ce167b6f00941"><td class="memItemLeft" align="right" valign="top"><a id="aab6f8a404a9629192d8ce167b6f00941"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#aab6f8a404a9629192d8ce167b6f00941">REG_SERCOM0_SPI_DBGCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003030UL)</td></tr>
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||
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<tr class="memdesc:aab6f8a404a9629192d8ce167b6f00941"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) SPI Debug Control <br /></td></tr>
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<tr class="separator:aab6f8a404a9629192d8ce167b6f00941"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab0cd4a33a08c5e9771bf891c1b5670f3"><td class="memItemLeft" align="right" valign="top"><a id="ab0cd4a33a08c5e9771bf891c1b5670f3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#ab0cd4a33a08c5e9771bf891c1b5670f3">REG_SERCOM0_USART_CTRLA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003000UL)</td></tr>
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||
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<tr class="memdesc:ab0cd4a33a08c5e9771bf891c1b5670f3"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Control A <br /></td></tr>
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<tr class="separator:ab0cd4a33a08c5e9771bf891c1b5670f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a04b6ce11e4ed4b1a60f67d04431565a9"><td class="memItemLeft" align="right" valign="top"><a id="a04b6ce11e4ed4b1a60f67d04431565a9"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a04b6ce11e4ed4b1a60f67d04431565a9">REG_SERCOM0_USART_CTRLB</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003004UL)</td></tr>
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||
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<tr class="memdesc:a04b6ce11e4ed4b1a60f67d04431565a9"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Control B <br /></td></tr>
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<tr class="separator:a04b6ce11e4ed4b1a60f67d04431565a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a48dafec85fab04635f8325f738f42d71"><td class="memItemLeft" align="right" valign="top"><a id="a48dafec85fab04635f8325f738f42d71"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a48dafec85fab04635f8325f738f42d71">REG_SERCOM0_USART_CTRLC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003008UL)</td></tr>
|
||
|
|
<tr class="memdesc:a48dafec85fab04635f8325f738f42d71"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Control C <br /></td></tr>
|
||
|
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<tr class="separator:a48dafec85fab04635f8325f738f42d71"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a5a4f3901ad67d099f2e75dcc010be132"><td class="memItemLeft" align="right" valign="top"><a id="a5a4f3901ad67d099f2e75dcc010be132"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a5a4f3901ad67d099f2e75dcc010be132">REG_SERCOM0_USART_BAUD</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4000300CUL)</td></tr>
|
||
|
|
<tr class="memdesc:a5a4f3901ad67d099f2e75dcc010be132"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Baud Rate <br /></td></tr>
|
||
|
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<tr class="separator:a5a4f3901ad67d099f2e75dcc010be132"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a2814e7df2e883da6643f55af730a24c3"><td class="memItemLeft" align="right" valign="top"><a id="a2814e7df2e883da6643f55af730a24c3"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a2814e7df2e883da6643f55af730a24c3">REG_SERCOM0_USART_RXPL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4000300EUL)</td></tr>
|
||
|
|
<tr class="memdesc:a2814e7df2e883da6643f55af730a24c3"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Receive Pulse Length <br /></td></tr>
|
||
|
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<tr class="separator:a2814e7df2e883da6643f55af730a24c3"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a5213dedbc00d79c4d52a996d01cbf588"><td class="memItemLeft" align="right" valign="top"><a id="a5213dedbc00d79c4d52a996d01cbf588"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a5213dedbc00d79c4d52a996d01cbf588">REG_SERCOM0_USART_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003014UL)</td></tr>
|
||
|
|
<tr class="memdesc:a5213dedbc00d79c4d52a996d01cbf588"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Interrupt Enable Clear <br /></td></tr>
|
||
|
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<tr class="separator:a5213dedbc00d79c4d52a996d01cbf588"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a5048732f2b797803f1f79b0b657b7fa1"><td class="memItemLeft" align="right" valign="top"><a id="a5048732f2b797803f1f79b0b657b7fa1"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a5048732f2b797803f1f79b0b657b7fa1">REG_SERCOM0_USART_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003016UL)</td></tr>
|
||
|
|
<tr class="memdesc:a5048732f2b797803f1f79b0b657b7fa1"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Interrupt Enable Set <br /></td></tr>
|
||
|
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<tr class="separator:a5048732f2b797803f1f79b0b657b7fa1"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab5ae69febae1d7c1f9923f6803ee7090"><td class="memItemLeft" align="right" valign="top"><a id="ab5ae69febae1d7c1f9923f6803ee7090"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#ab5ae69febae1d7c1f9923f6803ee7090">REG_SERCOM0_USART_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003018UL)</td></tr>
|
||
|
|
<tr class="memdesc:ab5ae69febae1d7c1f9923f6803ee7090"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Interrupt Flag Status and Clear <br /></td></tr>
|
||
|
|
<tr class="separator:ab5ae69febae1d7c1f9923f6803ee7090"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a9551ce1bb3b05df226d1cdac9c0b0e3d"><td class="memItemLeft" align="right" valign="top"><a id="a9551ce1bb3b05df226d1cdac9c0b0e3d"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a9551ce1bb3b05df226d1cdac9c0b0e3d">REG_SERCOM0_USART_STATUS</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4000301AUL)</td></tr>
|
||
|
|
<tr class="memdesc:a9551ce1bb3b05df226d1cdac9c0b0e3d"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Status <br /></td></tr>
|
||
|
|
<tr class="separator:a9551ce1bb3b05df226d1cdac9c0b0e3d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a61a9f25c2423d94b3c1d5352d7c16078"><td class="memItemLeft" align="right" valign="top"><a id="a61a9f25c2423d94b3c1d5352d7c16078"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a61a9f25c2423d94b3c1d5352d7c16078">REG_SERCOM0_USART_SYNCBUSY</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4000301CUL)</td></tr>
|
||
|
|
<tr class="memdesc:a61a9f25c2423d94b3c1d5352d7c16078"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Synchronization Busy <br /></td></tr>
|
||
|
|
<tr class="separator:a61a9f25c2423d94b3c1d5352d7c16078"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a390991d6f293f04d8346bf2a81a61889"><td class="memItemLeft" align="right" valign="top"><a id="a390991d6f293f04d8346bf2a81a61889"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a390991d6f293f04d8346bf2a81a61889">REG_SERCOM0_USART_RXERRCNT</a>   (*(<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> *)0x40003020UL)</td></tr>
|
||
|
|
<tr class="memdesc:a390991d6f293f04d8346bf2a81a61889"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Receive Error Count <br /></td></tr>
|
||
|
|
<tr class="separator:a390991d6f293f04d8346bf2a81a61889"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:afb98bd6c51aa314bd7dce3e742619160"><td class="memItemLeft" align="right" valign="top"><a id="afb98bd6c51aa314bd7dce3e742619160"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#afb98bd6c51aa314bd7dce3e742619160">REG_SERCOM0_USART_LENGTH</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x40003022UL)</td></tr>
|
||
|
|
<tr class="memdesc:afb98bd6c51aa314bd7dce3e742619160"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Length <br /></td></tr>
|
||
|
|
<tr class="separator:afb98bd6c51aa314bd7dce3e742619160"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a33dc7ce14fc276a6517eec4415337bfe"><td class="memItemLeft" align="right" valign="top"><a id="a33dc7ce14fc276a6517eec4415337bfe"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a33dc7ce14fc276a6517eec4415337bfe">REG_SERCOM0_USART_DATA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40003028UL)</td></tr>
|
||
|
|
<tr class="memdesc:a33dc7ce14fc276a6517eec4415337bfe"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Data <br /></td></tr>
|
||
|
|
<tr class="separator:a33dc7ce14fc276a6517eec4415337bfe"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a9ab3e7ff1ab77f452ccf225d7a42075c"><td class="memItemLeft" align="right" valign="top"><a id="a9ab3e7ff1ab77f452ccf225d7a42075c"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom0_8h.html#a9ab3e7ff1ab77f452ccf225d7a42075c">REG_SERCOM0_USART_DBGCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40003030UL)</td></tr>
|
||
|
|
<tr class="memdesc:a9ab3e7ff1ab77f452ccf225d7a42075c"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM0) USART Debug Control <br /></td></tr>
|
||
|
|
<tr class="separator:a9ab3e7ff1ab77f452ccf225d7a42075c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aaf8fd9fcadf057f97135c946788b592d"><td class="memItemLeft" align="right" valign="top"><a id="aaf8fd9fcadf057f97135c946788b592d"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_CLK_REDUCTION</b>   1</td></tr>
|
||
|
|
<tr class="separator:aaf8fd9fcadf057f97135c946788b592d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a81b4f7daf1819e1dcae4c7b36cedc554"><td class="memItemLeft" align="right" valign="top"><a id="a81b4f7daf1819e1dcae4c7b36cedc554"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_DLY_COMPENSATION</b>   1</td></tr>
|
||
|
|
<tr class="separator:a81b4f7daf1819e1dcae4c7b36cedc554"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a8b1aaff6e3a143d21c61957e8aa04576"><td class="memItemLeft" align="right" valign="top"><a id="a8b1aaff6e3a143d21c61957e8aa04576"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_DMA</b>   1</td></tr>
|
||
|
|
<tr class="separator:a8b1aaff6e3a143d21c61957e8aa04576"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab5613175d987b32d775857976f6ab457"><td class="memItemLeft" align="right" valign="top"><a id="ab5613175d987b32d775857976f6ab457"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_DMAC_ID_RX</b>   4</td></tr>
|
||
|
|
<tr class="separator:ab5613175d987b32d775857976f6ab457"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a365bf9ad932c1ae4fec249bb03a5e886"><td class="memItemLeft" align="right" valign="top"><a id="a365bf9ad932c1ae4fec249bb03a5e886"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_DMAC_ID_TX</b>   5</td></tr>
|
||
|
|
<tr class="separator:a365bf9ad932c1ae4fec249bb03a5e886"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a6f19d02761d005ad2de14ed75cdf76f6"><td class="memItemLeft" align="right" valign="top"><a id="a6f19d02761d005ad2de14ed75cdf76f6"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_FIFO_DEPTH_POWER</b>   1</td></tr>
|
||
|
|
<tr class="separator:a6f19d02761d005ad2de14ed75cdf76f6"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a1e023f1dfde432bc8fff67c735136d35"><td class="memItemLeft" align="right" valign="top"><a id="a1e023f1dfde432bc8fff67c735136d35"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_GCLK_ID_CORE</b>   7</td></tr>
|
||
|
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<tr class="separator:a1e023f1dfde432bc8fff67c735136d35"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ac7af828d156477300caf5a01bbf6584b"><td class="memItemLeft" align="right" valign="top"><a id="ac7af828d156477300caf5a01bbf6584b"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_GCLK_ID_SLOW</b>   3</td></tr>
|
||
|
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<tr class="separator:ac7af828d156477300caf5a01bbf6584b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab5e0a885e41aabe050e478311afff073"><td class="memItemLeft" align="right" valign="top"><a id="ab5e0a885e41aabe050e478311afff073"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_INT_MSB</b>   6</td></tr>
|
||
|
|
<tr class="separator:ab5e0a885e41aabe050e478311afff073"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aa92a9fe5675137a743e387a36b37a30b"><td class="memItemLeft" align="right" valign="top"><a id="aa92a9fe5675137a743e387a36b37a30b"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_I2CM</b>   1</td></tr>
|
||
|
|
<tr class="separator:aa92a9fe5675137a743e387a36b37a30b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a17778040df9baf389a0c1b7abe30c72d"><td class="memItemLeft" align="right" valign="top"><a id="a17778040df9baf389a0c1b7abe30c72d"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_I2CS</b>   1</td></tr>
|
||
|
|
<tr class="separator:a17778040df9baf389a0c1b7abe30c72d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a02747abcb7f4f83e304ead0dc79ad29b"><td class="memItemLeft" align="right" valign="top"><a id="a02747abcb7f4f83e304ead0dc79ad29b"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_I2CS_AUTO_ACK</b>   1</td></tr>
|
||
|
|
<tr class="separator:a02747abcb7f4f83e304ead0dc79ad29b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:abb67b322e0c43e946b5f4d4319ef4fa4"><td class="memItemLeft" align="right" valign="top"><a id="abb67b322e0c43e946b5f4d4319ef4fa4"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_I2CS_GROUP_CMD</b>   1</td></tr>
|
||
|
|
<tr class="separator:abb67b322e0c43e946b5f4d4319ef4fa4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a041f94e0dacd56a3d35d7dea47681b5c"><td class="memItemLeft" align="right" valign="top"><a id="a041f94e0dacd56a3d35d7dea47681b5c"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_I2CS_SDASETUP_CNT_SIZE</b>   8</td></tr>
|
||
|
|
<tr class="separator:a041f94e0dacd56a3d35d7dea47681b5c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a1ae408661695abd5c8f24693b21e81ff"><td class="memItemLeft" align="right" valign="top"><a id="a1ae408661695abd5c8f24693b21e81ff"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_I2CS_SDASETUP_SIZE</b>   4</td></tr>
|
||
|
|
<tr class="separator:a1ae408661695abd5c8f24693b21e81ff"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a74381b04e9726b41e8a03f4e571837d4"><td class="memItemLeft" align="right" valign="top"><a id="a74381b04e9726b41e8a03f4e571837d4"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_I2CS_SUDAT</b>   1</td></tr>
|
||
|
|
<tr class="separator:a74381b04e9726b41e8a03f4e571837d4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ac42c1e0762cdf29e6217d999d2093d81"><td class="memItemLeft" align="right" valign="top"><a id="ac42c1e0762cdf29e6217d999d2093d81"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_I2C_FASTMP</b>   1</td></tr>
|
||
|
|
<tr class="separator:ac42c1e0762cdf29e6217d999d2093d81"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a429f11336c526b01778b4a079e51996e"><td class="memItemLeft" align="right" valign="top"><a id="a429f11336c526b01778b4a079e51996e"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_I2C_HSMODE</b>   1</td></tr>
|
||
|
|
<tr class="separator:a429f11336c526b01778b4a079e51996e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a7578c6ff3cbd76ea14603a9c1891ed0b"><td class="memItemLeft" align="right" valign="top"><a id="a7578c6ff3cbd76ea14603a9c1891ed0b"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_I2C_SCLSM_MODE</b>   1</td></tr>
|
||
|
|
<tr class="separator:a7578c6ff3cbd76ea14603a9c1891ed0b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab8accaeaf0341b33ca6ce9c027284f37"><td class="memItemLeft" align="right" valign="top"><a id="ab8accaeaf0341b33ca6ce9c027284f37"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_I2C_SMB_TIMEOUTS</b>   1</td></tr>
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<tr class="separator:ab8accaeaf0341b33ca6ce9c027284f37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adc60e6f8f15993e92e9a83b0030e75d7"><td class="memItemLeft" align="right" valign="top"><a id="adc60e6f8f15993e92e9a83b0030e75d7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_I2C_TENBIT_ADR</b>   1</td></tr>
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<tr class="separator:adc60e6f8f15993e92e9a83b0030e75d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a88ae5313598e994fadc6618195b0b143"><td class="memItemLeft" align="right" valign="top"><a id="a88ae5313598e994fadc6618195b0b143"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_PMSB</b>   3</td></tr>
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<tr class="separator:a88ae5313598e994fadc6618195b0b143"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a95fd697a4727df0a06f5eb4577a424db"><td class="memItemLeft" align="right" valign="top"><a id="a95fd697a4727df0a06f5eb4577a424db"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_RETENTION_SUPPORT</b>   0</td></tr>
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<tr class="separator:a95fd697a4727df0a06f5eb4577a424db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3797d6c184138cb54504f901a7a32899"><td class="memItemLeft" align="right" valign="top"><a id="a3797d6c184138cb54504f901a7a32899"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_SE_CNT</b>   1</td></tr>
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<tr class="separator:a3797d6c184138cb54504f901a7a32899"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a863815836ca2780a8546a50c1133845d"><td class="memItemLeft" align="right" valign="top"><a id="a863815836ca2780a8546a50c1133845d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_SPI</b>   1</td></tr>
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<tr class="separator:a863815836ca2780a8546a50c1133845d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a41f716d61f6b7092bae5cce3e01da144"><td class="memItemLeft" align="right" valign="top"><a id="a41f716d61f6b7092bae5cce3e01da144"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_SPI_HW_SS_CTRL</b>   1</td></tr>
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<tr class="separator:a41f716d61f6b7092bae5cce3e01da144"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b914b5f30c8db83b4d52b97b405476c"><td class="memItemLeft" align="right" valign="top"><a id="a8b914b5f30c8db83b4d52b97b405476c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_SPI_ICSPACE_EXT</b>   1</td></tr>
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<tr class="separator:a8b914b5f30c8db83b4d52b97b405476c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b42934c56d9ca9825819f4dcb34907f"><td class="memItemLeft" align="right" valign="top"><a id="a8b42934c56d9ca9825819f4dcb34907f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_SPI_OZMO</b>   0</td></tr>
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<tr class="separator:a8b42934c56d9ca9825819f4dcb34907f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af9c2f7ca4a62e3b79129ba0ef010ddc7"><td class="memItemLeft" align="right" valign="top"><a id="af9c2f7ca4a62e3b79129ba0ef010ddc7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_SPI_WAKE_ON_SSL</b>   1</td></tr>
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<tr class="separator:af9c2f7ca4a62e3b79129ba0ef010ddc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a46acd3e2d8ba9db01e55e6e50010ca55"><td class="memItemLeft" align="right" valign="top"><a id="a46acd3e2d8ba9db01e55e6e50010ca55"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_TTBIT_EXTENSION</b>   1</td></tr>
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<tr class="separator:a46acd3e2d8ba9db01e55e6e50010ca55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acb88821fdabaad4c0f4c4ed8aee9755e"><td class="memItemLeft" align="right" valign="top"><a id="acb88821fdabaad4c0f4c4ed8aee9755e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_USART</b>   1</td></tr>
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<tr class="separator:acb88821fdabaad4c0f4c4ed8aee9755e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a44e91a17f708614101d1978f5769321d"><td class="memItemLeft" align="right" valign="top"><a id="a44e91a17f708614101d1978f5769321d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_USART_AUTOBAUD</b>   1</td></tr>
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<tr class="separator:a44e91a17f708614101d1978f5769321d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a54f6252ceb14e4dd953fdf3af6bbc0ce"><td class="memItemLeft" align="right" valign="top"><a id="a54f6252ceb14e4dd953fdf3af6bbc0ce"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_USART_COLDET</b>   1</td></tr>
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<tr class="separator:a54f6252ceb14e4dd953fdf3af6bbc0ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a68f87c3247234960184ba62f035db628"><td class="memItemLeft" align="right" valign="top"><a id="a68f87c3247234960184ba62f035db628"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_USART_FLOW_CTRL</b>   1</td></tr>
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<tr class="separator:a68f87c3247234960184ba62f035db628"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a32b83f9b3786a043fe4d6d1054875c5e"><td class="memItemLeft" align="right" valign="top"><a id="a32b83f9b3786a043fe4d6d1054875c5e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_USART_FRAC_BAUD</b>   1</td></tr>
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<tr class="separator:a32b83f9b3786a043fe4d6d1054875c5e"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a9abe2d281e7adfae33b374d324c37326"><td class="memItemLeft" align="right" valign="top"><a id="a9abe2d281e7adfae33b374d324c37326"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_USART_IRDA</b>   1</td></tr>
|
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<tr class="separator:a9abe2d281e7adfae33b374d324c37326"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a3be75a264d971d05326033e8146404a4"><td class="memItemLeft" align="right" valign="top"><a id="a3be75a264d971d05326033e8146404a4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_USART_ISO7816</b>   1</td></tr>
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<tr class="separator:a3be75a264d971d05326033e8146404a4"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ad315cee3b8f04bfdea8aa1dc317b976b"><td class="memItemLeft" align="right" valign="top"><a id="ad315cee3b8f04bfdea8aa1dc317b976b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_USART_LIN_MASTER</b>   1</td></tr>
|
||
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<tr class="separator:ad315cee3b8f04bfdea8aa1dc317b976b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a72632b1f3ab25f9643714ebb74a7e5f4"><td class="memItemLeft" align="right" valign="top"><a id="a72632b1f3ab25f9643714ebb74a7e5f4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_USART_RS485</b>   1</td></tr>
|
||
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<tr class="separator:a72632b1f3ab25f9643714ebb74a7e5f4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a3735173a6e9842f57cd6f881e384a5e5"><td class="memItemLeft" align="right" valign="top"><a id="a3735173a6e9842f57cd6f881e384a5e5"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_USART_SAMPA_EXT</b>   1</td></tr>
|
||
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<tr class="separator:a3735173a6e9842f57cd6f881e384a5e5"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aada4a62817e7f8018d9b2b999073940f"><td class="memItemLeft" align="right" valign="top"><a id="aada4a62817e7f8018d9b2b999073940f"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM0_USART_SAMPR_EXT</b>   1</td></tr>
|
||
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<tr class="separator:aada4a62817e7f8018d9b2b999073940f"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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</table>
|
||
|
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
|
||
|
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<div class="textblock"><p>Instance description for SERCOM0. </p>
|
||
|
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
|
||
|
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<p>\asf_license_start </p>
|
||
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|
||
|
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<p class="definition">Definition in file <a class="el" href="sercom0_8h_source.html">sercom0.h</a>.</p>
|
||
|
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</div></div><!-- contents -->
|
||
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<!-- start footer part -->
|
||
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<hr class="footer"/><address class="footer"><small>
|
||
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Generated by <a href="http://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.8.20
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</small></address>
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||
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</body>
|
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</html>
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