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206 lines
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4 years ago
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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/dac.h File Reference</title>
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<a href="#define-members">Macros</a> </div>
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<div class="title">dac.h File Reference</div> </div>
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<div class="contents">
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<p>Instance description for DAC.
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<a href="#details">More...</a></p>
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<p><a href="instance_2dac_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a5699fa7b80f1ae2c4e9611548c1fe3c1"><td class="memItemLeft" align="right" valign="top"><a id="a5699fa7b80f1ae2c4e9611548c1fe3c1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#a5699fa7b80f1ae2c4e9611548c1fe3c1">REG_DAC_CTRLA</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43002400UL)</td></tr>
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<tr class="memdesc:a5699fa7b80f1ae2c4e9611548c1fe3c1"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) Control A <br /></td></tr>
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<tr class="separator:a5699fa7b80f1ae2c4e9611548c1fe3c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a322393d1d023012f89e4235d7acec17a"><td class="memItemLeft" align="right" valign="top"><a id="a322393d1d023012f89e4235d7acec17a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#a322393d1d023012f89e4235d7acec17a">REG_DAC_CTRLB</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43002401UL)</td></tr>
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<tr class="memdesc:a322393d1d023012f89e4235d7acec17a"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) Control B <br /></td></tr>
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<tr class="separator:a322393d1d023012f89e4235d7acec17a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3b1adf492342d95b0e27046e6ebeab9b"><td class="memItemLeft" align="right" valign="top"><a id="a3b1adf492342d95b0e27046e6ebeab9b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#a3b1adf492342d95b0e27046e6ebeab9b">REG_DAC_EVCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43002402UL)</td></tr>
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<tr class="memdesc:a3b1adf492342d95b0e27046e6ebeab9b"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) Event Control <br /></td></tr>
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<tr class="separator:a3b1adf492342d95b0e27046e6ebeab9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7aaf07eac55924ef717595282722bced"><td class="memItemLeft" align="right" valign="top"><a id="a7aaf07eac55924ef717595282722bced"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#a7aaf07eac55924ef717595282722bced">REG_DAC_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43002404UL)</td></tr>
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<tr class="memdesc:a7aaf07eac55924ef717595282722bced"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:a7aaf07eac55924ef717595282722bced"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad3964a77af25d3f3f6e6e491b44181af"><td class="memItemLeft" align="right" valign="top"><a id="ad3964a77af25d3f3f6e6e491b44181af"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#ad3964a77af25d3f3f6e6e491b44181af">REG_DAC_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43002405UL)</td></tr>
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<tr class="memdesc:ad3964a77af25d3f3f6e6e491b44181af"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) Interrupt Enable Set <br /></td></tr>
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<tr class="separator:ad3964a77af25d3f3f6e6e491b44181af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab86a1fc63a3458b14273128fcc98207c"><td class="memItemLeft" align="right" valign="top"><a id="ab86a1fc63a3458b14273128fcc98207c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#ab86a1fc63a3458b14273128fcc98207c">REG_DAC_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43002406UL)</td></tr>
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<tr class="memdesc:ab86a1fc63a3458b14273128fcc98207c"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:ab86a1fc63a3458b14273128fcc98207c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab18777fc13e36281ca757e4686463406"><td class="memItemLeft" align="right" valign="top"><a id="ab18777fc13e36281ca757e4686463406"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#ab18777fc13e36281ca757e4686463406">REG_DAC_STATUS</a>   (*(<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> *)0x43002407UL)</td></tr>
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<tr class="memdesc:ab18777fc13e36281ca757e4686463406"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) Status <br /></td></tr>
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<tr class="separator:ab18777fc13e36281ca757e4686463406"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2e4f6383a3ee511167567dc6ddceb059"><td class="memItemLeft" align="right" valign="top"><a id="a2e4f6383a3ee511167567dc6ddceb059"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#a2e4f6383a3ee511167567dc6ddceb059">REG_DAC_SYNCBUSY</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x43002408UL)</td></tr>
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<tr class="memdesc:a2e4f6383a3ee511167567dc6ddceb059"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) Synchronization Busy <br /></td></tr>
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<tr class="separator:a2e4f6383a3ee511167567dc6ddceb059"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aae12ac3d0074eb9f29237c6438df468e"><td class="memItemLeft" align="right" valign="top"><a id="aae12ac3d0074eb9f29237c6438df468e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#aae12ac3d0074eb9f29237c6438df468e">REG_DAC_DACCTRL0</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4300240CUL)</td></tr>
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<tr class="memdesc:aae12ac3d0074eb9f29237c6438df468e"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) DAC 0 Control <br /></td></tr>
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<tr class="separator:aae12ac3d0074eb9f29237c6438df468e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adadb258625d188e1e1043d24908e6168"><td class="memItemLeft" align="right" valign="top"><a id="adadb258625d188e1e1043d24908e6168"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#adadb258625d188e1e1043d24908e6168">REG_DAC_DACCTRL1</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4300240EUL)</td></tr>
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<tr class="memdesc:adadb258625d188e1e1043d24908e6168"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) DAC 1 Control <br /></td></tr>
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<tr class="separator:adadb258625d188e1e1043d24908e6168"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7b5b397c05785c0440c90ee679b96b0f"><td class="memItemLeft" align="right" valign="top"><a id="a7b5b397c05785c0440c90ee679b96b0f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#a7b5b397c05785c0440c90ee679b96b0f">REG_DAC_DATA0</a>   (*(<a class="el" href="same54n19a_8h.html#a0ab0e5f6c8301aa1c2068e511d854094">WoReg16</a>*)0x43002410UL)</td></tr>
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<tr class="memdesc:a7b5b397c05785c0440c90ee679b96b0f"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) DAC 0 Data <br /></td></tr>
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<tr class="separator:a7b5b397c05785c0440c90ee679b96b0f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a483b3f4929f0c65e0d0d28ed97047075"><td class="memItemLeft" align="right" valign="top"><a id="a483b3f4929f0c65e0d0d28ed97047075"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#a483b3f4929f0c65e0d0d28ed97047075">REG_DAC_DATA1</a>   (*(<a class="el" href="same54n19a_8h.html#a0ab0e5f6c8301aa1c2068e511d854094">WoReg16</a>*)0x43002412UL)</td></tr>
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<tr class="memdesc:a483b3f4929f0c65e0d0d28ed97047075"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) DAC 1 Data <br /></td></tr>
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<tr class="separator:a483b3f4929f0c65e0d0d28ed97047075"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af64c12f023a2ad2995c2d773a75c5e78"><td class="memItemLeft" align="right" valign="top"><a id="af64c12f023a2ad2995c2d773a75c5e78"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#af64c12f023a2ad2995c2d773a75c5e78">REG_DAC_DATABUF0</a>   (*(<a class="el" href="same54n19a_8h.html#a0ab0e5f6c8301aa1c2068e511d854094">WoReg16</a>*)0x43002414UL)</td></tr>
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<tr class="memdesc:af64c12f023a2ad2995c2d773a75c5e78"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) DAC 0 Data Buffer <br /></td></tr>
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<tr class="separator:af64c12f023a2ad2995c2d773a75c5e78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2f9713d6a4cf390a50cec15a0f3f0f81"><td class="memItemLeft" align="right" valign="top"><a id="a2f9713d6a4cf390a50cec15a0f3f0f81"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#a2f9713d6a4cf390a50cec15a0f3f0f81">REG_DAC_DATABUF1</a>   (*(<a class="el" href="same54n19a_8h.html#a0ab0e5f6c8301aa1c2068e511d854094">WoReg16</a>*)0x43002416UL)</td></tr>
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<tr class="memdesc:a2f9713d6a4cf390a50cec15a0f3f0f81"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) DAC 1 Data Buffer <br /></td></tr>
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<tr class="separator:a2f9713d6a4cf390a50cec15a0f3f0f81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a05a15d737324974ff86c7fea415406f9"><td class="memItemLeft" align="right" valign="top"><a id="a05a15d737324974ff86c7fea415406f9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#a05a15d737324974ff86c7fea415406f9">REG_DAC_DBGCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43002418UL)</td></tr>
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<tr class="memdesc:a05a15d737324974ff86c7fea415406f9"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) Debug Control <br /></td></tr>
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<tr class="separator:a05a15d737324974ff86c7fea415406f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2f7e75215b1564476796b1f6e851b2b6"><td class="memItemLeft" align="right" valign="top"><a id="a2f7e75215b1564476796b1f6e851b2b6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#a2f7e75215b1564476796b1f6e851b2b6">REG_DAC_RESULT0</a>   (*(<a class="el" href="same54n19a_8h.html#aebf6e33c2d49a802e06e22a95ea9d0d0">RoReg16</a>*)0x4300241CUL)</td></tr>
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<tr class="memdesc:a2f7e75215b1564476796b1f6e851b2b6"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) Filter Result 0 <br /></td></tr>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dac_8h.html#a2231e8cbbe682c0dc8e174b0bf29ab32">REG_DAC_RESULT1</a>   (*(<a class="el" href="same54n19a_8h.html#aebf6e33c2d49a802e06e22a95ea9d0d0">RoReg16</a>*)0x4300241EUL)</td></tr>
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<tr class="memdesc:a2231e8cbbe682c0dc8e174b0bf29ab32"><td class="mdescLeft"> </td><td class="mdescRight">(DAC) Filter Result 1 <br /></td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_CHANNEL_SIZE</b>   2</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_DATA_SIZE</b>   12</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_DMAC_ID_EMPTY_0</b>   72</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_DMAC_ID_EMPTY_1</b>   73</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_DMAC_ID_EMPTY_LSB</b>   72</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_DMAC_ID_EMPTY_MSB</b>   73</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_DMAC_ID_EMPTY_SIZE</b>   2</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_DMAC_ID_RESRDY_0</b>   74</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_DMAC_ID_RESRDY_1</b>   75</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_DMAC_ID_RESRDY_LSB</b>   74</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_DMAC_ID_RESRDY_MSB</b>   75</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_DMAC_ID_RESRDY_SIZE</b>   2</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_GCLK_ID</b>   42</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DAC_STEP</b>   7</td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for DAC. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="instance_2dac_8h_source.html">dac.h</a>.</p>
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</small></address>
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