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780 lines
89 KiB
C
780 lines
89 KiB
C
4 years ago
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/**
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* \brief Component description for DMAC
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2019-11-25T06:55:46Z */
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#ifndef _SAMD21_DMAC_COMPONENT_H_
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#define _SAMD21_DMAC_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR DMAC */
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/* ************************************************************************** */
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/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
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#define DMAC_BTCTRL_RESETVALUE _U_(0x00) /**< (DMAC_BTCTRL) Block Transfer Control Reset Value */
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#define DMAC_BTCTRL_VALID_Pos _U_(0) /**< (DMAC_BTCTRL) Descriptor Valid Position */
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#define DMAC_BTCTRL_VALID_Msk (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) /**< (DMAC_BTCTRL) Descriptor Valid Mask */
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#define DMAC_BTCTRL_VALID(value) (DMAC_BTCTRL_VALID_Msk & ((value) << DMAC_BTCTRL_VALID_Pos))
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#define DMAC_BTCTRL_EVOSEL_Pos _U_(1) /**< (DMAC_BTCTRL) Event Output Selection Position */
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#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Event Output Selection Mask */
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#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
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#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< (DMAC_BTCTRL) Event generation disabled */
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#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< (DMAC_BTCTRL) Event strobe when block transfer complete */
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#define DMAC_BTCTRL_EVOSEL_BEAT_Val _U_(0x3) /**< (DMAC_BTCTRL) Event strobe when beat transfer complete */
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#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Event generation disabled Position */
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#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Event strobe when block transfer complete Position */
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#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Event strobe when beat transfer complete Position */
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#define DMAC_BTCTRL_BLOCKACT_Pos _U_(3) /**< (DMAC_BTCTRL) Block Action Position */
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#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Block Action Mask */
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#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
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#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< (DMAC_BTCTRL) No action */
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#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< (DMAC_BTCTRL) Channel in normal operation and block interrupt */
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#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< (DMAC_BTCTRL) Channel suspend operation is completed */
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#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
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#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) No action Position */
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#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Channel in normal operation and block interrupt Position */
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#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Channel suspend operation is completed Position */
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#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Both channel suspend operation and block interrupt Position */
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#define DMAC_BTCTRL_BEATSIZE_Pos _U_(8) /**< (DMAC_BTCTRL) Beat Size Position */
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#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) Beat Size Mask */
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#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
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#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< (DMAC_BTCTRL) 8-bit access */
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#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< (DMAC_BTCTRL) 16-bit access */
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#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< (DMAC_BTCTRL) 32-bit access */
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#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) 8-bit access Position */
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#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) 16-bit access Position */
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#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) 32-bit access Position */
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#define DMAC_BTCTRL_SRCINC_Pos _U_(10) /**< (DMAC_BTCTRL) Source Address Increment Enable Position */
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#define DMAC_BTCTRL_SRCINC_Msk (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) /**< (DMAC_BTCTRL) Source Address Increment Enable Mask */
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#define DMAC_BTCTRL_SRCINC(value) (DMAC_BTCTRL_SRCINC_Msk & ((value) << DMAC_BTCTRL_SRCINC_Pos))
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#define DMAC_BTCTRL_DSTINC_Pos _U_(11) /**< (DMAC_BTCTRL) Destination Address Increment Enable Position */
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#define DMAC_BTCTRL_DSTINC_Msk (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) /**< (DMAC_BTCTRL) Destination Address Increment Enable Mask */
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#define DMAC_BTCTRL_DSTINC(value) (DMAC_BTCTRL_DSTINC_Msk & ((value) << DMAC_BTCTRL_DSTINC_Pos))
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#define DMAC_BTCTRL_STEPSEL_Pos _U_(12) /**< (DMAC_BTCTRL) Step Selection Position */
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#define DMAC_BTCTRL_STEPSEL_Msk (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) /**< (DMAC_BTCTRL) Step Selection Mask */
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#define DMAC_BTCTRL_STEPSEL(value) (DMAC_BTCTRL_STEPSEL_Msk & ((value) << DMAC_BTCTRL_STEPSEL_Pos))
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#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< (DMAC_BTCTRL) Step size settings apply to the destination address */
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#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< (DMAC_BTCTRL) Step size settings apply to the source address */
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#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) /**< (DMAC_BTCTRL) Step size settings apply to the destination address Position */
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#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) /**< (DMAC_BTCTRL) Step size settings apply to the source address Position */
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#define DMAC_BTCTRL_STEPSIZE_Pos _U_(13) /**< (DMAC_BTCTRL) Address Increment Step Size Position */
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#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) /**< (DMAC_BTCTRL) Address Increment Step Size Mask */
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#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
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#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 1 */
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#define DMAC_BTCTRL_STEPSIZE_X2_Val _U_(0x1) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 2 */
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#define DMAC_BTCTRL_STEPSIZE_X4_Val _U_(0x2) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 4 */
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#define DMAC_BTCTRL_STEPSIZE_X8_Val _U_(0x3) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 8 */
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#define DMAC_BTCTRL_STEPSIZE_X16_Val _U_(0x4) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 16 */
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#define DMAC_BTCTRL_STEPSIZE_X32_Val _U_(0x5) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 32 */
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#define DMAC_BTCTRL_STEPSIZE_X64_Val _U_(0x6) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 64 */
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#define DMAC_BTCTRL_STEPSIZE_X128_Val _U_(0x7) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 128 */
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#define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 1 Position */
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#define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 2 Position */
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#define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 4 Position */
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#define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 8 Position */
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#define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 16 Position */
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#define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 32 Position */
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#define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 64 Position */
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#define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos) /**< (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 128 Position */
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#define DMAC_BTCTRL_Msk _U_(0xFF1F) /**< (DMAC_BTCTRL) Register Mask */
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/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
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#define DMAC_BTCNT_BTCNT_Pos _U_(0) /**< (DMAC_BTCNT) Block Transfer Count Position */
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#define DMAC_BTCNT_BTCNT_Msk (_U_(0xFFFF) << DMAC_BTCNT_BTCNT_Pos) /**< (DMAC_BTCNT) Block Transfer Count Mask */
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#define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
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#define DMAC_BTCNT_Msk _U_(0xFFFF) /**< (DMAC_BTCNT) Register Mask */
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/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
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#define DMAC_SRCADDR_SRCADDR_Pos _U_(0) /**< (DMAC_SRCADDR) Transfer Source Address Position */
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#define DMAC_SRCADDR_SRCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos) /**< (DMAC_SRCADDR) Transfer Source Address Mask */
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#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
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#define DMAC_SRCADDR_Msk _U_(0xFFFFFFFF) /**< (DMAC_SRCADDR) Register Mask */
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/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
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#define DMAC_DSTADDR_DSTADDR_Pos _U_(0) /**< (DMAC_DSTADDR) Transfer Destination Address Position */
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#define DMAC_DSTADDR_DSTADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos) /**< (DMAC_DSTADDR) Transfer Destination Address Mask */
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#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
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#define DMAC_DSTADDR_Msk _U_(0xFFFFFFFF) /**< (DMAC_DSTADDR) Register Mask */
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/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
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#define DMAC_DESCADDR_DESCADDR_Pos _U_(0) /**< (DMAC_DESCADDR) Next Descriptor Address Position */
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#define DMAC_DESCADDR_DESCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos) /**< (DMAC_DESCADDR) Next Descriptor Address Mask */
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#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
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#define DMAC_DESCADDR_Msk _U_(0xFFFFFFFF) /**< (DMAC_DESCADDR) Register Mask */
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/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
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#define DMAC_CTRL_RESETVALUE _U_(0x00) /**< (DMAC_CTRL) Control Reset Value */
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#define DMAC_CTRL_SWRST_Pos _U_(0) /**< (DMAC_CTRL) Software Reset Position */
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#define DMAC_CTRL_SWRST_Msk (_U_(0x1) << DMAC_CTRL_SWRST_Pos) /**< (DMAC_CTRL) Software Reset Mask */
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#define DMAC_CTRL_SWRST(value) (DMAC_CTRL_SWRST_Msk & ((value) << DMAC_CTRL_SWRST_Pos))
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#define DMAC_CTRL_DMAENABLE_Pos _U_(1) /**< (DMAC_CTRL) DMA Enable Position */
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#define DMAC_CTRL_DMAENABLE_Msk (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos) /**< (DMAC_CTRL) DMA Enable Mask */
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#define DMAC_CTRL_DMAENABLE(value) (DMAC_CTRL_DMAENABLE_Msk & ((value) << DMAC_CTRL_DMAENABLE_Pos))
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#define DMAC_CTRL_CRCENABLE_Pos _U_(2) /**< (DMAC_CTRL) CRC Enable Position */
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#define DMAC_CTRL_CRCENABLE_Msk (_U_(0x1) << DMAC_CTRL_CRCENABLE_Pos) /**< (DMAC_CTRL) CRC Enable Mask */
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#define DMAC_CTRL_CRCENABLE(value) (DMAC_CTRL_CRCENABLE_Msk & ((value) << DMAC_CTRL_CRCENABLE_Pos))
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#define DMAC_CTRL_LVLEN0_Pos _U_(8) /**< (DMAC_CTRL) Priority Level 0 Enable Position */
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#define DMAC_CTRL_LVLEN0_Msk (_U_(0x1) << DMAC_CTRL_LVLEN0_Pos) /**< (DMAC_CTRL) Priority Level 0 Enable Mask */
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#define DMAC_CTRL_LVLEN0(value) (DMAC_CTRL_LVLEN0_Msk & ((value) << DMAC_CTRL_LVLEN0_Pos))
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#define DMAC_CTRL_LVLEN1_Pos _U_(9) /**< (DMAC_CTRL) Priority Level 1 Enable Position */
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#define DMAC_CTRL_LVLEN1_Msk (_U_(0x1) << DMAC_CTRL_LVLEN1_Pos) /**< (DMAC_CTRL) Priority Level 1 Enable Mask */
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#define DMAC_CTRL_LVLEN1(value) (DMAC_CTRL_LVLEN1_Msk & ((value) << DMAC_CTRL_LVLEN1_Pos))
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#define DMAC_CTRL_LVLEN2_Pos _U_(10) /**< (DMAC_CTRL) Priority Level 2 Enable Position */
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#define DMAC_CTRL_LVLEN2_Msk (_U_(0x1) << DMAC_CTRL_LVLEN2_Pos) /**< (DMAC_CTRL) Priority Level 2 Enable Mask */
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#define DMAC_CTRL_LVLEN2(value) (DMAC_CTRL_LVLEN2_Msk & ((value) << DMAC_CTRL_LVLEN2_Pos))
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#define DMAC_CTRL_LVLEN3_Pos _U_(11) /**< (DMAC_CTRL) Priority Level 3 Enable Position */
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#define DMAC_CTRL_LVLEN3_Msk (_U_(0x1) << DMAC_CTRL_LVLEN3_Pos) /**< (DMAC_CTRL) Priority Level 3 Enable Mask */
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#define DMAC_CTRL_LVLEN3(value) (DMAC_CTRL_LVLEN3_Msk & ((value) << DMAC_CTRL_LVLEN3_Pos))
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#define DMAC_CTRL_Msk _U_(0x0F07) /**< (DMAC_CTRL) Register Mask */
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#define DMAC_CTRL_LVLEN_Pos _U_(8) /**< (DMAC_CTRL Position) Priority Level 3 Enable */
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#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos) /**< (DMAC_CTRL Mask) LVLEN */
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#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
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/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
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#define DMAC_CRCCTRL_RESETVALUE _U_(0x00) /**< (DMAC_CRCCTRL) CRC Control Reset Value */
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#define DMAC_CRCCTRL_CRCBEATSIZE_Pos _U_(0) /**< (DMAC_CRCCTRL) CRC Beat Size Position */
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#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) /**< (DMAC_CRCCTRL) CRC Beat Size Mask */
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#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
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#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< (DMAC_CRCCTRL) Byte bus access */
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#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< (DMAC_CRCCTRL) Half-word bus access */
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#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< (DMAC_CRCCTRL) Word bus access */
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#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) /**< (DMAC_CRCCTRL) Byte bus access Position */
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#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) /**< (DMAC_CRCCTRL) Half-word bus access Position */
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#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) /**< (DMAC_CRCCTRL) Word bus access Position */
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#define DMAC_CRCCTRL_CRCPOLY_Pos _U_(2) /**< (DMAC_CRCCTRL) CRC Polynomial Type Position */
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#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) /**< (DMAC_CRCCTRL) CRC Polynomial Type Mask */
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#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
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#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
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#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
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#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) /**< (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) Position */
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#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) /**< (DMAC_CRCCTRL) CRC32 (IEEE 802.3) Position */
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#define DMAC_CRCCTRL_CRCSRC_Pos _U_(8) /**< (DMAC_CRCCTRL) CRC Input Source Position */
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#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) /**< (DMAC_CRCCTRL) CRC Input Source Mask */
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#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
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#define DMAC_CRCCTRL_CRCSRC_NOACT_Val _U_(0x0) /**< (DMAC_CRCCTRL) No action */
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#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< (DMAC_CRCCTRL) I/O interface */
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#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) /**< (DMAC_CRCCTRL) No action Position */
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#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) /**< (DMAC_CRCCTRL) I/O interface Position */
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#define DMAC_CRCCTRL_Msk _U_(0x3F0F) /**< (DMAC_CRCCTRL) Register Mask */
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/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
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#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00) /**< (DMAC_CRCDATAIN) CRC Data Input Reset Value */
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#define DMAC_CRCDATAIN_CRCDATAIN_Pos _U_(0) /**< (DMAC_CRCDATAIN) CRC Data Input Position */
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#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) /**< (DMAC_CRCDATAIN) CRC Data Input Mask */
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#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
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#define DMAC_CRCDATAIN_Msk _U_(0xFFFFFFFF) /**< (DMAC_CRCDATAIN) Register Mask */
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/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
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#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00) /**< (DMAC_CRCCHKSUM) CRC Checksum Reset Value */
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#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos _U_(0) /**< (DMAC_CRCCHKSUM) CRC Checksum Position */
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#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) /**< (DMAC_CRCCHKSUM) CRC Checksum Mask */
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#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
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#define DMAC_CRCCHKSUM_Msk _U_(0xFFFFFFFF) /**< (DMAC_CRCCHKSUM) Register Mask */
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/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
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#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< (DMAC_CRCSTATUS) CRC Status Reset Value */
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#define DMAC_CRCSTATUS_CRCBUSY_Pos _U_(0) /**< (DMAC_CRCSTATUS) CRC Module Busy Position */
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#define DMAC_CRCSTATUS_CRCBUSY_Msk (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) /**< (DMAC_CRCSTATUS) CRC Module Busy Mask */
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#define DMAC_CRCSTATUS_CRCBUSY(value) (DMAC_CRCSTATUS_CRCBUSY_Msk & ((value) << DMAC_CRCSTATUS_CRCBUSY_Pos))
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#define DMAC_CRCSTATUS_CRCZERO_Pos _U_(1) /**< (DMAC_CRCSTATUS) CRC Zero Position */
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#define DMAC_CRCSTATUS_CRCZERO_Msk (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) /**< (DMAC_CRCSTATUS) CRC Zero Mask */
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#define DMAC_CRCSTATUS_CRCZERO(value) (DMAC_CRCSTATUS_CRCZERO_Msk & ((value) << DMAC_CRCSTATUS_CRCZERO_Pos))
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#define DMAC_CRCSTATUS_Msk _U_(0x03) /**< (DMAC_CRCSTATUS) Register Mask */
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/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
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#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< (DMAC_DBGCTRL) Debug Control Reset Value */
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#define DMAC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (DMAC_DBGCTRL) Debug Run Position */
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#define DMAC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) /**< (DMAC_DBGCTRL) Debug Run Mask */
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#define DMAC_DBGCTRL_DBGRUN(value) (DMAC_DBGCTRL_DBGRUN_Msk & ((value) << DMAC_DBGCTRL_DBGRUN_Pos))
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#define DMAC_DBGCTRL_Msk _U_(0x01) /**< (DMAC_DBGCTRL) Register Mask */
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/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
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#define DMAC_QOSCTRL_RESETVALUE _U_(0x15) /**< (DMAC_QOSCTRL) QOS Control Reset Value */
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#define DMAC_QOSCTRL_WRBQOS_Pos _U_(0) /**< (DMAC_QOSCTRL) Write-Back Quality of Service Position */
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#define DMAC_QOSCTRL_WRBQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_WRBQOS_Pos) /**< (DMAC_QOSCTRL) Write-Back Quality of Service Mask */
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#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))
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#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val _U_(0x0) /**< (DMAC_QOSCTRL) Background (no sensitive operation) */
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#define DMAC_QOSCTRL_WRBQOS_LOW_Val _U_(0x1) /**< (DMAC_QOSCTRL) Sensitive Bandwidth */
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#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val _U_(0x2) /**< (DMAC_QOSCTRL) Sensitive Latency */
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#define DMAC_QOSCTRL_WRBQOS_HIGH_Val _U_(0x3) /**< (DMAC_QOSCTRL) Critical Latency */
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#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) /**< (DMAC_QOSCTRL) Background (no sensitive operation) Position */
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#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) /**< (DMAC_QOSCTRL) Sensitive Bandwidth Position */
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#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) /**< (DMAC_QOSCTRL) Sensitive Latency Position */
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#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) /**< (DMAC_QOSCTRL) Critical Latency Position */
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#define DMAC_QOSCTRL_FQOS_Pos _U_(2) /**< (DMAC_QOSCTRL) Fetch Quality of Service Position */
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#define DMAC_QOSCTRL_FQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_FQOS_Pos) /**< (DMAC_QOSCTRL) Fetch Quality of Service Mask */
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#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))
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#define DMAC_QOSCTRL_FQOS_DISABLE_Val _U_(0x0) /**< (DMAC_QOSCTRL) Background (no sensitive operation) */
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#define DMAC_QOSCTRL_FQOS_LOW_Val _U_(0x1) /**< (DMAC_QOSCTRL) Sensitive Bandwidth */
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#define DMAC_QOSCTRL_FQOS_MEDIUM_Val _U_(0x2) /**< (DMAC_QOSCTRL) Sensitive Latency */
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#define DMAC_QOSCTRL_FQOS_HIGH_Val _U_(0x3) /**< (DMAC_QOSCTRL) Critical Latency */
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#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) /**< (DMAC_QOSCTRL) Background (no sensitive operation) Position */
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#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) /**< (DMAC_QOSCTRL) Sensitive Bandwidth Position */
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#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) /**< (DMAC_QOSCTRL) Sensitive Latency Position */
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#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) /**< (DMAC_QOSCTRL) Critical Latency Position */
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#define DMAC_QOSCTRL_DQOS_Pos _U_(4) /**< (DMAC_QOSCTRL) Data Transfer Quality of Service Position */
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#define DMAC_QOSCTRL_DQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_DQOS_Pos) /**< (DMAC_QOSCTRL) Data Transfer Quality of Service Mask */
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#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))
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#define DMAC_QOSCTRL_DQOS_DISABLE_Val _U_(0x0) /**< (DMAC_QOSCTRL) Background (no sensitive operation) */
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#define DMAC_QOSCTRL_DQOS_LOW_Val _U_(0x1) /**< (DMAC_QOSCTRL) Sensitive Bandwidth */
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#define DMAC_QOSCTRL_DQOS_MEDIUM_Val _U_(0x2) /**< (DMAC_QOSCTRL) Sensitive Latency */
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#define DMAC_QOSCTRL_DQOS_HIGH_Val _U_(0x3) /**< (DMAC_QOSCTRL) Critical Latency */
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#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) /**< (DMAC_QOSCTRL) Background (no sensitive operation) Position */
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#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) /**< (DMAC_QOSCTRL) Sensitive Bandwidth Position */
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#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) /**< (DMAC_QOSCTRL) Sensitive Latency Position */
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#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) /**< (DMAC_QOSCTRL) Critical Latency Position */
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#define DMAC_QOSCTRL_Msk _U_(0x3F) /**< (DMAC_QOSCTRL) Register Mask */
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/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
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#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00) /**< (DMAC_SWTRIGCTRL) Software Trigger Control Reset Value */
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#define DMAC_SWTRIGCTRL_SWTRIG0_Pos _U_(0) /**< (DMAC_SWTRIGCTRL) Channel 0 Software Trigger Position */
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#define DMAC_SWTRIGCTRL_SWTRIG0_Msk (_U_(0x1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos) /**< (DMAC_SWTRIGCTRL) Channel 0 Software Trigger Mask */
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#define DMAC_SWTRIGCTRL_SWTRIG0(value) (DMAC_SWTRIGCTRL_SWTRIG0_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG0_Pos))
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#define DMAC_SWTRIGCTRL_SWTRIG1_Pos _U_(1) /**< (DMAC_SWTRIGCTRL) Channel 1 Software Trigger Position */
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#define DMAC_SWTRIGCTRL_SWTRIG1_Msk (_U_(0x1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos) /**< (DMAC_SWTRIGCTRL) Channel 1 Software Trigger Mask */
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#define DMAC_SWTRIGCTRL_SWTRIG1(value) (DMAC_SWTRIGCTRL_SWTRIG1_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG1_Pos))
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#define DMAC_SWTRIGCTRL_SWTRIG2_Pos _U_(2) /**< (DMAC_SWTRIGCTRL) Channel 2 Software Trigger Position */
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#define DMAC_SWTRIGCTRL_SWTRIG2_Msk (_U_(0x1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos) /**< (DMAC_SWTRIGCTRL) Channel 2 Software Trigger Mask */
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#define DMAC_SWTRIGCTRL_SWTRIG2(value) (DMAC_SWTRIGCTRL_SWTRIG2_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG2_Pos))
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#define DMAC_SWTRIGCTRL_SWTRIG3_Pos _U_(3) /**< (DMAC_SWTRIGCTRL) Channel 3 Software Trigger Position */
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#define DMAC_SWTRIGCTRL_SWTRIG3_Msk (_U_(0x1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos) /**< (DMAC_SWTRIGCTRL) Channel 3 Software Trigger Mask */
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#define DMAC_SWTRIGCTRL_SWTRIG3(value) (DMAC_SWTRIGCTRL_SWTRIG3_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG3_Pos))
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#define DMAC_SWTRIGCTRL_SWTRIG4_Pos _U_(4) /**< (DMAC_SWTRIGCTRL) Channel 4 Software Trigger Position */
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#define DMAC_SWTRIGCTRL_SWTRIG4_Msk (_U_(0x1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos) /**< (DMAC_SWTRIGCTRL) Channel 4 Software Trigger Mask */
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#define DMAC_SWTRIGCTRL_SWTRIG4(value) (DMAC_SWTRIGCTRL_SWTRIG4_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG4_Pos))
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#define DMAC_SWTRIGCTRL_SWTRIG5_Pos _U_(5) /**< (DMAC_SWTRIGCTRL) Channel 5 Software Trigger Position */
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#define DMAC_SWTRIGCTRL_SWTRIG5_Msk (_U_(0x1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos) /**< (DMAC_SWTRIGCTRL) Channel 5 Software Trigger Mask */
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#define DMAC_SWTRIGCTRL_SWTRIG5(value) (DMAC_SWTRIGCTRL_SWTRIG5_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG5_Pos))
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#define DMAC_SWTRIGCTRL_SWTRIG6_Pos _U_(6) /**< (DMAC_SWTRIGCTRL) Channel 6 Software Trigger Position */
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#define DMAC_SWTRIGCTRL_SWTRIG6_Msk (_U_(0x1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos) /**< (DMAC_SWTRIGCTRL) Channel 6 Software Trigger Mask */
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#define DMAC_SWTRIGCTRL_SWTRIG6(value) (DMAC_SWTRIGCTRL_SWTRIG6_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG6_Pos))
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#define DMAC_SWTRIGCTRL_SWTRIG7_Pos _U_(7) /**< (DMAC_SWTRIGCTRL) Channel 7 Software Trigger Position */
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#define DMAC_SWTRIGCTRL_SWTRIG7_Msk (_U_(0x1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos) /**< (DMAC_SWTRIGCTRL) Channel 7 Software Trigger Mask */
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#define DMAC_SWTRIGCTRL_SWTRIG7(value) (DMAC_SWTRIGCTRL_SWTRIG7_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG7_Pos))
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#define DMAC_SWTRIGCTRL_SWTRIG8_Pos _U_(8) /**< (DMAC_SWTRIGCTRL) Channel 8 Software Trigger Position */
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#define DMAC_SWTRIGCTRL_SWTRIG8_Msk (_U_(0x1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos) /**< (DMAC_SWTRIGCTRL) Channel 8 Software Trigger Mask */
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#define DMAC_SWTRIGCTRL_SWTRIG8(value) (DMAC_SWTRIGCTRL_SWTRIG8_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG8_Pos))
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#define DMAC_SWTRIGCTRL_SWTRIG9_Pos _U_(9) /**< (DMAC_SWTRIGCTRL) Channel 9 Software Trigger Position */
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#define DMAC_SWTRIGCTRL_SWTRIG9_Msk (_U_(0x1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos) /**< (DMAC_SWTRIGCTRL) Channel 9 Software Trigger Mask */
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#define DMAC_SWTRIGCTRL_SWTRIG9(value) (DMAC_SWTRIGCTRL_SWTRIG9_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG9_Pos))
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#define DMAC_SWTRIGCTRL_SWTRIG10_Pos _U_(10) /**< (DMAC_SWTRIGCTRL) Channel 10 Software Trigger Position */
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#define DMAC_SWTRIGCTRL_SWTRIG10_Msk (_U_(0x1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos) /**< (DMAC_SWTRIGCTRL) Channel 10 Software Trigger Mask */
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|
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#define DMAC_SWTRIGCTRL_SWTRIG10(value) (DMAC_SWTRIGCTRL_SWTRIG10_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG10_Pos))
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#define DMAC_SWTRIGCTRL_SWTRIG11_Pos _U_(11) /**< (DMAC_SWTRIGCTRL) Channel 11 Software Trigger Position */
|
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|
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#define DMAC_SWTRIGCTRL_SWTRIG11_Msk (_U_(0x1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos) /**< (DMAC_SWTRIGCTRL) Channel 11 Software Trigger Mask */
|
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|
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#define DMAC_SWTRIGCTRL_SWTRIG11(value) (DMAC_SWTRIGCTRL_SWTRIG11_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG11_Pos))
|
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#define DMAC_SWTRIGCTRL_Msk _U_(0x00000FFF) /**< (DMAC_SWTRIGCTRL) Register Mask */
|
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|
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|
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#define DMAC_SWTRIGCTRL_SWTRIG_Pos _U_(0) /**< (DMAC_SWTRIGCTRL Position) Channel xx Software Trigger */
|
||
|
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#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) /**< (DMAC_SWTRIGCTRL Mask) SWTRIG */
|
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|
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#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
|
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|
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|
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/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
|
||
|
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#define DMAC_PRICTRL0_RESETVALUE _U_(0x00) /**< (DMAC_PRICTRL0) Priority Control 0 Reset Value */
|
||
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|
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|
|
#define DMAC_PRICTRL0_LVLPRI0_Pos _U_(0) /**< (DMAC_PRICTRL0) Level 0 Channel Priority Number Position */
|
||
|
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#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos) /**< (DMAC_PRICTRL0) Level 0 Channel Priority Number Mask */
|
||
|
|
#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
|
||
|
|
#define DMAC_PRICTRL0_RRLVLEN0_Pos _U_(7) /**< (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable Position */
|
||
|
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#define DMAC_PRICTRL0_RRLVLEN0_Msk (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) /**< (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable Mask */
|
||
|
|
#define DMAC_PRICTRL0_RRLVLEN0(value) (DMAC_PRICTRL0_RRLVLEN0_Msk & ((value) << DMAC_PRICTRL0_RRLVLEN0_Pos))
|
||
|
|
#define DMAC_PRICTRL0_LVLPRI1_Pos _U_(8) /**< (DMAC_PRICTRL0) Level 1 Channel Priority Number Position */
|
||
|
|
#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos) /**< (DMAC_PRICTRL0) Level 1 Channel Priority Number Mask */
|
||
|
|
#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
|
||
|
|
#define DMAC_PRICTRL0_RRLVLEN1_Pos _U_(15) /**< (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable Position */
|
||
|
|
#define DMAC_PRICTRL0_RRLVLEN1_Msk (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) /**< (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable Mask */
|
||
|
|
#define DMAC_PRICTRL0_RRLVLEN1(value) (DMAC_PRICTRL0_RRLVLEN1_Msk & ((value) << DMAC_PRICTRL0_RRLVLEN1_Pos))
|
||
|
|
#define DMAC_PRICTRL0_LVLPRI2_Pos _U_(16) /**< (DMAC_PRICTRL0) Level 2 Channel Priority Number Position */
|
||
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#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos) /**< (DMAC_PRICTRL0) Level 2 Channel Priority Number Mask */
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#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
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#define DMAC_PRICTRL0_RRLVLEN2_Pos _U_(23) /**< (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable Position */
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#define DMAC_PRICTRL0_RRLVLEN2_Msk (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) /**< (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable Mask */
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#define DMAC_PRICTRL0_RRLVLEN2(value) (DMAC_PRICTRL0_RRLVLEN2_Msk & ((value) << DMAC_PRICTRL0_RRLVLEN2_Pos))
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#define DMAC_PRICTRL0_LVLPRI3_Pos _U_(24) /**< (DMAC_PRICTRL0) Level 3 Channel Priority Number Position */
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#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos) /**< (DMAC_PRICTRL0) Level 3 Channel Priority Number Mask */
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#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
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#define DMAC_PRICTRL0_RRLVLEN3_Pos _U_(31) /**< (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable Position */
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#define DMAC_PRICTRL0_RRLVLEN3_Msk (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) /**< (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable Mask */
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#define DMAC_PRICTRL0_RRLVLEN3(value) (DMAC_PRICTRL0_RRLVLEN3_Msk & ((value) << DMAC_PRICTRL0_RRLVLEN3_Pos))
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#define DMAC_PRICTRL0_Msk _U_(0x8F8F8F8F) /**< (DMAC_PRICTRL0) Register Mask */
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/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
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#define DMAC_INTPEND_RESETVALUE _U_(0x00) /**< (DMAC_INTPEND) Interrupt Pending Reset Value */
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#define DMAC_INTPEND_ID_Pos _U_(0) /**< (DMAC_INTPEND) Channel ID Position */
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#define DMAC_INTPEND_ID_Msk (_U_(0xF) << DMAC_INTPEND_ID_Pos) /**< (DMAC_INTPEND) Channel ID Mask */
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#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
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#define DMAC_INTPEND_TERR_Pos _U_(8) /**< (DMAC_INTPEND) Transfer Error Position */
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#define DMAC_INTPEND_TERR_Msk (_U_(0x1) << DMAC_INTPEND_TERR_Pos) /**< (DMAC_INTPEND) Transfer Error Mask */
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#define DMAC_INTPEND_TERR(value) (DMAC_INTPEND_TERR_Msk & ((value) << DMAC_INTPEND_TERR_Pos))
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#define DMAC_INTPEND_TCMPL_Pos _U_(9) /**< (DMAC_INTPEND) Transfer Complete Position */
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#define DMAC_INTPEND_TCMPL_Msk (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos) /**< (DMAC_INTPEND) Transfer Complete Mask */
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#define DMAC_INTPEND_TCMPL(value) (DMAC_INTPEND_TCMPL_Msk & ((value) << DMAC_INTPEND_TCMPL_Pos))
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#define DMAC_INTPEND_SUSP_Pos _U_(10) /**< (DMAC_INTPEND) Channel Suspend Position */
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#define DMAC_INTPEND_SUSP_Msk (_U_(0x1) << DMAC_INTPEND_SUSP_Pos) /**< (DMAC_INTPEND) Channel Suspend Mask */
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#define DMAC_INTPEND_SUSP(value) (DMAC_INTPEND_SUSP_Msk & ((value) << DMAC_INTPEND_SUSP_Pos))
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#define DMAC_INTPEND_FERR_Pos _U_(13) /**< (DMAC_INTPEND) Fetch Error Position */
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#define DMAC_INTPEND_FERR_Msk (_U_(0x1) << DMAC_INTPEND_FERR_Pos) /**< (DMAC_INTPEND) Fetch Error Mask */
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#define DMAC_INTPEND_FERR(value) (DMAC_INTPEND_FERR_Msk & ((value) << DMAC_INTPEND_FERR_Pos))
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#define DMAC_INTPEND_BUSY_Pos _U_(14) /**< (DMAC_INTPEND) Busy Position */
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#define DMAC_INTPEND_BUSY_Msk (_U_(0x1) << DMAC_INTPEND_BUSY_Pos) /**< (DMAC_INTPEND) Busy Mask */
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#define DMAC_INTPEND_BUSY(value) (DMAC_INTPEND_BUSY_Msk & ((value) << DMAC_INTPEND_BUSY_Pos))
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#define DMAC_INTPEND_PEND_Pos _U_(15) /**< (DMAC_INTPEND) Pending Position */
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#define DMAC_INTPEND_PEND_Msk (_U_(0x1) << DMAC_INTPEND_PEND_Pos) /**< (DMAC_INTPEND) Pending Mask */
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#define DMAC_INTPEND_PEND(value) (DMAC_INTPEND_PEND_Msk & ((value) << DMAC_INTPEND_PEND_Pos))
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#define DMAC_INTPEND_Msk _U_(0xE70F) /**< (DMAC_INTPEND) Register Mask */
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/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) ( R/ 32) Interrupt Status -------- */
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#define DMAC_INTSTATUS_RESETVALUE _U_(0x00) /**< (DMAC_INTSTATUS) Interrupt Status Reset Value */
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#define DMAC_INTSTATUS_CHINT0_Pos _U_(0) /**< (DMAC_INTSTATUS) Channel 0 Pending Interrupt Position */
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#define DMAC_INTSTATUS_CHINT0_Msk (_U_(0x1) << DMAC_INTSTATUS_CHINT0_Pos) /**< (DMAC_INTSTATUS) Channel 0 Pending Interrupt Mask */
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#define DMAC_INTSTATUS_CHINT0(value) (DMAC_INTSTATUS_CHINT0_Msk & ((value) << DMAC_INTSTATUS_CHINT0_Pos))
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#define DMAC_INTSTATUS_CHINT1_Pos _U_(1) /**< (DMAC_INTSTATUS) Channel 1 Pending Interrupt Position */
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#define DMAC_INTSTATUS_CHINT1_Msk (_U_(0x1) << DMAC_INTSTATUS_CHINT1_Pos) /**< (DMAC_INTSTATUS) Channel 1 Pending Interrupt Mask */
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#define DMAC_INTSTATUS_CHINT1(value) (DMAC_INTSTATUS_CHINT1_Msk & ((value) << DMAC_INTSTATUS_CHINT1_Pos))
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#define DMAC_INTSTATUS_CHINT2_Pos _U_(2) /**< (DMAC_INTSTATUS) Channel 2 Pending Interrupt Position */
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#define DMAC_INTSTATUS_CHINT2_Msk (_U_(0x1) << DMAC_INTSTATUS_CHINT2_Pos) /**< (DMAC_INTSTATUS) Channel 2 Pending Interrupt Mask */
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#define DMAC_INTSTATUS_CHINT2(value) (DMAC_INTSTATUS_CHINT2_Msk & ((value) << DMAC_INTSTATUS_CHINT2_Pos))
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#define DMAC_INTSTATUS_CHINT3_Pos _U_(3) /**< (DMAC_INTSTATUS) Channel 3 Pending Interrupt Position */
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#define DMAC_INTSTATUS_CHINT3_Msk (_U_(0x1) << DMAC_INTSTATUS_CHINT3_Pos) /**< (DMAC_INTSTATUS) Channel 3 Pending Interrupt Mask */
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#define DMAC_INTSTATUS_CHINT3(value) (DMAC_INTSTATUS_CHINT3_Msk & ((value) << DMAC_INTSTATUS_CHINT3_Pos))
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#define DMAC_INTSTATUS_CHINT4_Pos _U_(4) /**< (DMAC_INTSTATUS) Channel 4 Pending Interrupt Position */
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#define DMAC_INTSTATUS_CHINT4_Msk (_U_(0x1) << DMAC_INTSTATUS_CHINT4_Pos) /**< (DMAC_INTSTATUS) Channel 4 Pending Interrupt Mask */
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#define DMAC_INTSTATUS_CHINT4(value) (DMAC_INTSTATUS_CHINT4_Msk & ((value) << DMAC_INTSTATUS_CHINT4_Pos))
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#define DMAC_INTSTATUS_CHINT5_Pos _U_(5) /**< (DMAC_INTSTATUS) Channel 5 Pending Interrupt Position */
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#define DMAC_INTSTATUS_CHINT5_Msk (_U_(0x1) << DMAC_INTSTATUS_CHINT5_Pos) /**< (DMAC_INTSTATUS) Channel 5 Pending Interrupt Mask */
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#define DMAC_INTSTATUS_CHINT5(value) (DMAC_INTSTATUS_CHINT5_Msk & ((value) << DMAC_INTSTATUS_CHINT5_Pos))
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#define DMAC_INTSTATUS_CHINT6_Pos _U_(6) /**< (DMAC_INTSTATUS) Channel 6 Pending Interrupt Position */
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#define DMAC_INTSTATUS_CHINT6_Msk (_U_(0x1) << DMAC_INTSTATUS_CHINT6_Pos) /**< (DMAC_INTSTATUS) Channel 6 Pending Interrupt Mask */
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#define DMAC_INTSTATUS_CHINT6(value) (DMAC_INTSTATUS_CHINT6_Msk & ((value) << DMAC_INTSTATUS_CHINT6_Pos))
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#define DMAC_INTSTATUS_CHINT7_Pos _U_(7) /**< (DMAC_INTSTATUS) Channel 7 Pending Interrupt Position */
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#define DMAC_INTSTATUS_CHINT7_Msk (_U_(0x1) << DMAC_INTSTATUS_CHINT7_Pos) /**< (DMAC_INTSTATUS) Channel 7 Pending Interrupt Mask */
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#define DMAC_INTSTATUS_CHINT7(value) (DMAC_INTSTATUS_CHINT7_Msk & ((value) << DMAC_INTSTATUS_CHINT7_Pos))
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#define DMAC_INTSTATUS_CHINT8_Pos _U_(8) /**< (DMAC_INTSTATUS) Channel 8 Pending Interrupt Position */
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#define DMAC_INTSTATUS_CHINT8_Msk (_U_(0x1) << DMAC_INTSTATUS_CHINT8_Pos) /**< (DMAC_INTSTATUS) Channel 8 Pending Interrupt Mask */
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#define DMAC_INTSTATUS_CHINT8(value) (DMAC_INTSTATUS_CHINT8_Msk & ((value) << DMAC_INTSTATUS_CHINT8_Pos))
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#define DMAC_INTSTATUS_CHINT9_Pos _U_(9) /**< (DMAC_INTSTATUS) Channel 9 Pending Interrupt Position */
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#define DMAC_INTSTATUS_CHINT9_Msk (_U_(0x1) << DMAC_INTSTATUS_CHINT9_Pos) /**< (DMAC_INTSTATUS) Channel 9 Pending Interrupt Mask */
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#define DMAC_INTSTATUS_CHINT9(value) (DMAC_INTSTATUS_CHINT9_Msk & ((value) << DMAC_INTSTATUS_CHINT9_Pos))
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#define DMAC_INTSTATUS_CHINT10_Pos _U_(10) /**< (DMAC_INTSTATUS) Channel 10 Pending Interrupt Position */
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#define DMAC_INTSTATUS_CHINT10_Msk (_U_(0x1) << DMAC_INTSTATUS_CHINT10_Pos) /**< (DMAC_INTSTATUS) Channel 10 Pending Interrupt Mask */
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#define DMAC_INTSTATUS_CHINT10(value) (DMAC_INTSTATUS_CHINT10_Msk & ((value) << DMAC_INTSTATUS_CHINT10_Pos))
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#define DMAC_INTSTATUS_CHINT11_Pos _U_(11) /**< (DMAC_INTSTATUS) Channel 11 Pending Interrupt Position */
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#define DMAC_INTSTATUS_CHINT11_Msk (_U_(0x1) << DMAC_INTSTATUS_CHINT11_Pos) /**< (DMAC_INTSTATUS) Channel 11 Pending Interrupt Mask */
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#define DMAC_INTSTATUS_CHINT11(value) (DMAC_INTSTATUS_CHINT11_Msk & ((value) << DMAC_INTSTATUS_CHINT11_Pos))
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#define DMAC_INTSTATUS_Msk _U_(0x00000FFF) /**< (DMAC_INTSTATUS) Register Mask */
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#define DMAC_INTSTATUS_CHINT_Pos _U_(0) /**< (DMAC_INTSTATUS Position) Channel xx Pending Interrupt */
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#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFF) << DMAC_INTSTATUS_CHINT_Pos) /**< (DMAC_INTSTATUS Mask) CHINT */
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#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
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/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) ( R/ 32) Busy Channels -------- */
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#define DMAC_BUSYCH_RESETVALUE _U_(0x00) /**< (DMAC_BUSYCH) Busy Channels Reset Value */
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#define DMAC_BUSYCH_BUSYCH0_Pos _U_(0) /**< (DMAC_BUSYCH) Busy Channel 0 Position */
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#define DMAC_BUSYCH_BUSYCH0_Msk (_U_(0x1) << DMAC_BUSYCH_BUSYCH0_Pos) /**< (DMAC_BUSYCH) Busy Channel 0 Mask */
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#define DMAC_BUSYCH_BUSYCH0(value) (DMAC_BUSYCH_BUSYCH0_Msk & ((value) << DMAC_BUSYCH_BUSYCH0_Pos))
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#define DMAC_BUSYCH_BUSYCH1_Pos _U_(1) /**< (DMAC_BUSYCH) Busy Channel 1 Position */
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#define DMAC_BUSYCH_BUSYCH1_Msk (_U_(0x1) << DMAC_BUSYCH_BUSYCH1_Pos) /**< (DMAC_BUSYCH) Busy Channel 1 Mask */
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#define DMAC_BUSYCH_BUSYCH1(value) (DMAC_BUSYCH_BUSYCH1_Msk & ((value) << DMAC_BUSYCH_BUSYCH1_Pos))
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#define DMAC_BUSYCH_BUSYCH2_Pos _U_(2) /**< (DMAC_BUSYCH) Busy Channel 2 Position */
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#define DMAC_BUSYCH_BUSYCH2_Msk (_U_(0x1) << DMAC_BUSYCH_BUSYCH2_Pos) /**< (DMAC_BUSYCH) Busy Channel 2 Mask */
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#define DMAC_BUSYCH_BUSYCH2(value) (DMAC_BUSYCH_BUSYCH2_Msk & ((value) << DMAC_BUSYCH_BUSYCH2_Pos))
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#define DMAC_BUSYCH_BUSYCH3_Pos _U_(3) /**< (DMAC_BUSYCH) Busy Channel 3 Position */
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#define DMAC_BUSYCH_BUSYCH3_Msk (_U_(0x1) << DMAC_BUSYCH_BUSYCH3_Pos) /**< (DMAC_BUSYCH) Busy Channel 3 Mask */
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#define DMAC_BUSYCH_BUSYCH3(value) (DMAC_BUSYCH_BUSYCH3_Msk & ((value) << DMAC_BUSYCH_BUSYCH3_Pos))
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#define DMAC_BUSYCH_BUSYCH4_Pos _U_(4) /**< (DMAC_BUSYCH) Busy Channel 4 Position */
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#define DMAC_BUSYCH_BUSYCH4_Msk (_U_(0x1) << DMAC_BUSYCH_BUSYCH4_Pos) /**< (DMAC_BUSYCH) Busy Channel 4 Mask */
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#define DMAC_BUSYCH_BUSYCH4(value) (DMAC_BUSYCH_BUSYCH4_Msk & ((value) << DMAC_BUSYCH_BUSYCH4_Pos))
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#define DMAC_BUSYCH_BUSYCH5_Pos _U_(5) /**< (DMAC_BUSYCH) Busy Channel 5 Position */
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#define DMAC_BUSYCH_BUSYCH5_Msk (_U_(0x1) << DMAC_BUSYCH_BUSYCH5_Pos) /**< (DMAC_BUSYCH) Busy Channel 5 Mask */
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#define DMAC_BUSYCH_BUSYCH5(value) (DMAC_BUSYCH_BUSYCH5_Msk & ((value) << DMAC_BUSYCH_BUSYCH5_Pos))
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#define DMAC_BUSYCH_BUSYCH6_Pos _U_(6) /**< (DMAC_BUSYCH) Busy Channel 6 Position */
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#define DMAC_BUSYCH_BUSYCH6_Msk (_U_(0x1) << DMAC_BUSYCH_BUSYCH6_Pos) /**< (DMAC_BUSYCH) Busy Channel 6 Mask */
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#define DMAC_BUSYCH_BUSYCH6(value) (DMAC_BUSYCH_BUSYCH6_Msk & ((value) << DMAC_BUSYCH_BUSYCH6_Pos))
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#define DMAC_BUSYCH_BUSYCH7_Pos _U_(7) /**< (DMAC_BUSYCH) Busy Channel 7 Position */
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#define DMAC_BUSYCH_BUSYCH7_Msk (_U_(0x1) << DMAC_BUSYCH_BUSYCH7_Pos) /**< (DMAC_BUSYCH) Busy Channel 7 Mask */
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#define DMAC_BUSYCH_BUSYCH7(value) (DMAC_BUSYCH_BUSYCH7_Msk & ((value) << DMAC_BUSYCH_BUSYCH7_Pos))
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#define DMAC_BUSYCH_BUSYCH8_Pos _U_(8) /**< (DMAC_BUSYCH) Busy Channel 8 Position */
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#define DMAC_BUSYCH_BUSYCH8_Msk (_U_(0x1) << DMAC_BUSYCH_BUSYCH8_Pos) /**< (DMAC_BUSYCH) Busy Channel 8 Mask */
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#define DMAC_BUSYCH_BUSYCH8(value) (DMAC_BUSYCH_BUSYCH8_Msk & ((value) << DMAC_BUSYCH_BUSYCH8_Pos))
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#define DMAC_BUSYCH_BUSYCH9_Pos _U_(9) /**< (DMAC_BUSYCH) Busy Channel 9 Position */
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#define DMAC_BUSYCH_BUSYCH9_Msk (_U_(0x1) << DMAC_BUSYCH_BUSYCH9_Pos) /**< (DMAC_BUSYCH) Busy Channel 9 Mask */
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#define DMAC_BUSYCH_BUSYCH9(value) (DMAC_BUSYCH_BUSYCH9_Msk & ((value) << DMAC_BUSYCH_BUSYCH9_Pos))
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#define DMAC_BUSYCH_BUSYCH10_Pos _U_(10) /**< (DMAC_BUSYCH) Busy Channel 10 Position */
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#define DMAC_BUSYCH_BUSYCH10_Msk (_U_(0x1) << DMAC_BUSYCH_BUSYCH10_Pos) /**< (DMAC_BUSYCH) Busy Channel 10 Mask */
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#define DMAC_BUSYCH_BUSYCH10(value) (DMAC_BUSYCH_BUSYCH10_Msk & ((value) << DMAC_BUSYCH_BUSYCH10_Pos))
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#define DMAC_BUSYCH_BUSYCH11_Pos _U_(11) /**< (DMAC_BUSYCH) Busy Channel 11 Position */
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#define DMAC_BUSYCH_BUSYCH11_Msk (_U_(0x1) << DMAC_BUSYCH_BUSYCH11_Pos) /**< (DMAC_BUSYCH) Busy Channel 11 Mask */
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#define DMAC_BUSYCH_BUSYCH11(value) (DMAC_BUSYCH_BUSYCH11_Msk & ((value) << DMAC_BUSYCH_BUSYCH11_Pos))
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#define DMAC_BUSYCH_Msk _U_(0x00000FFF) /**< (DMAC_BUSYCH) Register Mask */
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#define DMAC_BUSYCH_BUSYCH_Pos _U_(0) /**< (DMAC_BUSYCH Position) Busy Channel xx */
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#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFF) << DMAC_BUSYCH_BUSYCH_Pos) /**< (DMAC_BUSYCH Mask) BUSYCH */
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#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
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/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) ( R/ 32) Pending Channels -------- */
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#define DMAC_PENDCH_RESETVALUE _U_(0x00) /**< (DMAC_PENDCH) Pending Channels Reset Value */
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#define DMAC_PENDCH_PENDCH0_Pos _U_(0) /**< (DMAC_PENDCH) Pending Channel 0 Position */
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#define DMAC_PENDCH_PENDCH0_Msk (_U_(0x1) << DMAC_PENDCH_PENDCH0_Pos) /**< (DMAC_PENDCH) Pending Channel 0 Mask */
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#define DMAC_PENDCH_PENDCH0(value) (DMAC_PENDCH_PENDCH0_Msk & ((value) << DMAC_PENDCH_PENDCH0_Pos))
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#define DMAC_PENDCH_PENDCH1_Pos _U_(1) /**< (DMAC_PENDCH) Pending Channel 1 Position */
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#define DMAC_PENDCH_PENDCH1_Msk (_U_(0x1) << DMAC_PENDCH_PENDCH1_Pos) /**< (DMAC_PENDCH) Pending Channel 1 Mask */
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#define DMAC_PENDCH_PENDCH1(value) (DMAC_PENDCH_PENDCH1_Msk & ((value) << DMAC_PENDCH_PENDCH1_Pos))
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#define DMAC_PENDCH_PENDCH2_Pos _U_(2) /**< (DMAC_PENDCH) Pending Channel 2 Position */
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#define DMAC_PENDCH_PENDCH2_Msk (_U_(0x1) << DMAC_PENDCH_PENDCH2_Pos) /**< (DMAC_PENDCH) Pending Channel 2 Mask */
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#define DMAC_PENDCH_PENDCH2(value) (DMAC_PENDCH_PENDCH2_Msk & ((value) << DMAC_PENDCH_PENDCH2_Pos))
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#define DMAC_PENDCH_PENDCH3_Pos _U_(3) /**< (DMAC_PENDCH) Pending Channel 3 Position */
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#define DMAC_PENDCH_PENDCH3_Msk (_U_(0x1) << DMAC_PENDCH_PENDCH3_Pos) /**< (DMAC_PENDCH) Pending Channel 3 Mask */
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#define DMAC_PENDCH_PENDCH3(value) (DMAC_PENDCH_PENDCH3_Msk & ((value) << DMAC_PENDCH_PENDCH3_Pos))
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#define DMAC_PENDCH_PENDCH4_Pos _U_(4) /**< (DMAC_PENDCH) Pending Channel 4 Position */
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#define DMAC_PENDCH_PENDCH4_Msk (_U_(0x1) << DMAC_PENDCH_PENDCH4_Pos) /**< (DMAC_PENDCH) Pending Channel 4 Mask */
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#define DMAC_PENDCH_PENDCH4(value) (DMAC_PENDCH_PENDCH4_Msk & ((value) << DMAC_PENDCH_PENDCH4_Pos))
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#define DMAC_PENDCH_PENDCH5_Pos _U_(5) /**< (DMAC_PENDCH) Pending Channel 5 Position */
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#define DMAC_PENDCH_PENDCH5_Msk (_U_(0x1) << DMAC_PENDCH_PENDCH5_Pos) /**< (DMAC_PENDCH) Pending Channel 5 Mask */
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#define DMAC_PENDCH_PENDCH5(value) (DMAC_PENDCH_PENDCH5_Msk & ((value) << DMAC_PENDCH_PENDCH5_Pos))
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#define DMAC_PENDCH_PENDCH6_Pos _U_(6) /**< (DMAC_PENDCH) Pending Channel 6 Position */
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#define DMAC_PENDCH_PENDCH6_Msk (_U_(0x1) << DMAC_PENDCH_PENDCH6_Pos) /**< (DMAC_PENDCH) Pending Channel 6 Mask */
|
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#define DMAC_PENDCH_PENDCH6(value) (DMAC_PENDCH_PENDCH6_Msk & ((value) << DMAC_PENDCH_PENDCH6_Pos))
|
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#define DMAC_PENDCH_PENDCH7_Pos _U_(7) /**< (DMAC_PENDCH) Pending Channel 7 Position */
|
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#define DMAC_PENDCH_PENDCH7_Msk (_U_(0x1) << DMAC_PENDCH_PENDCH7_Pos) /**< (DMAC_PENDCH) Pending Channel 7 Mask */
|
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#define DMAC_PENDCH_PENDCH7(value) (DMAC_PENDCH_PENDCH7_Msk & ((value) << DMAC_PENDCH_PENDCH7_Pos))
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#define DMAC_PENDCH_PENDCH8_Pos _U_(8) /**< (DMAC_PENDCH) Pending Channel 8 Position */
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#define DMAC_PENDCH_PENDCH8_Msk (_U_(0x1) << DMAC_PENDCH_PENDCH8_Pos) /**< (DMAC_PENDCH) Pending Channel 8 Mask */
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#define DMAC_PENDCH_PENDCH8(value) (DMAC_PENDCH_PENDCH8_Msk & ((value) << DMAC_PENDCH_PENDCH8_Pos))
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#define DMAC_PENDCH_PENDCH9_Pos _U_(9) /**< (DMAC_PENDCH) Pending Channel 9 Position */
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#define DMAC_PENDCH_PENDCH9_Msk (_U_(0x1) << DMAC_PENDCH_PENDCH9_Pos) /**< (DMAC_PENDCH) Pending Channel 9 Mask */
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#define DMAC_PENDCH_PENDCH9(value) (DMAC_PENDCH_PENDCH9_Msk & ((value) << DMAC_PENDCH_PENDCH9_Pos))
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#define DMAC_PENDCH_PENDCH10_Pos _U_(10) /**< (DMAC_PENDCH) Pending Channel 10 Position */
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#define DMAC_PENDCH_PENDCH10_Msk (_U_(0x1) << DMAC_PENDCH_PENDCH10_Pos) /**< (DMAC_PENDCH) Pending Channel 10 Mask */
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#define DMAC_PENDCH_PENDCH10(value) (DMAC_PENDCH_PENDCH10_Msk & ((value) << DMAC_PENDCH_PENDCH10_Pos))
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#define DMAC_PENDCH_PENDCH11_Pos _U_(11) /**< (DMAC_PENDCH) Pending Channel 11 Position */
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#define DMAC_PENDCH_PENDCH11_Msk (_U_(0x1) << DMAC_PENDCH_PENDCH11_Pos) /**< (DMAC_PENDCH) Pending Channel 11 Mask */
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#define DMAC_PENDCH_PENDCH11(value) (DMAC_PENDCH_PENDCH11_Msk & ((value) << DMAC_PENDCH_PENDCH11_Pos))
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#define DMAC_PENDCH_Msk _U_(0x00000FFF) /**< (DMAC_PENDCH) Register Mask */
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#define DMAC_PENDCH_PENDCH_Pos _U_(0) /**< (DMAC_PENDCH Position) Pending Channel xx */
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#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFF) << DMAC_PENDCH_PENDCH_Pos) /**< (DMAC_PENDCH Mask) PENDCH */
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#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
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/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) ( R/ 32) Active Channel and Levels -------- */
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#define DMAC_ACTIVE_RESETVALUE _U_(0x00) /**< (DMAC_ACTIVE) Active Channel and Levels Reset Value */
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#define DMAC_ACTIVE_LVLEX0_Pos _U_(0) /**< (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing Position */
|
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#define DMAC_ACTIVE_LVLEX0_Msk (_U_(0x1) << DMAC_ACTIVE_LVLEX0_Pos) /**< (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing Mask */
|
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#define DMAC_ACTIVE_LVLEX0(value) (DMAC_ACTIVE_LVLEX0_Msk & ((value) << DMAC_ACTIVE_LVLEX0_Pos))
|
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#define DMAC_ACTIVE_LVLEX1_Pos _U_(1) /**< (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing Position */
|
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#define DMAC_ACTIVE_LVLEX1_Msk (_U_(0x1) << DMAC_ACTIVE_LVLEX1_Pos) /**< (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing Mask */
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#define DMAC_ACTIVE_LVLEX1(value) (DMAC_ACTIVE_LVLEX1_Msk & ((value) << DMAC_ACTIVE_LVLEX1_Pos))
|
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#define DMAC_ACTIVE_LVLEX2_Pos _U_(2) /**< (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing Position */
|
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#define DMAC_ACTIVE_LVLEX2_Msk (_U_(0x1) << DMAC_ACTIVE_LVLEX2_Pos) /**< (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing Mask */
|
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#define DMAC_ACTIVE_LVLEX2(value) (DMAC_ACTIVE_LVLEX2_Msk & ((value) << DMAC_ACTIVE_LVLEX2_Pos))
|
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#define DMAC_ACTIVE_LVLEX3_Pos _U_(3) /**< (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing Position */
|
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#define DMAC_ACTIVE_LVLEX3_Msk (_U_(0x1) << DMAC_ACTIVE_LVLEX3_Pos) /**< (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing Mask */
|
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#define DMAC_ACTIVE_LVLEX3(value) (DMAC_ACTIVE_LVLEX3_Msk & ((value) << DMAC_ACTIVE_LVLEX3_Pos))
|
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#define DMAC_ACTIVE_ID_Pos _U_(8) /**< (DMAC_ACTIVE) Active Channel ID Position */
|
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#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos) /**< (DMAC_ACTIVE) Active Channel ID Mask */
|
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#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
|
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#define DMAC_ACTIVE_ABUSY_Pos _U_(15) /**< (DMAC_ACTIVE) Active Channel Busy Position */
|
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#define DMAC_ACTIVE_ABUSY_Msk (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos) /**< (DMAC_ACTIVE) Active Channel Busy Mask */
|
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#define DMAC_ACTIVE_ABUSY(value) (DMAC_ACTIVE_ABUSY_Msk & ((value) << DMAC_ACTIVE_ABUSY_Pos))
|
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#define DMAC_ACTIVE_BTCNT_Pos _U_(16) /**< (DMAC_ACTIVE) Active Channel Block Transfer Count Position */
|
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#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) /**< (DMAC_ACTIVE) Active Channel Block Transfer Count Mask */
|
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|
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#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
|
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|
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#define DMAC_ACTIVE_Msk _U_(0xFFFF9F0F) /**< (DMAC_ACTIVE) Register Mask */
|
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|
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|
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#define DMAC_ACTIVE_LVLEX_Pos _U_(0) /**< (DMAC_ACTIVE Position) Level x Channel Trigger Request Executing */
|
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|
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#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos) /**< (DMAC_ACTIVE Mask) LVLEX */
|
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|
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#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
|
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|
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|
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|
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/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
|
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|
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#define DMAC_BASEADDR_RESETVALUE _U_(0x00) /**< (DMAC_BASEADDR) Descriptor Memory Section Base Address Reset Value */
|
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|
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|
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#define DMAC_BASEADDR_BASEADDR_Pos _U_(0) /**< (DMAC_BASEADDR) Descriptor Memory Base Address Position */
|
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#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) /**< (DMAC_BASEADDR) Descriptor Memory Base Address Mask */
|
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|
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#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
|
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|
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#define DMAC_BASEADDR_Msk _U_(0xFFFFFFFF) /**< (DMAC_BASEADDR) Register Mask */
|
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|
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/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
|
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#define DMAC_WRBADDR_RESETVALUE _U_(0x00) /**< (DMAC_WRBADDR) Write-Back Memory Section Base Address Reset Value */
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#define DMAC_WRBADDR_WRBADDR_Pos _U_(0) /**< (DMAC_WRBADDR) Write-Back Memory Base Address Position */
|
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#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) /**< (DMAC_WRBADDR) Write-Back Memory Base Address Mask */
|
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|
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#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
|
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#define DMAC_WRBADDR_Msk _U_(0xFFFFFFFF) /**< (DMAC_WRBADDR) Register Mask */
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/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
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#define DMAC_CHID_RESETVALUE _U_(0x00) /**< (DMAC_CHID) Channel ID Reset Value */
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#define DMAC_CHID_ID_Pos _U_(0) /**< (DMAC_CHID) Channel ID Position */
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#define DMAC_CHID_ID_Msk (_U_(0xF) << DMAC_CHID_ID_Pos) /**< (DMAC_CHID) Channel ID Mask */
|
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#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))
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#define DMAC_CHID_Msk _U_(0x0F) /**< (DMAC_CHID) Register Mask */
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/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
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#define DMAC_CHCTRLA_RESETVALUE _U_(0x00) /**< (DMAC_CHCTRLA) Channel Control A Reset Value */
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#define DMAC_CHCTRLA_SWRST_Pos _U_(0) /**< (DMAC_CHCTRLA) Channel Software Reset Position */
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#define DMAC_CHCTRLA_SWRST_Msk (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos) /**< (DMAC_CHCTRLA) Channel Software Reset Mask */
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#define DMAC_CHCTRLA_SWRST(value) (DMAC_CHCTRLA_SWRST_Msk & ((value) << DMAC_CHCTRLA_SWRST_Pos))
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#define DMAC_CHCTRLA_ENABLE_Pos _U_(1) /**< (DMAC_CHCTRLA) Channel Enable Position */
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#define DMAC_CHCTRLA_ENABLE_Msk (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos) /**< (DMAC_CHCTRLA) Channel Enable Mask */
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#define DMAC_CHCTRLA_ENABLE(value) (DMAC_CHCTRLA_ENABLE_Msk & ((value) << DMAC_CHCTRLA_ENABLE_Pos))
|
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#define DMAC_CHCTRLA_Msk _U_(0x03) /**< (DMAC_CHCTRLA) Register Mask */
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/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
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|
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#define DMAC_CHCTRLB_RESETVALUE _U_(0x00) /**< (DMAC_CHCTRLB) Channel Control B Reset Value */
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|
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#define DMAC_CHCTRLB_EVACT_Pos _U_(0) /**< (DMAC_CHCTRLB) Event Input Action Position */
|
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#define DMAC_CHCTRLB_EVACT_Msk (_U_(0x7) << DMAC_CHCTRLB_EVACT_Pos) /**< (DMAC_CHCTRLB) Event Input Action Mask */
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|
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#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))
|
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|
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#define DMAC_CHCTRLB_EVACT_NOACT_Val _U_(0x0) /**< (DMAC_CHCTRLB) No action */
|
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|
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#define DMAC_CHCTRLB_EVACT_TRIG_Val _U_(0x1) /**< (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
|
||
|
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#define DMAC_CHCTRLB_EVACT_CTRIG_Val _U_(0x2) /**< (DMAC_CHCTRLB) Conditional transfer trigger */
|
||
|
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#define DMAC_CHCTRLB_EVACT_CBLOCK_Val _U_(0x3) /**< (DMAC_CHCTRLB) Conditional block transfer */
|
||
|
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#define DMAC_CHCTRLB_EVACT_SUSPEND_Val _U_(0x4) /**< (DMAC_CHCTRLB) Channel suspend operation */
|
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|
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#define DMAC_CHCTRLB_EVACT_RESUME_Val _U_(0x5) /**< (DMAC_CHCTRLB) Channel resume operation */
|
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|
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#define DMAC_CHCTRLB_EVACT_SSKIP_Val _U_(0x6) /**< (DMAC_CHCTRLB) Skip next block suspend action */
|
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|
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#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) /**< (DMAC_CHCTRLB) No action Position */
|
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|
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#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) /**< (DMAC_CHCTRLB) Transfer and periodic transfer trigger Position */
|
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|
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#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) /**< (DMAC_CHCTRLB) Conditional transfer trigger Position */
|
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|
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#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) /**< (DMAC_CHCTRLB) Conditional block transfer Position */
|
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|
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#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) /**< (DMAC_CHCTRLB) Channel suspend operation Position */
|
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|
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#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) /**< (DMAC_CHCTRLB) Channel resume operation Position */
|
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|
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#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) /**< (DMAC_CHCTRLB) Skip next block suspend action Position */
|
||
|
|
#define DMAC_CHCTRLB_EVIE_Pos _U_(3) /**< (DMAC_CHCTRLB) Channel Event Input Enable Position */
|
||
|
|
#define DMAC_CHCTRLB_EVIE_Msk (_U_(0x1) << DMAC_CHCTRLB_EVIE_Pos) /**< (DMAC_CHCTRLB) Channel Event Input Enable Mask */
|
||
|
|
#define DMAC_CHCTRLB_EVIE(value) (DMAC_CHCTRLB_EVIE_Msk & ((value) << DMAC_CHCTRLB_EVIE_Pos))
|
||
|
|
#define DMAC_CHCTRLB_EVOE_Pos _U_(4) /**< (DMAC_CHCTRLB) Channel Event Output Enable Position */
|
||
|
|
#define DMAC_CHCTRLB_EVOE_Msk (_U_(0x1) << DMAC_CHCTRLB_EVOE_Pos) /**< (DMAC_CHCTRLB) Channel Event Output Enable Mask */
|
||
|
|
#define DMAC_CHCTRLB_EVOE(value) (DMAC_CHCTRLB_EVOE_Msk & ((value) << DMAC_CHCTRLB_EVOE_Pos))
|
||
|
|
#define DMAC_CHCTRLB_LVL_Pos _U_(5) /**< (DMAC_CHCTRLB) Channel Arbitration Level Position */
|
||
|
|
#define DMAC_CHCTRLB_LVL_Msk (_U_(0x3) << DMAC_CHCTRLB_LVL_Pos) /**< (DMAC_CHCTRLB) Channel Arbitration Level Mask */
|
||
|
|
#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))
|
||
|
|
#define DMAC_CHCTRLB_LVL_LVL0_Val _U_(0x0) /**< (DMAC_CHCTRLB) Channel Priority Level 0 */
|
||
|
|
#define DMAC_CHCTRLB_LVL_LVL1_Val _U_(0x1) /**< (DMAC_CHCTRLB) Channel Priority Level 1 */
|
||
|
|
#define DMAC_CHCTRLB_LVL_LVL2_Val _U_(0x2) /**< (DMAC_CHCTRLB) Channel Priority Level 2 */
|
||
|
|
#define DMAC_CHCTRLB_LVL_LVL3_Val _U_(0x3) /**< (DMAC_CHCTRLB) Channel Priority Level 3 */
|
||
|
|
#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos) /**< (DMAC_CHCTRLB) Channel Priority Level 0 Position */
|
||
|
|
#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos) /**< (DMAC_CHCTRLB) Channel Priority Level 1 Position */
|
||
|
|
#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos) /**< (DMAC_CHCTRLB) Channel Priority Level 2 Position */
|
||
|
|
#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos) /**< (DMAC_CHCTRLB) Channel Priority Level 3 Position */
|
||
|
|
#define DMAC_CHCTRLB_TRIGSRC_Pos _U_(8) /**< (DMAC_CHCTRLB) Peripheral Trigger Source Position */
|
||
|
|
#define DMAC_CHCTRLB_TRIGSRC_Msk (_U_(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos) /**< (DMAC_CHCTRLB) Peripheral Trigger Source Mask */
|
||
|
|
#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))
|
||
|
|
#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U_(0x0) /**< (DMAC_CHCTRLB) Only software/event triggers */
|
||
|
|
#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) /**< (DMAC_CHCTRLB) Only software/event triggers Position */
|
||
|
|
#define DMAC_CHCTRLB_TRIGACT_Pos _U_(22) /**< (DMAC_CHCTRLB) Trigger Action Position */
|
||
|
|
#define DMAC_CHCTRLB_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLB_TRIGACT_Pos) /**< (DMAC_CHCTRLB) Trigger Action Mask */
|
||
|
|
#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))
|
||
|
|
#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val _U_(0x0) /**< (DMAC_CHCTRLB) One trigger required for each block transfer */
|
||
|
|
#define DMAC_CHCTRLB_TRIGACT_BEAT_Val _U_(0x2) /**< (DMAC_CHCTRLB) One trigger required for each beat transfer */
|
||
|
|
#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U_(0x3) /**< (DMAC_CHCTRLB) One trigger required for each transaction */
|
||
|
|
#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) /**< (DMAC_CHCTRLB) One trigger required for each block transfer Position */
|
||
|
|
#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) /**< (DMAC_CHCTRLB) One trigger required for each beat transfer Position */
|
||
|
|
#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) /**< (DMAC_CHCTRLB) One trigger required for each transaction Position */
|
||
|
|
#define DMAC_CHCTRLB_CMD_Pos _U_(24) /**< (DMAC_CHCTRLB) Software Command Position */
|
||
|
|
#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos) /**< (DMAC_CHCTRLB) Software Command Mask */
|
||
|
|
#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
|
||
|
|
#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< (DMAC_CHCTRLB) No action */
|
||
|
|
#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< (DMAC_CHCTRLB) Channel suspend operation */
|
||
|
|
#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< (DMAC_CHCTRLB) Channel resume operation */
|
||
|
|
#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) /**< (DMAC_CHCTRLB) No action Position */
|
||
|
|
#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) /**< (DMAC_CHCTRLB) Channel suspend operation Position */
|
||
|
|
#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) /**< (DMAC_CHCTRLB) Channel resume operation Position */
|
||
|
|
#define DMAC_CHCTRLB_Msk _U_(0x03C03F7F) /**< (DMAC_CHCTRLB) Register Mask */
|
||
|
|
|
||
|
|
|
||
|
|
/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
|
||
|
|
#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< (DMAC_CHINTENCLR) Channel Interrupt Enable Clear Reset Value */
|
||
|
|
|
||
|
|
#define DMAC_CHINTENCLR_TERR_Pos _U_(0) /**< (DMAC_CHINTENCLR) Transfer Error Interrupt Enable Position */
|
||
|
|
#define DMAC_CHINTENCLR_TERR_Msk (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos) /**< (DMAC_CHINTENCLR) Transfer Error Interrupt Enable Mask */
|
||
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#define DMAC_CHINTENCLR_TERR(value) (DMAC_CHINTENCLR_TERR_Msk & ((value) << DMAC_CHINTENCLR_TERR_Pos))
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#define DMAC_CHINTENCLR_TCMPL_Pos _U_(1) /**< (DMAC_CHINTENCLR) Transfer Complete Interrupt Enable Position */
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#define DMAC_CHINTENCLR_TCMPL_Msk (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) /**< (DMAC_CHINTENCLR) Transfer Complete Interrupt Enable Mask */
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#define DMAC_CHINTENCLR_TCMPL(value) (DMAC_CHINTENCLR_TCMPL_Msk & ((value) << DMAC_CHINTENCLR_TCMPL_Pos))
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#define DMAC_CHINTENCLR_SUSP_Pos _U_(2) /**< (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable Position */
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#define DMAC_CHINTENCLR_SUSP_Msk (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos) /**< (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable Mask */
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#define DMAC_CHINTENCLR_SUSP(value) (DMAC_CHINTENCLR_SUSP_Msk & ((value) << DMAC_CHINTENCLR_SUSP_Pos))
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#define DMAC_CHINTENCLR_Msk _U_(0x07) /**< (DMAC_CHINTENCLR) Register Mask */
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/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
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#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< (DMAC_CHINTENSET) Channel Interrupt Enable Set Reset Value */
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#define DMAC_CHINTENSET_TERR_Pos _U_(0) /**< (DMAC_CHINTENSET) Transfer Error Interrupt Enable Position */
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#define DMAC_CHINTENSET_TERR_Msk (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos) /**< (DMAC_CHINTENSET) Transfer Error Interrupt Enable Mask */
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#define DMAC_CHINTENSET_TERR(value) (DMAC_CHINTENSET_TERR_Msk & ((value) << DMAC_CHINTENSET_TERR_Pos))
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#define DMAC_CHINTENSET_TCMPL_Pos _U_(1) /**< (DMAC_CHINTENSET) Transfer Complete Interrupt Enable Position */
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#define DMAC_CHINTENSET_TCMPL_Msk (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos) /**< (DMAC_CHINTENSET) Transfer Complete Interrupt Enable Mask */
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#define DMAC_CHINTENSET_TCMPL(value) (DMAC_CHINTENSET_TCMPL_Msk & ((value) << DMAC_CHINTENSET_TCMPL_Pos))
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#define DMAC_CHINTENSET_SUSP_Pos _U_(2) /**< (DMAC_CHINTENSET) Channel Suspend Interrupt Enable Position */
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#define DMAC_CHINTENSET_SUSP_Msk (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos) /**< (DMAC_CHINTENSET) Channel Suspend Interrupt Enable Mask */
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#define DMAC_CHINTENSET_SUSP(value) (DMAC_CHINTENSET_SUSP_Msk & ((value) << DMAC_CHINTENSET_SUSP_Pos))
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#define DMAC_CHINTENSET_Msk _U_(0x07) /**< (DMAC_CHINTENSET) Register Mask */
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/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
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#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< (DMAC_CHINTFLAG) Channel Interrupt Flag Status and Clear Reset Value */
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#define DMAC_CHINTFLAG_TERR_Pos _U_(0) /**< (DMAC_CHINTFLAG) Transfer Error Position */
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#define DMAC_CHINTFLAG_TERR_Msk (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos) /**< (DMAC_CHINTFLAG) Transfer Error Mask */
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#define DMAC_CHINTFLAG_TERR(value) (DMAC_CHINTFLAG_TERR_Msk & ((value) << DMAC_CHINTFLAG_TERR_Pos))
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#define DMAC_CHINTFLAG_TCMPL_Pos _U_(1) /**< (DMAC_CHINTFLAG) Transfer Complete Position */
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#define DMAC_CHINTFLAG_TCMPL_Msk (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) /**< (DMAC_CHINTFLAG) Transfer Complete Mask */
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#define DMAC_CHINTFLAG_TCMPL(value) (DMAC_CHINTFLAG_TCMPL_Msk & ((value) << DMAC_CHINTFLAG_TCMPL_Pos))
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#define DMAC_CHINTFLAG_SUSP_Pos _U_(2) /**< (DMAC_CHINTFLAG) Channel Suspend Position */
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#define DMAC_CHINTFLAG_SUSP_Msk (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos) /**< (DMAC_CHINTFLAG) Channel Suspend Mask */
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#define DMAC_CHINTFLAG_SUSP(value) (DMAC_CHINTFLAG_SUSP_Msk & ((value) << DMAC_CHINTFLAG_SUSP_Pos))
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#define DMAC_CHINTFLAG_Msk _U_(0x07) /**< (DMAC_CHINTFLAG) Register Mask */
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/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) ( R/ 8) Channel Status -------- */
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#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< (DMAC_CHSTATUS) Channel Status Reset Value */
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#define DMAC_CHSTATUS_PEND_Pos _U_(0) /**< (DMAC_CHSTATUS) Channel Pending Position */
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#define DMAC_CHSTATUS_PEND_Msk (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos) /**< (DMAC_CHSTATUS) Channel Pending Mask */
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#define DMAC_CHSTATUS_PEND(value) (DMAC_CHSTATUS_PEND_Msk & ((value) << DMAC_CHSTATUS_PEND_Pos))
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#define DMAC_CHSTATUS_BUSY_Pos _U_(1) /**< (DMAC_CHSTATUS) Channel Busy Position */
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#define DMAC_CHSTATUS_BUSY_Msk (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos) /**< (DMAC_CHSTATUS) Channel Busy Mask */
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#define DMAC_CHSTATUS_BUSY(value) (DMAC_CHSTATUS_BUSY_Msk & ((value) << DMAC_CHSTATUS_BUSY_Pos))
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#define DMAC_CHSTATUS_FERR_Pos _U_(2) /**< (DMAC_CHSTATUS) Fetch Error Position */
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#define DMAC_CHSTATUS_FERR_Msk (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos) /**< (DMAC_CHSTATUS) Fetch Error Mask */
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#define DMAC_CHSTATUS_FERR(value) (DMAC_CHSTATUS_FERR_Msk & ((value) << DMAC_CHSTATUS_FERR_Pos))
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#define DMAC_CHSTATUS_Msk _U_(0x07) /**< (DMAC_CHSTATUS) Register Mask */
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/** \brief DMAC register offsets definitions */
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#define DMAC_BTCTRL_REG_OFST (0x00) /**< (DMAC_BTCTRL) Block Transfer Control Offset */
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#define DMAC_BTCNT_REG_OFST (0x02) /**< (DMAC_BTCNT) Block Transfer Count Offset */
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#define DMAC_SRCADDR_REG_OFST (0x04) /**< (DMAC_SRCADDR) Transfer Source Address Offset */
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#define DMAC_DSTADDR_REG_OFST (0x08) /**< (DMAC_DSTADDR) Transfer Destination Address Offset */
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#define DMAC_DESCADDR_REG_OFST (0x0C) /**< (DMAC_DESCADDR) Next Descriptor Address Offset */
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#define DMAC_CTRL_REG_OFST (0x00) /**< (DMAC_CTRL) Control Offset */
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#define DMAC_CRCCTRL_REG_OFST (0x02) /**< (DMAC_CRCCTRL) CRC Control Offset */
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#define DMAC_CRCDATAIN_REG_OFST (0x04) /**< (DMAC_CRCDATAIN) CRC Data Input Offset */
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#define DMAC_CRCCHKSUM_REG_OFST (0x08) /**< (DMAC_CRCCHKSUM) CRC Checksum Offset */
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#define DMAC_CRCSTATUS_REG_OFST (0x0C) /**< (DMAC_CRCSTATUS) CRC Status Offset */
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#define DMAC_DBGCTRL_REG_OFST (0x0D) /**< (DMAC_DBGCTRL) Debug Control Offset */
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#define DMAC_QOSCTRL_REG_OFST (0x0E) /**< (DMAC_QOSCTRL) QOS Control Offset */
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#define DMAC_SWTRIGCTRL_REG_OFST (0x10) /**< (DMAC_SWTRIGCTRL) Software Trigger Control Offset */
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#define DMAC_PRICTRL0_REG_OFST (0x14) /**< (DMAC_PRICTRL0) Priority Control 0 Offset */
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#define DMAC_INTPEND_REG_OFST (0x20) /**< (DMAC_INTPEND) Interrupt Pending Offset */
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#define DMAC_INTSTATUS_REG_OFST (0x24) /**< (DMAC_INTSTATUS) Interrupt Status Offset */
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#define DMAC_BUSYCH_REG_OFST (0x28) /**< (DMAC_BUSYCH) Busy Channels Offset */
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#define DMAC_PENDCH_REG_OFST (0x2C) /**< (DMAC_PENDCH) Pending Channels Offset */
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#define DMAC_ACTIVE_REG_OFST (0x30) /**< (DMAC_ACTIVE) Active Channel and Levels Offset */
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#define DMAC_BASEADDR_REG_OFST (0x34) /**< (DMAC_BASEADDR) Descriptor Memory Section Base Address Offset */
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#define DMAC_WRBADDR_REG_OFST (0x38) /**< (DMAC_WRBADDR) Write-Back Memory Section Base Address Offset */
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#define DMAC_CHID_REG_OFST (0x3F) /**< (DMAC_CHID) Channel ID Offset */
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#define DMAC_CHCTRLA_REG_OFST (0x40) /**< (DMAC_CHCTRLA) Channel Control A Offset */
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#define DMAC_CHCTRLB_REG_OFST (0x44) /**< (DMAC_CHCTRLB) Channel Control B Offset */
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#define DMAC_CHINTENCLR_REG_OFST (0x4C) /**< (DMAC_CHINTENCLR) Channel Interrupt Enable Clear Offset */
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#define DMAC_CHINTENSET_REG_OFST (0x4D) /**< (DMAC_CHINTENSET) Channel Interrupt Enable Set Offset */
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#define DMAC_CHINTFLAG_REG_OFST (0x4E) /**< (DMAC_CHINTFLAG) Channel Interrupt Flag Status and Clear Offset */
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#define DMAC_CHSTATUS_REG_OFST (0x4F) /**< (DMAC_CHSTATUS) Channel Status Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief DMAC_DESCRIPTOR register API structure */
|
||
|
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typedef struct
|
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|
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{ /* Direct Memory Access Controller */
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__IO uint16_t DMAC_BTCTRL; /**< Offset: 0x00 (R/W 16) Block Transfer Control */
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__IO uint16_t DMAC_BTCNT; /**< Offset: 0x02 (R/W 16) Block Transfer Count */
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__IO uint32_t DMAC_SRCADDR; /**< Offset: 0x04 (R/W 32) Transfer Source Address */
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__IO uint32_t DMAC_DSTADDR; /**< Offset: 0x08 (R/W 32) Transfer Destination Address */
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__IO uint32_t DMAC_DESCADDR; /**< Offset: 0x0C (R/W 32) Next Descriptor Address */
|
||
|
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} dmac_descriptor_registers_t
|
||
|
|
#ifdef __GNUC__
|
||
|
|
__attribute__ ((aligned (8)))
|
||
|
|
#endif
|
||
|
|
;
|
||
|
|
|
||
|
|
/** \brief DMAC register API structure */
|
||
|
|
typedef struct
|
||
|
|
{ /* Direct Memory Access Controller */
|
||
|
|
__IO uint16_t DMAC_CTRL; /**< Offset: 0x00 (R/W 16) Control */
|
||
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__IO uint16_t DMAC_CRCCTRL; /**< Offset: 0x02 (R/W 16) CRC Control */
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__IO uint32_t DMAC_CRCDATAIN; /**< Offset: 0x04 (R/W 32) CRC Data Input */
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__IO uint32_t DMAC_CRCCHKSUM; /**< Offset: 0x08 (R/W 32) CRC Checksum */
|
||
|
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__IO uint8_t DMAC_CRCSTATUS; /**< Offset: 0x0C (R/W 8) CRC Status */
|
||
|
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__IO uint8_t DMAC_DBGCTRL; /**< Offset: 0x0D (R/W 8) Debug Control */
|
||
|
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__IO uint8_t DMAC_QOSCTRL; /**< Offset: 0x0E (R/W 8) QOS Control */
|
||
|
|
__I uint8_t Reserved1[0x01];
|
||
|
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__IO uint32_t DMAC_SWTRIGCTRL; /**< Offset: 0x10 (R/W 32) Software Trigger Control */
|
||
|
|
__IO uint32_t DMAC_PRICTRL0; /**< Offset: 0x14 (R/W 32) Priority Control 0 */
|
||
|
|
__I uint8_t Reserved2[0x08];
|
||
|
|
__IO uint16_t DMAC_INTPEND; /**< Offset: 0x20 (R/W 16) Interrupt Pending */
|
||
|
|
__I uint8_t Reserved3[0x02];
|
||
|
|
__I uint32_t DMAC_INTSTATUS; /**< Offset: 0x24 (R/ 32) Interrupt Status */
|
||
|
|
__I uint32_t DMAC_BUSYCH; /**< Offset: 0x28 (R/ 32) Busy Channels */
|
||
|
|
__I uint32_t DMAC_PENDCH; /**< Offset: 0x2C (R/ 32) Pending Channels */
|
||
|
|
__I uint32_t DMAC_ACTIVE; /**< Offset: 0x30 (R/ 32) Active Channel and Levels */
|
||
|
|
__IO uint32_t DMAC_BASEADDR; /**< Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
|
||
|
|
__IO uint32_t DMAC_WRBADDR; /**< Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
|
||
|
|
__I uint8_t Reserved4[0x03];
|
||
|
|
__IO uint8_t DMAC_CHID; /**< Offset: 0x3F (R/W 8) Channel ID */
|
||
|
|
__IO uint8_t DMAC_CHCTRLA; /**< Offset: 0x40 (R/W 8) Channel Control A */
|
||
|
|
__I uint8_t Reserved5[0x03];
|
||
|
|
__IO uint32_t DMAC_CHCTRLB; /**< Offset: 0x44 (R/W 32) Channel Control B */
|
||
|
|
__I uint8_t Reserved6[0x04];
|
||
|
|
__IO uint8_t DMAC_CHINTENCLR; /**< Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
|
||
|
|
__IO uint8_t DMAC_CHINTENSET; /**< Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
|
||
|
|
__IO uint8_t DMAC_CHINTFLAG; /**< Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
|
||
|
|
__I uint8_t DMAC_CHSTATUS; /**< Offset: 0x4F (R/ 8) Channel Status */
|
||
|
|
} dmac_registers_t;
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||
|
|
/** \brief DMAC_DESCRIPTOR memory section attribute */
|
||
|
|
#define SECTION_DMAC_DESCRIPTOR
|
||
|
|
|
||
|
|
#endif /* _SAMD21_DMAC_COMPONENT_H_ */
|